X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Ffr30-opc.c;h=b47cbcd1d6fdb00458bf37c55455bd2890bc8865;hb=d943fe33c64a06a950c92ba6db28e65977b87767;hp=302100dfc643daba00ae4d4875ef03f00a461dd1;hpb=ed288bb597072176e84fc8279707a3f2f475779b;p=deliverable%2Fbinutils-gdb.git

diff --git a/opcodes/fr30-opc.c b/opcodes/fr30-opc.c
index 302100dfc6..b47cbcd1d6 100644
--- a/opcodes/fr30-opc.c
+++ b/opcodes/fr30-opc.c
@@ -2,7 +2,7 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
 
 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
 
@@ -28,6 +28,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 #include "symcat.h"
 #include "fr30-desc.h"
 #include "fr30-opc.h"
+#include "libiberty.h"
 
 /* The hash functions are recorded here to help keep assembler code out of
    the disassembler and vice versa.  */
@@ -39,133 +40,144 @@ static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
 
 /* Instruction formats.  */
 
-#define F(f) & fr30_cgen_ifld_table[CONCAT2 (FR30_,f)]
-
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define F(f) & fr30_cgen_ifld_table[FR30_##f]
+#else
+#define F(f) & fr30_cgen_ifld_table[FR30_/**/f]
+#endif
 static const CGEN_IFMT ifmt_empty = {
-  0, 0, 0x0, { 0 }
+  0, 0, 0x0, { { 0 } }
 };
 
 static const CGEN_IFMT ifmt_add = {
-  16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RJ), F (F_RI), 0 }
+  16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_RJ) }, { F (F_RI) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_addi = {
-  16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U4), F (F_RI), 0 }
+  16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_U4) }, { F (F_RI) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_add2 = {
-  16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_M4), F (F_RI), 0 }
+  16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_M4) }, { F (F_RI) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_div0s = {
-  16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RI), 0 }
+  16, 16, 0xfff0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_RI) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_div3 = {
-  16, 16, 0xffff, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_OP4), 0 }
+  16, 16, 0xffff, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_OP4) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_ldi8 = {
-  16, 16, 0xf000, { F (F_OP1), F (F_I8), F (F_RI), 0 }
+  16, 16, 0xf000, { { F (F_OP1) }, { F (F_I8) }, { F (F_RI) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_ldi20 = {
-  16, 32, 0xff00, { F (F_OP1), F (F_I20), F (F_OP2), F (F_RI), 0 }
+  16, 32, 0xff00, { { F (F_OP1) }, { F (F_I20) }, { F (F_OP2) }, { F (F_RI) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_ldi32 = {
-  16, 48, 0xfff0, { F (F_OP1), F (F_I32), F (F_OP2), F (F_OP3), F (F_RI), 0 }
+  16, 48, 0xfff0, { { F (F_OP1) }, { F (F_I32) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_RI) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_ldr14 = {
-  16, 16, 0xf000, { F (F_OP1), F (F_DISP10), F (F_RI), 0 }
+  16, 16, 0xf000, { { F (F_OP1) }, { F (F_DISP10) }, { F (F_RI) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_ldr14uh = {
-  16, 16, 0xf000, { F (F_OP1), F (F_DISP9), F (F_RI), 0 }
+  16, 16, 0xf000, { { F (F_OP1) }, { F (F_DISP9) }, { F (F_RI) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_ldr14ub = {
-  16, 16, 0xf000, { F (F_OP1), F (F_DISP8), F (F_RI), 0 }
+  16, 16, 0xf000, { { F (F_OP1) }, { F (F_DISP8) }, { F (F_RI) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_ldr15 = {
-  16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_UDISP6), F (F_RI), 0 }
+  16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_UDISP6) }, { F (F_RI) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_ldr15dr = {
-  16, 16, 0xfff0, { F (F_OP1), F (F_OP2), F (F_OP3), F (F_RS2), 0 }
+  16, 16, 0xfff0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_RS2) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_movdr = {
-  16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_RS1), F (F_RI), 0 }
+  16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_RS1) }, { F (F_RI) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_call = {
-  16, 16, 0xf800, { F (F_OP1), F (F_OP5), F (F_REL12), 0 }
+  16, 16, 0xf800, { { F (F_OP1) }, { F (F_OP5) }, { F (F_REL12) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_int = {
-  16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U8), 0 }
+  16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_U8) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_brad = {
-  16, 16, 0xff00, { F (F_OP1), F (F_CC), F (F_REL9), 0 }
+  16, 16, 0xff00, { { F (F_OP1) }, { F (F_CC) }, { F (F_REL9) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_dmovr13 = {
-  16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR10), 0 }
+  16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_DIR10) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_dmovr13h = {
-  16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR9), 0 }
+  16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_DIR9) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_dmovr13b = {
-  16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_DIR8), 0 }
+  16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_DIR8) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_copop = {
-  16, 32, 0xfff0, { F (F_OP1), F (F_CCC), F (F_OP2), F (F_OP3), F (F_CRJ), F (F_U4C), F (F_CRI), 0 }
+  16, 32, 0xfff0, { { F (F_OP1) }, { F (F_CCC) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_CRJ) }, { F (F_U4C) }, { F (F_CRI) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_copld = {
-  16, 32, 0xfff0, { F (F_OP1), F (F_CCC), F (F_OP2), F (F_OP3), F (F_RJC), F (F_U4C), F (F_CRI), 0 }
+  16, 32, 0xfff0, { { F (F_OP1) }, { F (F_CCC) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_RJC) }, { F (F_U4C) }, { F (F_CRI) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_copst = {
-  16, 32, 0xfff0, { F (F_OP1), F (F_CCC), F (F_OP2), F (F_OP3), F (F_CRJ), F (F_U4C), F (F_RIC), 0 }
+  16, 32, 0xfff0, { { F (F_OP1) }, { F (F_CCC) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_CRJ) }, { F (F_U4C) }, { F (F_RIC) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_addsp = {
-  16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_S10), 0 }
+  16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_S10) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_ldm0 = {
-  16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_REGLIST_LOW_LD), 0 }
+  16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_REGLIST_LOW_LD) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_ldm1 = {
-  16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_REGLIST_HI_LD), 0 }
+  16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_REGLIST_HI_LD) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_stm0 = {
-  16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_REGLIST_LOW_ST), 0 }
+  16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_REGLIST_LOW_ST) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_stm1 = {
-  16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_REGLIST_HI_ST), 0 }
+  16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_REGLIST_HI_ST) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_enter = {
-  16, 16, 0xff00, { F (F_OP1), F (F_OP2), F (F_U10), 0 }
+  16, 16, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_U10) }, { 0 } }
 };
 
 #undef F
 
-#define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define A(a) (1 << CGEN_INSN_##a)
+#else
+#define A(a) (1 << CGEN_INSN_/**/a)
+#endif
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define OPERAND(op) FR30_OPERAND_##op
+#else
+#define OPERAND(op) FR30_OPERAND_/**/op
+#endif
 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
-#define OPERAND(op) CONCAT2 (FR30_OPERAND_,op)
 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
 
 /* The instruction table.  */
@@ -175,7 +187,7 @@ static const CGEN_OPCODE fr30_cgen_insn_opcode_table[MAX_INSNS] =
   /* Special null first entry.
      A `num' value of zero is thus invalid.
      Also, the special `invalid' insn resides here.  */
-  { { 0 } },
+  { { 0, 0, 0, 0 }, {{0}}, 0, {0}},
 /* add $Rj,$Ri */
   {
     { 0, 0, 0, 0 },
@@ -1169,33 +1181,44 @@ static const CGEN_OPCODE fr30_cgen_insn_opcode_table[MAX_INSNS] =
 };
 
 #undef A
-#undef MNEM
 #undef OPERAND
+#undef MNEM
 #undef OP
 
 /* Formats for ALIAS macro-insns.  */
 
-#define F(f) & fr30_cgen_ifld_table[CONCAT2 (FR30_,f)]
-
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define F(f) & fr30_cgen_ifld_table[FR30_##f]
+#else
+#define F(f) & fr30_cgen_ifld_table[FR30_/**/f]
+#endif
 static const CGEN_IFMT ifmt_ldi8m = {
-  16, 16, 0xf000, { F (F_OP1), F (F_I8), F (F_RI), 0 }
+  16, 16, 0xf000, { { F (F_OP1) }, { F (F_I8) }, { F (F_RI) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_ldi20m = {
-  16, 32, 0xff00, { F (F_OP1), F (F_I20), F (F_OP2), F (F_RI), 0 }
+  16, 32, 0xff00, { { F (F_OP1) }, { F (F_OP2) }, { F (F_RI) }, { F (F_I20) }, { 0 } }
 };
 
 static const CGEN_IFMT ifmt_ldi32m = {
-  16, 48, 0xfff0, { F (F_OP1), F (F_I32), F (F_OP2), F (F_OP3), F (F_RI), 0 }
+  16, 48, 0xfff0, { { F (F_OP1) }, { F (F_OP2) }, { F (F_OP3) }, { F (F_RI) }, { F (F_I32) }, { 0 } }
 };
 
 #undef F
 
 /* Each non-simple macro entry points to an array of expansion possibilities.  */
 
-#define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define A(a) (1 << CGEN_INSN_##a)
+#else
+#define A(a) (1 << CGEN_INSN_/**/a)
+#endif
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define OPERAND(op) FR30_OPERAND_##op
+#else
+#define OPERAND(op) FR30_OPERAND_/**/op
+#endif
 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
-#define OPERAND(op) CONCAT2 (FR30_OPERAND_,op)
 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
 
 /* The macro instruction table.  */
@@ -1244,8 +1267,8 @@ static const CGEN_OPCODE fr30_cgen_macro_insn_opcode_table[] =
 };
 
 #undef A
-#undef MNEM
 #undef OPERAND
+#undef MNEM
 #undef OP
 
 #ifndef CGEN_ASM_HASH_P
@@ -1261,7 +1284,7 @@ static const CGEN_OPCODE fr30_cgen_macro_insn_opcode_table[] =
 
 static int
 asm_hash_insn_p (insn)
-     const CGEN_INSN *insn;
+     const CGEN_INSN *insn ATTRIBUTE_UNUSED;
 {
   return CGEN_ASM_HASH_P (insn);
 }
@@ -1311,12 +1334,14 @@ asm_hash_insn (mnem)
 
 static unsigned int
 dis_hash_insn (buf, value)
-     const char * buf;
-     CGEN_INSN_INT value;
+     const char * buf ATTRIBUTE_UNUSED;
+     CGEN_INSN_INT value ATTRIBUTE_UNUSED;
 {
   return CGEN_DIS_HASH (buf, value);
 }
 
+static void set_fields_bitsize PARAMS ((CGEN_FIELDS *, int));
+
 /* Set the recorded length of the insn in the CGEN_FIELDS struct.  */
 
 static void
@@ -1345,6 +1370,7 @@ fr30_cgen_init_opcode_table (cd)
     {
       insns[i].base = &ib[i];
       insns[i].opcode = &oc[i];
+      fr30_cgen_build_insn_regex (& insns[i]);
     }
   cd->macro_insn_table.init_entries = insns;
   cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE);
@@ -1353,7 +1379,10 @@ fr30_cgen_init_opcode_table (cd)
   oc = & fr30_cgen_insn_opcode_table[0];
   insns = (CGEN_INSN *) cd->insn_table.init_entries;
   for (i = 0; i < MAX_INSNS; ++i)
-    insns[i].opcode = &oc[i];
+    {
+      insns[i].opcode = &oc[i];
+      fr30_cgen_build_insn_regex (& insns[i]);
+    }
 
   cd->sizeof_fields = sizeof (CGEN_FIELDS);
   cd->set_fields_bitsize = set_fields_bitsize;