X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Ffrv-opc.c;h=e7107a8ba2a40d3f59a16864c05c839aa690ffff;hb=9ccb8af972518810c66317c6c942d2268bfb5123;hp=8da1596c4e0c7ea0da63ebdf3db8c8a4796ae9ab;hpb=87337981d937b6b00c55827ea15438e19c518884;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/frv-opc.c b/opcodes/frv-opc.c index 8da1596c4e..e7107a8ba2 100644 --- a/opcodes/frv-opc.c +++ b/opcodes/frv-opc.c @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996-2009 Free Software Foundation, Inc. +Copyright 1996-2010 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. @@ -34,6 +34,9 @@ This file is part of the GNU Binutils and/or GDB, the GNU debugger. #include "elf/frv.h" #include +/* DEBUG appears below as argument of OP macro. */ +#undef DEBUG + /* Returns TRUE if {MAJOR,MACH} is a major branch of the FRV development tree. */ @@ -795,7 +798,7 @@ check_insn_major_constraints (FRV_VLIW *vliw, int frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn) { - int index; + int slot_index; CGEN_ATTR_VALUE_ENUM_TYPE major; CGEN_ATTR_VALUE_ENUM_TYPE unit; VLIW_COMBO *new_vliw; @@ -803,8 +806,8 @@ frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn) if (vliw->constraint_violation || CGEN_INSN_INVALID_P (insn)) return 1; - index = vliw->next_slot; - if (index >= FRV_VLIW_SIZE) + slot_index = vliw->next_slot; + if (slot_index >= FRV_VLIW_SIZE) return 1; unit = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_UNIT); @@ -831,7 +834,7 @@ frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn) break; } - if (index <= 0) + if (slot_index <= 0) { /* Any insn can be added to slot 0. */ while (! match_unit (vliw, unit, (*vliw->current_vliw)[0])) @@ -851,8 +854,8 @@ frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn) if (new_vliw && check_insn_major_constraints (vliw, major, insn)) { vliw->current_vliw = new_vliw; - vliw->major[index] = major; - vliw->insn[index] = insn; + vliw->major[slot_index] = major; + vliw->insn[slot_index] = insn; vliw->next_slot++; return 0; } @@ -886,11 +889,7 @@ static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT); /* Instruction formats. */ -#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) #define F(f) & frv_cgen_ifld_table[FRV_##f] -#else -#define F(f) & frv_cgen_ifld_table[FRV_/**/f] -#endif static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = { 0, 0, 0x0, { { 0 } } }; @@ -1501,16 +1500,8 @@ static const CGEN_IFMT ifmt_fnop ATTRIBUTE_UNUSED = { #undef F -#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) #define A(a) (1 << CGEN_INSN_##a) -#else -#define A(a) (1 << CGEN_INSN_/**/a) -#endif -#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) #define OPERAND(op) FRV_OPERAND_##op -#else -#define OPERAND(op) FRV_OPERAND_/**/op -#endif #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) @@ -5989,11 +5980,7 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] = /* Formats for ALIAS macro-insns. */ -#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) #define F(f) & frv_cgen_ifld_table[FRV_##f] -#else -#define F(f) & frv_cgen_ifld_table[FRV_/**/f] -#endif static const CGEN_IFMT ifmt_nop ATTRIBUTE_UNUSED = { 32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_D12) }, { 0 } } }; @@ -6026,16 +6013,8 @@ static const CGEN_IFMT ifmt_cmov ATTRIBUTE_UNUSED = { /* Each non-simple macro entry points to an array of expansion possibilities. */ -#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) #define A(a) (1 << CGEN_INSN_##a) -#else -#define A(a) (1 << CGEN_INSN_/**/a) -#endif -#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) #define OPERAND(op) FRV_OPERAND_##op -#else -#define OPERAND(op) FRV_OPERAND_/**/op -#endif #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))