X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Fi386-dis.c;h=108f0e3b236581f236911cb6667683618ba35b8e;hb=1b3cee563cafa73340314bbf32e4218dead72718;hp=ca9ea2deb4e327117101392171c58bd0c95dd295;hpb=3888916da84288994be10d6ae1a2db5b45b3f8f8;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index ca9ea2deb4..108f0e3b23 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -1,5 +1,5 @@ /* Print i386 instructions for GDB, the GNU debugger. - Copyright (C) 1988-2015 Free Software Foundation, Inc. + Copyright (C) 1988-2017 Free Software Foundation, Inc. This file is part of the GNU opcodes library. @@ -102,6 +102,7 @@ static void VPCMP_Fixup (int, int); static void OP_0f07 (int, int); static void OP_Monitor (int, int); static void OP_Mwait (int, int); +static void OP_Mwaitx (int, int); static void NOP_Fixup1 (int, int); static void NOP_Fixup2 (int, int); static void OP_3DNowSuffix (int, int); @@ -222,12 +223,6 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) } /* Possible values for prefix requirement. */ -#define PREFIX_UD_SHIFT 8 -#define PREFIX_UD_REPZ (PREFIX_REPZ << PREFIX_UD_SHIFT) -#define PREFIX_UD_REPNZ (PREFIX_REPNZ << PREFIX_UD_SHIFT) -#define PREFIX_UD_DATA (PREFIX_DATA << PREFIX_UD_SHIFT) -#define PREFIX_UD_ADDR (PREFIX_ADDR << PREFIX_UD_SHIFT) -#define PREFIX_UD_LOCK (PREFIX_LOCK << PREFIX_UD_SHIFT) #define PREFIX_IGNORED_SHIFT 16 #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT) #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT) @@ -257,13 +252,12 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define Ed { OP_E, d_mode } #define Edq { OP_E, dq_mode } #define Edqw { OP_E, dqw_mode } -#define EdqwS { OP_E, dqw_swap_mode } #define Edqb { OP_E, dqb_mode } #define Edb { OP_E, db_mode } #define Edw { OP_E, dw_mode } #define Edqd { OP_E, dqd_mode } #define Eq { OP_E, q_mode } -#define indirEv { OP_indirE, stack_v_mode } +#define indirEv { OP_indirE, indir_v_mode } #define indirEp { OP_indirE, f_mode } #define stackEv { OP_E, stack_v_mode } #define Em { OP_E, m_mode } @@ -561,11 +555,12 @@ enum dq_mode, /* registers like dq_mode, memory like w_mode. */ dqw_mode, - dqw_swap_mode, bnd_mode, /* 4- or 6-byte pointer operand */ f_mode, const_1_mode, + /* v_mode for indirect branch opcodes. */ + indir_v_mode, /* v_mode for stack-related opcodes. */ stack_v_mode, /* non-quad operand size depends on prefixes */ @@ -709,7 +704,7 @@ enum { REG_80 = 0, REG_81, - REG_82, + REG_83, REG_8F, REG_C0, REG_C1, @@ -763,6 +758,7 @@ enum MOD_0F01_REG_1, MOD_0F01_REG_2, MOD_0F01_REG_3, + MOD_0F01_REG_5, MOD_0F01_REG_7, MOD_0F12_PREFIX_0, MOD_0F13, @@ -807,6 +803,7 @@ enum MOD_0FB2, MOD_0FB4, MOD_0FB5, + MOD_0FC3, MOD_0FC7_REG_3, MOD_0FC7_REG_4, MOD_0FC7_REG_5, @@ -824,6 +821,37 @@ enum MOD_VEX_0F16_PREFIX_0, MOD_VEX_0F17, MOD_VEX_0F2B, + MOD_VEX_W_0_0F41_P_0_LEN_1, + MOD_VEX_W_1_0F41_P_0_LEN_1, + MOD_VEX_W_0_0F41_P_2_LEN_1, + MOD_VEX_W_1_0F41_P_2_LEN_1, + MOD_VEX_W_0_0F42_P_0_LEN_1, + MOD_VEX_W_1_0F42_P_0_LEN_1, + MOD_VEX_W_0_0F42_P_2_LEN_1, + MOD_VEX_W_1_0F42_P_2_LEN_1, + MOD_VEX_W_0_0F44_P_0_LEN_1, + MOD_VEX_W_1_0F44_P_0_LEN_1, + MOD_VEX_W_0_0F44_P_2_LEN_1, + MOD_VEX_W_1_0F44_P_2_LEN_1, + MOD_VEX_W_0_0F45_P_0_LEN_1, + MOD_VEX_W_1_0F45_P_0_LEN_1, + MOD_VEX_W_0_0F45_P_2_LEN_1, + MOD_VEX_W_1_0F45_P_2_LEN_1, + MOD_VEX_W_0_0F46_P_0_LEN_1, + MOD_VEX_W_1_0F46_P_0_LEN_1, + MOD_VEX_W_0_0F46_P_2_LEN_1, + MOD_VEX_W_1_0F46_P_2_LEN_1, + MOD_VEX_W_0_0F47_P_0_LEN_1, + MOD_VEX_W_1_0F47_P_0_LEN_1, + MOD_VEX_W_0_0F47_P_2_LEN_1, + MOD_VEX_W_1_0F47_P_2_LEN_1, + MOD_VEX_W_0_0F4A_P_0_LEN_1, + MOD_VEX_W_1_0F4A_P_0_LEN_1, + MOD_VEX_W_0_0F4A_P_2_LEN_1, + MOD_VEX_W_1_0F4A_P_2_LEN_1, + MOD_VEX_W_0_0F4B_P_0_LEN_1, + MOD_VEX_W_1_0F4B_P_0_LEN_1, + MOD_VEX_W_0_0F4B_P_2_LEN_1, MOD_VEX_0F50, MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, @@ -835,6 +863,26 @@ enum MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6, MOD_VEX_0F73_REG_7, + MOD_VEX_W_0_0F91_P_0_LEN_0, + MOD_VEX_W_1_0F91_P_0_LEN_0, + MOD_VEX_W_0_0F91_P_2_LEN_0, + MOD_VEX_W_1_0F91_P_2_LEN_0, + MOD_VEX_W_0_0F92_P_0_LEN_0, + MOD_VEX_W_0_0F92_P_2_LEN_0, + MOD_VEX_W_0_0F92_P_3_LEN_0, + MOD_VEX_W_1_0F92_P_3_LEN_0, + MOD_VEX_W_0_0F93_P_0_LEN_0, + MOD_VEX_W_0_0F93_P_2_LEN_0, + MOD_VEX_W_0_0F93_P_3_LEN_0, + MOD_VEX_W_1_0F93_P_3_LEN_0, + MOD_VEX_W_0_0F98_P_0_LEN_0, + MOD_VEX_W_1_0F98_P_0_LEN_0, + MOD_VEX_W_0_0F98_P_2_LEN_0, + MOD_VEX_W_1_0F98_P_2_LEN_0, + MOD_VEX_W_0_0F99_P_0_LEN_0, + MOD_VEX_W_1_0F99_P_0_LEN_0, + MOD_VEX_W_0_0F99_P_2_LEN_0, + MOD_VEX_W_1_0F99_P_2_LEN_0, MOD_VEX_0FAE_REG_2, MOD_VEX_0FAE_REG_3, MOD_VEX_0FD7_PREFIX_2, @@ -849,6 +897,14 @@ enum MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2, MOD_VEX_0F388E_PREFIX_2, + MOD_VEX_W_0_0F3A30_P_2_LEN_0, + MOD_VEX_W_1_0F3A30_P_2_LEN_0, + MOD_VEX_W_0_0F3A31_P_2_LEN_0, + MOD_VEX_W_1_0F3A31_P_2_LEN_0, + MOD_VEX_W_0_0F3A32_P_2_LEN_0, + MOD_VEX_W_1_0F3A32_P_2_LEN_0, + MOD_VEX_W_0_0F3A33_P_2_LEN_0, + MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3, @@ -874,6 +930,7 @@ enum RM_0F01_REG_1, RM_0F01_REG_2, RM_0F01_REG_3, + RM_0F01_REG_5, RM_0F01_REG_7, RM_0FAE_REG_5, RM_0FAE_REG_6, @@ -925,14 +982,15 @@ enum PREFIX_0FAE_REG_1, PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, + PREFIX_MOD_0_0FAE_REG_4, + PREFIX_MOD_3_0FAE_REG_4, PREFIX_0FAE_REG_6, PREFIX_0FAE_REG_7, - PREFIX_RM_0_0FAE_REG_7, PREFIX_0FB8, PREFIX_0FBC, PREFIX_0FBD, PREFIX_0FC2, - PREFIX_0FC3, + PREFIX_MOD_0_0FC3, PREFIX_MOD_0_0FC7_REG_6, PREFIX_MOD_3_0FC7_REG_6, PREFIX_MOD_3_0FC7_REG_7, @@ -1488,6 +1546,9 @@ enum PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, + PREFIX_EVEX_0F3852, + PREFIX_EVEX_0F3853, + PREFIX_EVEX_0F3855, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, @@ -1632,12 +1693,15 @@ enum X86_64_63, X86_64_6D, X86_64_6F, + X86_64_82, X86_64_9A, X86_64_C4, X86_64_C5, X86_64_CE, X86_64_D4, X86_64_D5, + X86_64_E8, + X86_64_E9, X86_64_EA, X86_64_0F01_REG_0, X86_64_0F01_REG_1, @@ -1648,8 +1712,7 @@ enum enum { THREE_BYTE_0F38 = 0, - THREE_BYTE_0F3A, - THREE_BYTE_0F7A + THREE_BYTE_0F3A }; enum @@ -2315,6 +2378,7 @@ enum EVEX_W_0F3839_P_1, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, + EVEX_W_0F3855_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, @@ -2407,9 +2471,12 @@ struct dis386 { is true 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) 'S' => print 'w', 'l' or 'q' if suffix_always is true - 'T' => print 'q' in 64bit mode and behave as 'P' otherwise - 'U' => print 'q' in 64bit mode and behave as 'Q' otherwise - 'V' => print 'q' in 64bit mode and behave as 'S' otherwise + 'T' => print 'q' in 64bit mode if instruction has no operand size + prefix and behave as 'P' otherwise + 'U' => print 'q' in 64bit mode if instruction has no operand size + prefix and behave as 'Q' otherwise + 'V' => print 'q' in 64bit mode if instruction has no operand size + prefix and behave as 'S' otherwise 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) 'X' => print 's', 'd' depending on data16 prefix (for XMM) 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and @@ -2417,10 +2484,19 @@ struct dis386 { 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise '!' => change condition from true to false or from false to true. '%' => add 1 upper case letter to the macro. + '^' => print 'w' or 'l' depending on operand size prefix or + suffix_always is true (lcall/ljmp). + '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending + on operand size prefix. + '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction + has no operand size prefix for AMD64 ISA, behave as 'P' + otherwise 2 upper case letter macros: - "XY" => print 'x' or 'y' if no register operands or suffix_always - is true. + "XY" => print 'x' or 'y' if suffix_always is true or no register + operands and no broadcast. + "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no + register operands and no broadcast. "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand or suffix_always is true @@ -2586,8 +2662,8 @@ static const struct dis386 dis386[] = { /* 80 */ { REG_TABLE (REG_80) }, { REG_TABLE (REG_81) }, - { Bad_Opcode }, - { REG_TABLE (REG_82) }, + { X86_64_TABLE (X86_64_82) }, + { REG_TABLE (REG_83) }, { "testB", { Eb, Gb }, 0 }, { "testS", { Ev, Gv }, 0 }, { "xchgB", { Ebh2, Gb }, 0 }, @@ -2701,8 +2777,8 @@ static const struct dis386 dis386[] = { { "outB", { Ib, AL }, 0 }, { "outG", { Ib, zAX }, 0 }, /* e8 */ - { "callT", { Jv, BND }, 0 }, - { "jmpT", { Jv, BND }, 0 }, + { X86_64_TABLE (X86_64_E8) }, + { X86_64_TABLE (X86_64_E9) }, { X86_64_TABLE (X86_64_EA) }, { "jmp", { Jb, BND }, 0 }, { "inB", { AL, indirDX }, 0 }, @@ -2868,7 +2944,7 @@ static const struct dis386 dis386_twobyte[] = { /* 78 */ { PREFIX_TABLE (PREFIX_0F78) }, { PREFIX_TABLE (PREFIX_0F79) }, - { THREE_BYTE_TABLE (THREE_BYTE_0F7A) }, + { Bad_Opcode }, { Bad_Opcode }, { PREFIX_TABLE (PREFIX_0F7C) }, { PREFIX_TABLE (PREFIX_0F7D) }, @@ -2950,7 +3026,7 @@ static const struct dis386 dis386_twobyte[] = { { "xaddB", { Ebh1, Gb }, 0 }, { "xaddS", { Evh1, Gv }, 0 }, { PREFIX_TABLE (PREFIX_0FC2) }, - { PREFIX_TABLE (PREFIX_0FC3) }, + { MOD_TABLE (MOD_0FC3) }, { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE }, { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE }, { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE }, @@ -3324,7 +3400,7 @@ static const struct dis386 reg_table[][8] = { { "xorQ", { Evh1, Iv }, 0 }, { "cmpQ", { Ev, Iv }, 0 }, }, - /* REG_82 */ + /* REG_83 */ { { "addQ", { Evh1, sIb }, 0 }, { "orQ", { Evh1, sIb }, 0 }, @@ -3463,9 +3539,9 @@ static const struct dis386 reg_table[][8] = { { { "incQ", { Evh1 }, 0 }, { "decQ", { Evh1 }, 0 }, - { "call{T|}", { indirEv, BND }, 0 }, + { "call{&|}", { indirEv, BND }, 0 }, { MOD_TABLE (MOD_FF_REG_3) }, - { "jmp{T|}", { indirEv, BND }, 0 }, + { "jmp{&|}", { indirEv, BND }, 0 }, { MOD_TABLE (MOD_FF_REG_5) }, { "pushU", { stackEv }, 0 }, { Bad_Opcode }, @@ -3488,7 +3564,7 @@ static const struct dis386 reg_table[][8] = { { MOD_TABLE (MOD_0F01_REG_2) }, { MOD_TABLE (MOD_0F01_REG_3) }, { "smswD", { Sv }, 0 }, - { Bad_Opcode }, + { MOD_TABLE (MOD_0F01_REG_5) }, { "lmsw", { Ew }, 0 }, { MOD_TABLE (MOD_0F01_REG_7) }, }, @@ -3993,6 +4069,18 @@ static const struct dis386 prefix_table[][4] = { { "wrgsbase", { Ev }, 0 }, }, + /* PREFIX_MOD_0_0FAE_REG_4 */ + { + { "xsave", { FXSAVE }, 0 }, + { "ptwrite%LQ", { Edq }, 0 }, + }, + + /* PREFIX_MOD_3_0FAE_REG_4 */ + { + { Bad_Opcode }, + { "ptwrite%LQ", { Edq }, 0 }, + }, + /* PREFIX_0FAE_REG_6 */ { { "xsaveopt", { FXSAVE }, 0 }, @@ -4007,13 +4095,6 @@ static const struct dis386 prefix_table[][4] = { { "clflushopt", { Mb }, 0 }, }, - /* PREFIX_RM_0_0FAE_REG_7 */ - { - { "sfence", { Skip_MODRM }, 0 }, - { Bad_Opcode }, - { "pcommit", { Skip_MODRM }, 0 }, - }, - /* PREFIX_0FB8 */ { { Bad_Opcode }, @@ -4042,9 +4123,9 @@ static const struct dis386 prefix_table[][4] = { { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE }, }, - /* PREFIX_0FC3 */ + /* PREFIX_MOD_0_0FC3 */ { - { "movntiS", { Ma, Gv }, PREFIX_OPCODE }, + { "movntiS", { Ev, Gv }, PREFIX_OPCODE }, }, /* PREFIX_MOD_0_0FC7_REG_6 */ @@ -4064,7 +4145,7 @@ static const struct dis386 prefix_table[][4] = { /* PREFIX_MOD_3_0FC7_REG_7 */ { { "rdseed", { Ev }, 0 }, - { Bad_Opcode }, + { "rdpid", { Em }, 0 }, { "rdseed", { Ev }, 0 }, }, @@ -6806,6 +6887,12 @@ static const struct dis386 x86_64_table[][2] = { { "outs{G|}", { indirDXr, Xz }, 0 }, }, + /* X86_64_82 */ + { + /* Opcode 0x82 is an alias of of opcode 0x80 in 32-bit mode. */ + { REG_TABLE (REG_80) }, + }, + /* X86_64_9A */ { { "Jcall{T|}", { Ap }, 0 }, @@ -6838,6 +6925,18 @@ static const struct dis386 x86_64_table[][2] = { { "aad", { Ib }, 0 }, }, + /* X86_64_E8 */ + { + { "callP", { Jv, BND }, 0 }, + { "call@", { Jv, BND }, 0 } + }, + + /* X86_64_E9 */ + { + { "jmpP", { Jv, BND }, 0 }, + { "jmp@", { Jv, BND }, 0 } + }, + /* X86_64_EA */ { { "Jjmp{T|}", { Ap }, 0 }, @@ -7452,8 +7551,10 @@ static const struct dis386 three_byte_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, }, +}; - /* THREE_BYTE_0F7A */ +static const struct dis386 xop_table[][256] = { + /* XOP_08 */ { /* 00 */ { Bad_Opcode }, @@ -7492,7 +7593,7 @@ static const struct dis386 three_byte_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* 20 */ - { "ptest", { XX }, PREFIX_OPCODE }, + { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -7529,120 +7630,120 @@ static const struct dis386 three_byte_table[][256] = { { Bad_Opcode }, /* 40 */ { Bad_Opcode }, - { "phaddbw", { XM, EXq }, PREFIX_OPCODE }, - { "phaddbd", { XM, EXq }, PREFIX_OPCODE }, - { "phaddbq", { XM, EXq }, PREFIX_OPCODE }, { Bad_Opcode }, { Bad_Opcode }, - { "phaddwd", { XM, EXq }, PREFIX_OPCODE }, - { "phaddwq", { XM, EXq }, PREFIX_OPCODE }, - /* 48 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "phadddq", { XM, EXq }, PREFIX_OPCODE }, { Bad_Opcode }, { Bad_Opcode }, + /* 48 */ + { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* 50 */ { Bad_Opcode }, - { "phaddubw", { XM, EXq }, PREFIX_OPCODE }, - { "phaddubd", { XM, EXq }, PREFIX_OPCODE }, - { "phaddubq", { XM, EXq }, PREFIX_OPCODE }, { Bad_Opcode }, { Bad_Opcode }, - { "phadduwd", { XM, EXq }, PREFIX_OPCODE }, - { "phadduwq", { XM, EXq }, PREFIX_OPCODE }, - /* 58 */ { Bad_Opcode }, { Bad_Opcode }, + /* 50 */ { Bad_Opcode }, - { "phaddudq", { XM, EXq }, PREFIX_OPCODE }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* 60 */ { Bad_Opcode }, - { "phsubbw", { XM, EXq }, PREFIX_OPCODE }, - { "phsubbd", { XM, EXq }, PREFIX_OPCODE }, - { "phsubbq", { XM, EXq }, PREFIX_OPCODE }, { Bad_Opcode }, { Bad_Opcode }, + /* 58 */ { Bad_Opcode }, { Bad_Opcode }, - /* 68 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* 60 */ { Bad_Opcode }, { Bad_Opcode }, - /* 70 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* 68 */ { Bad_Opcode }, { Bad_Opcode }, - /* 78 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* 70 */ { Bad_Opcode }, { Bad_Opcode }, - /* 80 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* 78 */ { Bad_Opcode }, { Bad_Opcode }, - /* 88 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* 80 */ { Bad_Opcode }, { Bad_Opcode }, - /* 90 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + /* 88 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* 98 */ + { Bad_Opcode }, + { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + /* 90 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + /* 98 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* a0 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + /* a0 */ { Bad_Opcode }, { Bad_Opcode }, + { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, { Bad_Opcode }, { Bad_Opcode }, + { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, { Bad_Opcode }, /* a8 */ { Bad_Opcode }, @@ -7660,7 +7761,7 @@ static const struct dis386 three_byte_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { Bad_Opcode }, + { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, { Bad_Opcode }, /* b8 */ { Bad_Opcode }, @@ -7672,10 +7773,10 @@ static const struct dis386 three_byte_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* c0 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { "vprotb", { XM, Vex_2src_1, Ib }, 0 }, + { "vprotw", { XM, Vex_2src_1, Ib }, 0 }, + { "vprotd", { XM, Vex_2src_1, Ib }, 0 }, + { "vprotq", { XM, Vex_2src_1, Ib }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -7685,10 +7786,10 @@ static const struct dis386 three_byte_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) }, + { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) }, + { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) }, + { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) }, /* d0 */ { Bad_Opcode }, { Bad_Opcode }, @@ -7721,10 +7822,10 @@ static const struct dis386 three_byte_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) }, + { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) }, + { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) }, + { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) }, /* f0 */ { Bad_Opcode }, { Bad_Opcode }, @@ -7744,15 +7845,12 @@ static const struct dis386 three_byte_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, }, -}; - -static const struct dis386 xop_table[][256] = { - /* XOP_08 */ + /* XOP_09 */ { /* 00 */ { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { REG_TABLE (REG_XOP_TBM_01) }, + { REG_TABLE (REG_XOP_TBM_02) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -7770,7 +7868,7 @@ static const struct dis386 xop_table[][256] = { /* 10 */ { Bad_Opcode }, { Bad_Opcode }, - { Bad_Opcode }, + { REG_TABLE (REG_XOP_LWPCB) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -7894,14 +7992,14 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* 80 */ + { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) }, + { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) }, + { "vfrczss", { XM, EXd }, 0 }, + { "vfrczsd", { XM, EXq }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { Bad_Opcode }, - { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, - { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, - { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, /* 88 */ { Bad_Opcode }, { Bad_Opcode }, @@ -7909,34 +8007,34 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, - { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, - /* 90 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, - { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, - { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + /* 90 */ + { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, + { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, + { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, + { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, + { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, + { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, + { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, + { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, /* 98 */ + { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, + { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, + { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, + { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, + { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* a0 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, - { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, - /* a0 */ { Bad_Opcode }, { Bad_Opcode }, - { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, - { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, { Bad_Opcode }, { Bad_Opcode }, - { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, { Bad_Opcode }, /* a8 */ { Bad_Opcode }, @@ -7954,7 +8052,7 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { Bad_Opcode }, { Bad_Opcode }, /* b8 */ { Bad_Opcode }, @@ -7966,59 +8064,59 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* c0 */ - { "vprotb", { XM, Vex_2src_1, Ib }, 0 }, - { "vprotw", { XM, Vex_2src_1, Ib }, 0 }, - { "vprotd", { XM, Vex_2src_1, Ib }, 0 }, - { "vprotq", { XM, Vex_2src_1, Ib }, 0 }, - { Bad_Opcode }, { Bad_Opcode }, + { "vphaddbw", { XM, EXxmm }, 0 }, + { "vphaddbd", { XM, EXxmm }, 0 }, + { "vphaddbq", { XM, EXxmm }, 0 }, { Bad_Opcode }, { Bad_Opcode }, + { "vphaddwd", { XM, EXxmm }, 0 }, + { "vphaddwq", { XM, EXxmm }, 0 }, /* c8 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) }, - { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) }, - { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) }, - { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) }, - /* d0 */ - { Bad_Opcode }, + { "vphadddq", { XM, EXxmm }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* d0 */ { Bad_Opcode }, + { "vphaddubw", { XM, EXxmm }, 0 }, + { "vphaddubd", { XM, EXxmm }, 0 }, + { "vphaddubq", { XM, EXxmm }, 0 }, { Bad_Opcode }, { Bad_Opcode }, + { "vphadduwd", { XM, EXxmm }, 0 }, + { "vphadduwq", { XM, EXxmm }, 0 }, /* d8 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { Bad_Opcode }, + { "vphaddudq", { XM, EXxmm }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, /* e0 */ { Bad_Opcode }, + { "vphsubbw", { XM, EXxmm }, 0 }, + { "vphsubwd", { XM, EXxmm }, 0 }, + { "vphsubdq", { XM, EXxmm }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* e8 */ + { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* e8 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) }, - { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) }, - { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) }, - { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) }, /* f0 */ { Bad_Opcode }, { Bad_Opcode }, @@ -8038,12 +8136,12 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, }, - /* XOP_09 */ + /* XOP_0A */ { /* 00 */ { Bad_Opcode }, - { REG_TABLE (REG_XOP_TBM_01) }, - { REG_TABLE (REG_XOP_TBM_02) }, + { Bad_Opcode }, + { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -8059,9 +8157,9 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* 10 */ + { "bextr", { Gv, Ev, Iq }, 0 }, { Bad_Opcode }, - { Bad_Opcode }, - { REG_TABLE (REG_XOP_LWPCB) }, + { REG_TABLE (REG_XOP_LWP) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -8185,10 +8283,10 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* 80 */ - { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) }, - { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) }, - { "vfrczss", { XM, EXd }, 0 }, - { "vfrczsd", { XM, EXq }, 0 }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -8203,405 +8301,114 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* 90 */ - { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, - { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, - { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, - { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, - { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, - { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, - { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, - { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, - /* 98 */ - { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, - { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, - { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, - { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* a0 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* 98 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* a8 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* a0 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* b0 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* a8 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* b8 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* b0 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* c0 */ { Bad_Opcode }, - { "vphaddbw", { XM, EXxmm }, 0 }, - { "vphaddbd", { XM, EXxmm }, 0 }, - { "vphaddbq", { XM, EXxmm }, 0 }, { Bad_Opcode }, { Bad_Opcode }, - { "vphaddwd", { XM, EXxmm }, 0 }, - { "vphaddwq", { XM, EXxmm }, 0 }, - /* c8 */ { Bad_Opcode }, + /* b8 */ { Bad_Opcode }, { Bad_Opcode }, - { "vphadddq", { XM, EXxmm }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* d0 */ { Bad_Opcode }, - { "vphaddubw", { XM, EXxmm }, 0 }, - { "vphaddubd", { XM, EXxmm }, 0 }, - { "vphaddubq", { XM, EXxmm }, 0 }, { Bad_Opcode }, + /* c0 */ { Bad_Opcode }, - { "vphadduwd", { XM, EXxmm }, 0 }, - { "vphadduwq", { XM, EXxmm }, 0 }, - /* d8 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "vphaddudq", { XM, EXxmm }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* e0 */ + /* c8 */ { Bad_Opcode }, - { "vphsubbw", { XM, EXxmm }, 0 }, - { "vphsubwd", { XM, EXxmm }, 0 }, - { "vphsubdq", { XM, EXxmm }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* e8 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* d0 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* f0 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* d8 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* f8 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* e0 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - }, - /* XOP_0A */ - { - /* 00 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* e8 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* 08 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* 10 */ - { "bextr", { Gv, Ev, Iq }, 0 }, - { Bad_Opcode }, - { REG_TABLE (REG_XOP_LWP) }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* 18 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* 20 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* 28 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* 30 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* 38 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* 40 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* 48 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* 50 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* 58 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* 60 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* 68 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* 70 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* 78 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* 80 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* 88 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* 90 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* 98 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* a0 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* a8 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* b0 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* b8 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* c0 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* c8 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* d0 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* d8 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* e0 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* e8 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* f0 */ + /* f0 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -10427,82 +10234,82 @@ static const struct dis386 vex_w_table[][2] = { }, { /* VEX_W_0F41_P_0_LEN_1 */ - { "kandw", { MaskG, MaskVex, MaskR }, 0 }, - { "kandq", { MaskG, MaskVex, MaskR }, 0 }, + { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) }, + { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) }, }, { /* VEX_W_0F41_P_2_LEN_1 */ - { "kandb", { MaskG, MaskVex, MaskR }, 0 }, - { "kandd", { MaskG, MaskVex, MaskR }, 0 }, + { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) }, + { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) } }, { /* VEX_W_0F42_P_0_LEN_1 */ - { "kandnw", { MaskG, MaskVex, MaskR }, 0 }, - { "kandnq", { MaskG, MaskVex, MaskR }, 0 }, + { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) }, + { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) }, }, { /* VEX_W_0F42_P_2_LEN_1 */ - { "kandnb", { MaskG, MaskVex, MaskR }, 0 }, - { "kandnd", { MaskG, MaskVex, MaskR }, 0 }, + { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) }, + { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) }, }, { /* VEX_W_0F44_P_0_LEN_0 */ - { "knotw", { MaskG, MaskR }, 0 }, - { "knotq", { MaskG, MaskR }, 0 }, + { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) }, + { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) }, }, { /* VEX_W_0F44_P_2_LEN_0 */ - { "knotb", { MaskG, MaskR }, 0 }, - { "knotd", { MaskG, MaskR }, 0 }, + { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) }, + { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) }, }, { /* VEX_W_0F45_P_0_LEN_1 */ - { "korw", { MaskG, MaskVex, MaskR }, 0 }, - { "korq", { MaskG, MaskVex, MaskR }, 0 }, + { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) }, + { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) }, }, { /* VEX_W_0F45_P_2_LEN_1 */ - { "korb", { MaskG, MaskVex, MaskR }, 0 }, - { "kord", { MaskG, MaskVex, MaskR }, 0 }, + { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) }, + { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) }, }, { /* VEX_W_0F46_P_0_LEN_1 */ - { "kxnorw", { MaskG, MaskVex, MaskR }, 0 }, - { "kxnorq", { MaskG, MaskVex, MaskR }, 0 }, + { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) }, + { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) }, }, { /* VEX_W_0F46_P_2_LEN_1 */ - { "kxnorb", { MaskG, MaskVex, MaskR }, 0 }, - { "kxnord", { MaskG, MaskVex, MaskR }, 0 }, + { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) }, + { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) }, }, { /* VEX_W_0F47_P_0_LEN_1 */ - { "kxorw", { MaskG, MaskVex, MaskR }, 0 }, - { "kxorq", { MaskG, MaskVex, MaskR }, 0 }, + { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) }, + { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) }, }, { /* VEX_W_0F47_P_2_LEN_1 */ - { "kxorb", { MaskG, MaskVex, MaskR }, 0 }, - { "kxord", { MaskG, MaskVex, MaskR }, 0 }, + { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) }, + { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) }, }, { /* VEX_W_0F4A_P_0_LEN_1 */ - { "kaddw", { MaskG, MaskVex, MaskR }, 0 }, - { "kaddq", { MaskG, MaskVex, MaskR }, 0 }, + { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) }, + { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) }, }, { /* VEX_W_0F4A_P_2_LEN_1 */ - { "kaddb", { MaskG, MaskVex, MaskR }, 0 }, - { "kaddd", { MaskG, MaskVex, MaskR }, 0 }, + { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) }, + { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) }, }, { /* VEX_W_0F4B_P_0_LEN_1 */ - { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 }, - { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 }, + { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) }, + { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) }, }, { /* VEX_W_0F4B_P_2_LEN_1 */ - { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 }, + { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) }, }, { /* VEX_W_0F50_M_0 */ @@ -10832,59 +10639,59 @@ static const struct dis386 vex_w_table[][2] = { }, { /* VEX_W_0F91_P_0_LEN_0 */ - { "kmovw", { Ew, MaskG }, 0 }, - { "kmovq", { Eq, MaskG }, 0 }, + { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) }, + { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) }, }, { /* VEX_W_0F91_P_2_LEN_0 */ - { "kmovb", { Eb, MaskG }, 0 }, - { "kmovd", { Ed, MaskG }, 0 }, + { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) }, + { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) }, }, { /* VEX_W_0F92_P_0_LEN_0 */ - { "kmovw", { MaskG, Rdq }, 0 }, + { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) }, }, { /* VEX_W_0F92_P_2_LEN_0 */ - { "kmovb", { MaskG, Rdq }, 0 }, + { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) }, }, { /* VEX_W_0F92_P_3_LEN_0 */ - { "kmovd", { MaskG, Rdq }, 0 }, - { "kmovq", { MaskG, Rdq }, 0 }, + { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) }, + { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) }, }, { /* VEX_W_0F93_P_0_LEN_0 */ - { "kmovw", { Gdq, MaskR }, 0 }, + { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) }, }, { /* VEX_W_0F93_P_2_LEN_0 */ - { "kmovb", { Gdq, MaskR }, 0 }, + { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) }, }, { /* VEX_W_0F93_P_3_LEN_0 */ - { "kmovd", { Gdq, MaskR }, 0 }, - { "kmovq", { Gdq, MaskR }, 0 }, + { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) }, + { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) }, }, { /* VEX_W_0F98_P_0_LEN_0 */ - { "kortestw", { MaskG, MaskR }, 0 }, - { "kortestq", { MaskG, MaskR }, 0 }, + { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) }, + { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) }, }, { /* VEX_W_0F98_P_2_LEN_0 */ - { "kortestb", { MaskG, MaskR }, 0 }, - { "kortestd", { MaskG, MaskR }, 0 }, + { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) }, + { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) }, }, { /* VEX_W_0F99_P_0_LEN_0 */ - { "ktestw", { MaskG, MaskR }, 0 }, - { "ktestq", { MaskG, MaskR }, 0 }, + { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) }, + { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) }, }, { /* VEX_W_0F99_P_2_LEN_0 */ - { "ktestb", { MaskG, MaskR }, 0 }, - { "ktestd", { MaskG, MaskR }, 0 }, + { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) }, + { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) }, }, { /* VEX_W_0FAE_R_2_M_0 */ @@ -11470,23 +11277,23 @@ static const struct dis386 vex_w_table[][2] = { }, { /* VEX_W_0F3A30_P_2_LEN_0 */ - { "kshiftrb", { MaskG, MaskR, Ib }, 0 }, - { "kshiftrw", { MaskG, MaskR, Ib }, 0 }, + { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) }, + { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) }, }, { /* VEX_W_0F3A31_P_2_LEN_0 */ - { "kshiftrd", { MaskG, MaskR, Ib }, 0 }, - { "kshiftrq", { MaskG, MaskR, Ib }, 0 }, + { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) }, + { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) }, }, { /* VEX_W_0F3A32_P_2_LEN_0 */ - { "kshiftlb", { MaskG, MaskR, Ib }, 0 }, - { "kshiftlw", { MaskG, MaskR, Ib }, 0 }, + { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) }, + { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) }, }, { /* VEX_W_0F3A33_P_2_LEN_0 */ - { "kshiftld", { MaskG, MaskR, Ib }, 0 }, - { "kshiftlq", { MaskG, MaskR, Ib }, 0 }, + { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) }, + { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) }, }, { /* VEX_W_0F3A38_P_2 */ @@ -11580,11 +11387,11 @@ static const struct dis386 mod_table[][2] = { }, { /* MOD_FF_REG_3 */ - { "Jcall{T|}", { indirEp }, 0 }, + { "Jcall^", { indirEp }, 0 }, }, { /* MOD_FF_REG_5 */ - { "Jjmp{T|}", { indirEp }, 0 }, + { "Jjmp^", { indirEp }, 0 }, }, { /* MOD_0F01_REG_0 */ @@ -11606,6 +11413,11 @@ static const struct dis386 mod_table[][2] = { { X86_64_TABLE (X86_64_0F01_REG_3) }, { RM_TABLE (RM_0F01_REG_3) }, }, + { + /* MOD_0F01_REG_5 */ + { Bad_Opcode }, + { RM_TABLE (RM_0F01_REG_5) }, + }, { /* MOD_0F01_REG_7 */ { "invlpg", { Mb }, 0 }, @@ -11779,7 +11591,8 @@ static const struct dis386 mod_table[][2] = { }, { /* MOD_0FAE_REG_4 */ - { "xsave", { FXSAVE }, 0 }, + { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) }, + { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) }, }, { /* MOD_0FAE_REG_5 */ @@ -11808,9 +11621,13 @@ static const struct dis386 mod_table[][2] = { /* MOD_0FB5 */ { "lgsS", { Gv, Mp }, 0 }, }, + { + /* MOD_0FC3 */ + { PREFIX_TABLE (PREFIX_MOD_0_0FC3) }, + }, { /* MOD_0FC7_REG_3 */ - { "xrstors", { FXSAVE }, 0 }, + { "xrstors", { FXSAVE }, 0 }, }, { /* MOD_0FC7_REG_4 */ @@ -11884,6 +11701,161 @@ static const struct dis386 mod_table[][2] = { /* MOD_VEX_0F2B */ { VEX_W_TABLE (VEX_W_0F2B_M_0) }, }, + { + /* MOD_VEX_W_0_0F41_P_0_LEN_1 */ + { Bad_Opcode }, + { "kandw", { MaskG, MaskVex, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_1_0F41_P_0_LEN_1 */ + { Bad_Opcode }, + { "kandq", { MaskG, MaskVex, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_0_0F41_P_2_LEN_1 */ + { Bad_Opcode }, + { "kandb", { MaskG, MaskVex, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_1_0F41_P_2_LEN_1 */ + { Bad_Opcode }, + { "kandd", { MaskG, MaskVex, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_0_0F42_P_0_LEN_1 */ + { Bad_Opcode }, + { "kandnw", { MaskG, MaskVex, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_1_0F42_P_0_LEN_1 */ + { Bad_Opcode }, + { "kandnq", { MaskG, MaskVex, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_0_0F42_P_2_LEN_1 */ + { Bad_Opcode }, + { "kandnb", { MaskG, MaskVex, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_1_0F42_P_2_LEN_1 */ + { Bad_Opcode }, + { "kandnd", { MaskG, MaskVex, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_0_0F44_P_0_LEN_0 */ + { Bad_Opcode }, + { "knotw", { MaskG, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_1_0F44_P_0_LEN_0 */ + { Bad_Opcode }, + { "knotq", { MaskG, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_0_0F44_P_2_LEN_0 */ + { Bad_Opcode }, + { "knotb", { MaskG, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_1_0F44_P_2_LEN_0 */ + { Bad_Opcode }, + { "knotd", { MaskG, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_0_0F45_P_0_LEN_1 */ + { Bad_Opcode }, + { "korw", { MaskG, MaskVex, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_1_0F45_P_0_LEN_1 */ + { Bad_Opcode }, + { "korq", { MaskG, MaskVex, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_0_0F45_P_2_LEN_1 */ + { Bad_Opcode }, + { "korb", { MaskG, MaskVex, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_1_0F45_P_2_LEN_1 */ + { Bad_Opcode }, + { "kord", { MaskG, MaskVex, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_0_0F46_P_0_LEN_1 */ + { Bad_Opcode }, + { "kxnorw", { MaskG, MaskVex, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_1_0F46_P_0_LEN_1 */ + { Bad_Opcode }, + { "kxnorq", { MaskG, MaskVex, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_0_0F46_P_2_LEN_1 */ + { Bad_Opcode }, + { "kxnorb", { MaskG, MaskVex, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_1_0F46_P_2_LEN_1 */ + { Bad_Opcode }, + { "kxnord", { MaskG, MaskVex, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_0_0F47_P_0_LEN_1 */ + { Bad_Opcode }, + { "kxorw", { MaskG, MaskVex, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_1_0F47_P_0_LEN_1 */ + { Bad_Opcode }, + { "kxorq", { MaskG, MaskVex, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_0_0F47_P_2_LEN_1 */ + { Bad_Opcode }, + { "kxorb", { MaskG, MaskVex, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_1_0F47_P_2_LEN_1 */ + { Bad_Opcode }, + { "kxord", { MaskG, MaskVex, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */ + { Bad_Opcode }, + { "kaddw", { MaskG, MaskVex, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */ + { Bad_Opcode }, + { "kaddq", { MaskG, MaskVex, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */ + { Bad_Opcode }, + { "kaddb", { MaskG, MaskVex, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */ + { Bad_Opcode }, + { "kaddd", { MaskG, MaskVex, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */ + { Bad_Opcode }, + { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */ + { Bad_Opcode }, + { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */ + { Bad_Opcode }, + { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 }, + }, { /* MOD_VEX_0F50 */ { Bad_Opcode }, @@ -11939,6 +11911,106 @@ static const struct dis386 mod_table[][2] = { { Bad_Opcode }, { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) }, }, + { + /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ + { "kmovw", { Ew, MaskG }, 0 }, + { Bad_Opcode }, + }, + { + /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ + { "kmovq", { Eq, MaskG }, 0 }, + { Bad_Opcode }, + }, + { + /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ + { "kmovb", { Eb, MaskG }, 0 }, + { Bad_Opcode }, + }, + { + /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ + { "kmovd", { Ed, MaskG }, 0 }, + { Bad_Opcode }, + }, + { + /* MOD_VEX_W_0_0F92_P_0_LEN_0 */ + { Bad_Opcode }, + { "kmovw", { MaskG, Rdq }, 0 }, + }, + { + /* MOD_VEX_W_0_0F92_P_2_LEN_0 */ + { Bad_Opcode }, + { "kmovb", { MaskG, Rdq }, 0 }, + }, + { + /* MOD_VEX_W_0_0F92_P_3_LEN_0 */ + { Bad_Opcode }, + { "kmovd", { MaskG, Rdq }, 0 }, + }, + { + /* MOD_VEX_W_1_0F92_P_3_LEN_0 */ + { Bad_Opcode }, + { "kmovq", { MaskG, Rdq }, 0 }, + }, + { + /* MOD_VEX_W_0_0F93_P_0_LEN_0 */ + { Bad_Opcode }, + { "kmovw", { Gdq, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_0_0F93_P_2_LEN_0 */ + { Bad_Opcode }, + { "kmovb", { Gdq, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_0_0F93_P_3_LEN_0 */ + { Bad_Opcode }, + { "kmovd", { Gdq, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_1_0F93_P_3_LEN_0 */ + { Bad_Opcode }, + { "kmovq", { Gdq, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_0_0F98_P_0_LEN_0 */ + { Bad_Opcode }, + { "kortestw", { MaskG, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_1_0F98_P_0_LEN_0 */ + { Bad_Opcode }, + { "kortestq", { MaskG, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_0_0F98_P_2_LEN_0 */ + { Bad_Opcode }, + { "kortestb", { MaskG, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_1_0F98_P_2_LEN_0 */ + { Bad_Opcode }, + { "kortestd", { MaskG, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_0_0F99_P_0_LEN_0 */ + { Bad_Opcode }, + { "ktestw", { MaskG, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_1_0F99_P_0_LEN_0 */ + { Bad_Opcode }, + { "ktestq", { MaskG, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_0_0F99_P_2_LEN_0 */ + { Bad_Opcode }, + { "ktestb", { MaskG, MaskR }, 0 }, + }, + { + /* MOD_VEX_W_1_0F99_P_2_LEN_0 */ + { Bad_Opcode }, + { "ktestd", { MaskG, MaskR }, 0 }, + }, { /* MOD_VEX_0FAE_REG_2 */ { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) }, @@ -11996,6 +12068,46 @@ static const struct dis386 mod_table[][2] = { /* MOD_VEX_0F388E_PREFIX_2 */ { "vpmaskmov%LW", { Mx, Vex, XM }, 0 }, }, + { + /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */ + { Bad_Opcode }, + { "kshiftrb", { MaskG, MaskR, Ib }, 0 }, + }, + { + /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */ + { Bad_Opcode }, + { "kshiftrw", { MaskG, MaskR, Ib }, 0 }, + }, + { + /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */ + { Bad_Opcode }, + { "kshiftrd", { MaskG, MaskR, Ib }, 0 }, + }, + { + /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */ + { Bad_Opcode }, + { "kshiftrq", { MaskG, MaskR, Ib }, 0 }, + }, + { + /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */ + { Bad_Opcode }, + { "kshiftlb", { MaskG, MaskR, Ib }, 0 }, + }, + { + /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */ + { Bad_Opcode }, + { "kshiftlw", { MaskG, MaskR, Ib }, 0 }, + }, + { + /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */ + { Bad_Opcode }, + { "kshiftld", { MaskG, MaskR, Ib }, 0 }, + }, + { + /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */ + { Bad_Opcode }, + { "kshiftlq", { MaskG, MaskR, Ib }, 0 }, + }, #define NEED_MOD_TABLE #include "i386-dis-evex.h" #undef NEED_MOD_TABLE @@ -12051,12 +12163,23 @@ static const struct dis386 rm_table[][8] = { { "skinit", { Skip_MODRM }, 0 }, { "invlpga", { Skip_MODRM }, 0 }, }, + { + /* RM_0F01_REG_5 */ + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { "rdpkru", { Skip_MODRM }, 0 }, + { "wrpkru", { Skip_MODRM }, 0 }, + }, { /* RM_0F01_REG_7 */ { "swapgs", { Skip_MODRM }, 0 }, { "rdtscp", { Skip_MODRM }, 0 }, - { Bad_Opcode }, - { Bad_Opcode }, + { "monitorx", { { OP_Monitor, 0 } }, 0 }, + { "mwaitx", { { OP_Mwaitx, 0 } }, 0 }, { "clzero", { Skip_MODRM }, 0 }, }, { @@ -12069,7 +12192,8 @@ static const struct dis386 rm_table[][8] = { }, { /* RM_0FAE_REG_7 */ - { PREFIX_TABLE (PREFIX_RM_0_0FAE_REG_7) }, + { "sfence", { Skip_MODRM }, 0 }, + }, }; @@ -12327,6 +12451,14 @@ static char close_char; static char separator_char; static char scale_char; +enum x86_64_isa +{ + amd64 = 0, + intel64 +}; + +static enum x86_64_isa isa64; + /* Here for backwards compatibility. When gdb stops using print_insn_i386_att and print_insn_i386_intel these functions can disappear, and print_insn_i386 be merged into print_insn. */ @@ -12376,6 +12508,8 @@ with the -M switch (multiple options should be separated by commas):\n")); fprintf (stream, _(" data32 Assume 32bit data size\n")); fprintf (stream, _(" data16 Assume 16bit data size\n")); fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); + fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n")); + fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n")); } /* Bad opcode. */ @@ -12538,11 +12672,15 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) rex |= REX_W; vex.register_specifier = (~(*codep >> 3)) & 0xf; - if (address_mode != mode_64bit - && vex.register_specifier > 0x7) + if (address_mode != mode_64bit) { - dp = &bad_opcode; - return dp; + /* In 16/32-bit mode REX_B is silently ignored. */ + rex &= ~REX_B; + if (vex.register_specifier > 0x7) + { + dp = &bad_opcode; + return dp; + } } vex.length = (*codep & 0x4) ? 256 : 128; @@ -12597,17 +12735,20 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) } codep++; vex.w = *codep & 0x80; - if (vex.w && address_mode == mode_64bit) - rex |= REX_W; - - vex.register_specifier = (~(*codep >> 3)) & 0xf; - if (address_mode != mode_64bit - && vex.register_specifier > 0x7) + if (address_mode == mode_64bit) { - dp = &bad_opcode; - return dp; + if (vex.w) + rex |= REX_W; + vex.register_specifier = (~(*codep >> 3)) & 0xf; + } + else + { + /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit + is ignored, other REX bits are 0 and the highest bit in + VEX.vvvv is also ignored. */ + rex = 0; + vex.register_specifier = (~(*codep >> 3)) & 0x7; } - vex.length = (*codep & 0x4) ? 256 : 128; switch ((*codep & 0x3)) { @@ -12630,8 +12771,8 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) vindex = *codep++; dp = &vex_table[vex_table_index][vindex]; end_codep = codep; - /* There is no MODRM byte for VEX [82|77]. */ - if (vindex != 0x77 && vindex != 0x82) + /* There is no MODRM byte for VEX0F 77. */ + if (vex_table_index != VEX_0F || vindex != 0x77) { FETCH_DATA (info, codep + 1); modrm.mod = (*codep >> 6) & 3; @@ -12647,16 +12788,10 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) rex_ignored = rex; rex = (*codep & 0x80) ? 0 : REX_R; + /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in + VEX.vvvv is 1. */ vex.register_specifier = (~(*codep >> 3)) & 0xf; - if (address_mode != mode_64bit - && vex.register_specifier > 0x7) - { - dp = &bad_opcode; - return dp; - } - vex.w = 0; - vex.length = (*codep & 0x4) ? 256 : 128; switch ((*codep & 0x3)) { @@ -12679,8 +12814,8 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) vindex = *codep++; dp = &vex_table[dp->op[1].bytemode][vindex]; end_codep = codep; - /* There is no MODRM byte for VEX [82|77]. */ - if (vindex != 0x77 && vindex != 0x82) + /* There is no MODRM byte for VEX 77. */ + if (vindex != 0x77) { FETCH_DATA (info, codep + 1); modrm.mod = (*codep >> 6) & 3; @@ -12859,7 +12994,11 @@ print_insn (bfd_vma pc, disassemble_info *info) for (p = info->disassembler_options; p != NULL; ) { - if (CONST_STRNEQ (p, "x86-64")) + if (CONST_STRNEQ (p, "amd64")) + isa64 = amd64; + else if (CONST_STRNEQ (p, "intel64")) + isa64 = intel64; + else if (CONST_STRNEQ (p, "x86-64")) { address_mode = mode_64bit; priv.orig_sizeflag = AFLAG | DFLAG; @@ -12918,6 +13057,13 @@ print_insn (bfd_vma pc, disassemble_info *info) p++; } + if (address_mode == mode_64bit && sizeof (bfd_vma) < 8) + { + (*info->fprintf_func) (info->stream, + _("64-bit address is disabled")); + return -1; + } + if (intel_syntax) { names64 = intel_names64; @@ -13047,8 +13193,10 @@ print_insn (bfd_vma pc, disassemble_info *info) if (*codep == 0x0f) { unsigned char threebyte; - FETCH_DATA (info, codep + 2); - threebyte = *++codep; + + codep++; + FETCH_DATA (info, codep + 1); + threebyte = *codep; dp = &dis386_twobyte[threebyte]; need_modrm = twobyte_has_modrm[*codep]; codep++; @@ -13193,6 +13341,13 @@ print_insn (bfd_vma pc, disassemble_info *info) for (i = 0; i < MAX_OPERANDS; ++i) op_txt[i] = op_out[i]; + if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding + && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL) + { + op_txt[2] = op_out[3]; + op_txt[3] = op_out[2]; + } + for (i = 0; i < (MAX_OPERANDS >> 1); ++i) { op_ad = op_index[i]; @@ -13226,7 +13381,7 @@ print_insn (bfd_vma pc, disassemble_info *info) if (op_index[i] != -1 && op_riprel[i]) { (*info->fprintf_func) (info->stream, " # "); - (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep + (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep) + op_address[op_index[i]]), info); break; } @@ -13386,15 +13541,15 @@ static const unsigned char float_mem_mode[] = { #define ST { OP_ST, 0 } #define STi { OP_STi, 0 } -#define FGRPd9_2 NULL, { { NULL, 0 } }, 0 -#define FGRPd9_4 NULL, { { NULL, 1 } }, 0 -#define FGRPd9_5 NULL, { { NULL, 2 } }, 0 -#define FGRPd9_6 NULL, { { NULL, 3 } }, 0 -#define FGRPd9_7 NULL, { { NULL, 4 } }, 0 -#define FGRPda_5 NULL, { { NULL, 5 } }, 0 -#define FGRPdb_4 NULL, { { NULL, 6 } }, 0 -#define FGRPde_3 NULL, { { NULL, 7 } }, 0 -#define FGRPdf_4 NULL, { { NULL, 8 } }, 0 +#define FGRPd9_2 NULL, { { NULL, 1 } }, 0 +#define FGRPd9_4 NULL, { { NULL, 2 } }, 0 +#define FGRPd9_5 NULL, { { NULL, 3 } }, 0 +#define FGRPd9_6 NULL, { { NULL, 4 } }, 0 +#define FGRPd9_7 NULL, { { NULL, 5 } }, 0 +#define FGRPda_5 NULL, { { NULL, 6 } }, 0 +#define FGRPdb_4 NULL, { { NULL, 7 } }, 0 +#define FGRPde_3 NULL, { { NULL, 8 } }, 0 +#define FGRPdf_4 NULL, { { NULL, 9 } }, 0 static const struct dis386 float_reg[][8] = { /* d8 */ @@ -13488,48 +13643,53 @@ static const struct dis386 float_reg[][8] = { }; static char *fgrps[][8] = { - /* d9_2 0 */ + /* Bad opcode 0 */ + { + "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", + }, + + /* d9_2 1 */ { "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", }, - /* d9_4 1 */ + /* d9_4 2 */ { "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", }, - /* d9_5 2 */ + /* d9_5 3 */ { "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", }, - /* d9_6 3 */ + /* d9_6 4 */ { "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", }, - /* d9_7 4 */ + /* d9_7 5 */ { "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", }, - /* da_5 5 */ + /* da_5 6 */ { "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", }, - /* db_4 6 */ + /* db_4 7 */ { "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", }, - /* de_3 7 */ + /* de_3 8 */ { "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", }, - /* df_4 8 */ + /* df_4 9 */ { "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", }, @@ -13650,7 +13810,6 @@ putop (const char *in_template, int sizeflag) cond = 0; break; case '{': - alt = 0; if (intel_syntax) { while (*++p != '|') @@ -13801,6 +13960,34 @@ case_B: *obufp++ = 'd'; break; case 'Z': + if (l != 0 || len != 1) + { + if (l != 1 || len != 2 || last[0] != 'X') + { + SAVE_LAST (*p); + break; + } + if (!need_vex || !vex.evex) + abort (); + if (intel_syntax + || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) + break; + switch (vex.length) + { + case 128: + *obufp++ = 'x'; + break; + case 256: + *obufp++ = 'y'; + break; + case 512: + *obufp++ = 'z'; + break; + default: + abort (); + } + break; + } if (intel_syntax) break; if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS)) @@ -13843,6 +14030,15 @@ case_L: if (!(rex & REX_W)) used_prefixes |= (prefixes & PREFIX_DATA); break; + case '&': + if (!intel_syntax + && address_mode == mode_64bit + && isa64 == intel64) + { + *obufp++ = 'q'; + break; + } + /* Fall through. */ case 'T': if (!intel_syntax && address_mode == mode_64bit @@ -14099,7 +14295,7 @@ case_S: if (!need_vex) abort (); if (intel_syntax - || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) + || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) break; switch (vex.length) { @@ -14109,8 +14305,10 @@ case_S: case 256: *obufp++ = 'y'; break; + case 512: + if (!vex.evex) default: - abort (); + abort (); } } break; @@ -14151,6 +14349,32 @@ case_S: *obufp++ = vex.w ? 'q': 'd'; } break; + case '^': + if (intel_syntax) + break; + if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) + { + if (sizeflag & DFLAG) + *obufp++ = 'l'; + else + *obufp++ = 'w'; + used_prefixes |= (prefixes & PREFIX_DATA); + } + break; + case '@': + if (intel_syntax) + break; + if (address_mode == mode_64bit + && (isa64 == intel64 + || ((sizeflag & DFLAG) || (rex & REX_W)))) + *obufp++ = 'q'; + else if ((prefixes & PREFIX_DATA)) + { + if (!(sizeflag & DFLAG)) + *obufp++ = 'w'; + used_prefixes |= (prefixes & PREFIX_DATA); + } + break; } alt = 0; } @@ -14332,16 +14556,22 @@ intel_operand_size (int bytemode, int sizeflag) case w_mode: case dw_mode: case dqw_mode: - case dqw_swap_mode: oappend ("WORD PTR "); break; + case indir_v_mode: + if (address_mode == mode_64bit && isa64 == intel64) + { + oappend ("QWORD PTR "); + break; + } + /* Fall through. */ case stack_v_mode: if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) { oappend ("QWORD PTR "); break; } - /* FALLTHRU */ + /* Fall through. */ case v_mode: case v_swap_mode: case dq_mode: @@ -14680,8 +14910,7 @@ OP_E_register (int bytemode, int sizeflag) if ((sizeflag & SUFFIX_ALWAYS) && (bytemode == b_swap_mode - || bytemode == v_swap_mode - || bytemode == dqw_swap_mode)) + || bytemode == v_swap_mode)) swap_operand (); switch (bytemode) @@ -14712,6 +14941,13 @@ OP_E_register (int bytemode, int sizeflag) case bnd_mode: names = names_bnd; break; + case indir_v_mode: + if (address_mode == mode_64bit && isa64 == intel64) + { + names = names64; + break; + } + /* Fall through. */ case stack_v_mode: if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) { @@ -14719,14 +14955,13 @@ OP_E_register (int bytemode, int sizeflag) break; } bytemode = v_mode; - /* FALLTHRU */ + /* Fall through. */ case v_mode: case v_swap_mode: case dq_mode: case dqb_mode: case dqd_mode: case dqw_mode: - case dqw_swap_mode: USED_REX (REX_W); if (rex & REX_W) names = names64; @@ -14743,6 +14978,11 @@ OP_E_register (int bytemode, int sizeflag) break; case mask_bd_mode: case mask_mode: + if (reg > 0x7) + { + oappend ("(bad)"); + return; + } names = names_mask; break; case 0: @@ -14777,7 +15017,6 @@ OP_E_memory (int bytemode, int sizeflag) { case dqw_mode: case dw_mode: - case dqw_swap_mode: shift = 1; break; case dqb_mode: @@ -14800,7 +15039,7 @@ OP_E_memory (int bytemode, int sizeflag) shift = vex.w ? 3 : 2; break; } - /* Fall through if vex.b == 0. */ + /* Fall through. */ case xmmqd_mode: case xmmdw_mode: case ymmq_mode: @@ -15000,7 +15239,7 @@ OP_E_memory (int bytemode, int sizeflag) if (riprel) { set_op (disp, 1); - oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)"); + oappend (!addr32flag ? "(%rip)" : "(%eip)"); } } @@ -15015,7 +15254,7 @@ OP_E_memory (int bytemode, int sizeflag) if (intel_syntax && riprel) { set_op (disp, 1); - oappend (sizeflag & AFLAG ? "rip" : "eip"); + oappend (!addr32flag ? "rip" : "eip"); } *obufp = '\0'; if (havebase) @@ -15251,7 +15490,6 @@ OP_G (int bytemode, int sizeflag) case dqb_mode: case dqd_mode: case dqw_mode: - case dqw_swap_mode: USED_REX (REX_W); if (rex & REX_W) oappend (names64[modrm.reg + add]); @@ -15272,6 +15510,11 @@ OP_G (int bytemode, int sizeflag) break; case mask_bd_mode: case mask_mode: + if ((modrm.reg + add) > 0x7) + { + oappend ("(bad)"); + return; + } oappend (names_mask[modrm.reg + add]); break; default: @@ -15292,11 +15535,11 @@ get64 (void) a = *codep++ & 0xff; a |= (*codep++ & 0xff) << 8; a |= (*codep++ & 0xff) << 16; - a |= (*codep++ & 0xff) << 24; + a |= (*codep++ & 0xffu) << 24; b = *codep++ & 0xff; b |= (*codep++ & 0xff) << 8; b |= (*codep++ & 0xff) << 16; - b |= (*codep++ & 0xff) << 24; + b |= (*codep++ & 0xffu) << 24; x = a + ((bfd_vma) b << 32); #else abort (); @@ -15667,8 +15910,11 @@ OP_J (int bytemode, int sizeflag) disp -= 0x100; break; case v_mode: - USED_REX (REX_W); - if ((sizeflag & DFLAG) || (rex & REX_W)) + if (isa64 == amd64) + USED_REX (REX_W); + if ((sizeflag & DFLAG) + || (address_mode == mode_64bit + && (isa64 != amd64 || (rex & REX_W)))) disp = get32s (); else { @@ -15681,10 +15927,11 @@ OP_J (int bytemode, int sizeflag) the displacement is added! */ mask = 0xffff; if ((prefixes & PREFIX_DATA) == 0) - segment = ((start_pc + codep - start_codep) + segment = ((start_pc + (codep - start_codep)) & ~((bfd_vma) 0xffff)); } - if (!(rex & REX_W)) + if (address_mode != mode_64bit + || (isa64 == amd64 && !(rex & REX_W))) used_prefixes |= (prefixes & PREFIX_DATA); break; default: @@ -16097,7 +16344,6 @@ OP_EX (int bytemode, int sizeflag) if ((sizeflag & SUFFIX_ALWAYS) && (bytemode == x_swap_mode || bytemode == d_swap_mode - || bytemode == dqw_swap_mode || bytemode == d_scalar_swap_mode || bytemode == q_swap_mode || bytemode == q_scalar_swap_mode)) @@ -16353,6 +16599,25 @@ CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) } } +static void +OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED, + int sizeflag ATTRIBUTE_UNUSED) +{ + /* mwaitx %eax,%ecx,%ebx */ + if (!intel_syntax) + { + const char **names = (address_mode == mode_64bit + ? names64 : names32); + strcpy (op_out[0], names[0]); + strcpy (op_out[1], names[1]); + strcpy (op_out[2], names[3]); + two_source_ops = 1; + } + /* Skip mod/rm byte. */ + MODRM_CHECK; + codep++; +} + static void OP_Mwait (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) @@ -16679,6 +16944,11 @@ OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) break; case mask_bd_mode: case mask_mode: + if (reg > 0x7) + { + oappend ("(bad)"); + return; + } names = names_mask; break; default: @@ -16699,10 +16969,16 @@ OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) break; case mask_bd_mode: case mask_mode: + if (reg > 0x7) + { + oappend ("(bad)"); + return; + } names = names_mask; break; default: - abort (); + /* See PR binutils/20893 for a reproducer. */ + oappend ("(bad)"); return; } break; @@ -16757,6 +17033,7 @@ get_vex_imm8 (int sizeflag, int opnum) if (base != 5) /* No displacement. */ break; + /* Fall through. */ case 2: /* 4 byte displacement. */ bytes_before_imm += 4; @@ -16783,6 +17060,7 @@ get_vex_imm8 (int sizeflag, int opnum) if (modrm.rm != 6) /* No displacement. */ break; + /* Fall through. */ case 2: /* 2 byte displacement. */ bytes_before_imm += 2;