X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Fi386-dis.c;h=21d9d3a61a63edabc57ac6feb00f4b50cbadbde6;hb=4e86f6e7478e40a288ec6567fa7f3b4ef0f8d516;hp=b0bb5e8cab26d625a0449ada317e02f768a4de58;hpb=8b89fe14b522cd6e5d160ff17defa8ecec243b11;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index b0bb5e8cab..21d9d3a61a 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -1,5 +1,5 @@ /* Print i386 instructions for GDB, the GNU debugger. - Copyright (C) 1988-2016 Free Software Foundation, Inc. + Copyright (C) 1988-2020 Free Software Foundation, Inc. This file is part of the GNU opcodes library. @@ -33,7 +33,7 @@ the Intel manual for details. */ #include "sysdep.h" -#include "dis-asm.h" +#include "disassemble.h" #include "opintl.h" #include "opcode/i386.h" #include "libiberty.h" @@ -95,21 +95,21 @@ static void OP_XMM_VexW (int, int); static void OP_Rounding (int, int); static void OP_REG_VexI4 (int, int); static void PCLMUL_Fixup (int, int); -static void VEXI4_Fixup (int, int); -static void VZERO_Fixup (int, int); static void VCMP_Fixup (int, int); static void VPCMP_Fixup (int, int); +static void VPCOM_Fixup (int, int); static void OP_0f07 (int, int); static void OP_Monitor (int, int); static void OP_Mwait (int, int); -static void OP_Mwaitx (int, int); static void NOP_Fixup1 (int, int); static void NOP_Fixup2 (int, int); static void OP_3DNowSuffix (int, int); static void CMP_Fixup (int, int); static void BadOp (void); static void REP_Fixup (int, int); +static void SEP_Fixup (int, int); static void BND_Fixup (int, int); +static void NOTRACK_Fixup (int, int); static void HLE_Fixup1 (int, int); static void HLE_Fixup2 (int, int); static void HLE_Fixup3 (int, int); @@ -117,12 +117,14 @@ static void CMPXCHG8B_Fixup (int, int); static void XMM_Fixup (int, int); static void CRC32_Fixup (int, int); static void FXSAVE_Fixup (int, int); +static void PCMPESTR_Fixup (int, int); static void OP_LWPCB_E (int, int); static void OP_LWP_E (int, int); static void OP_Vex_2src_1 (int, int); static void OP_Vex_2src_2 (int, int); static void MOVBE_Fixup (int, int); +static void MOVSXD_Fixup (int, int); static void OP_Mask (int, int); @@ -246,13 +248,14 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define Eb { OP_E, b_mode } #define Ebnd { OP_E, bnd_mode } #define EbS { OP_E, b_swap_mode } +#define EbndS { OP_E, bnd_swap_mode } #define Ev { OP_E, v_mode } +#define Eva { OP_E, va_mode } #define Ev_bnd { OP_E, v_bnd_mode } #define EvS { OP_E, v_swap_mode } #define Ed { OP_E, d_mode } #define Edq { OP_E, dq_mode } #define Edqw { OP_E, dqw_mode } -#define EdqwS { OP_E, dqw_swap_mode } #define Edqb { OP_E, dqb_mode } #define Edb { OP_E, db_mode } #define Edw { OP_E, dw_mode } @@ -270,6 +273,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define Mo { OP_M, o_mode } #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ #define Mq { OP_M, q_mode } +#define Mv_bnd { OP_M, v_bndmk_mode } #define Mx { OP_M, x_mode } #define Mxmm { OP_M, xmm_mode } #define Gb { OP_G, b_mode } @@ -278,6 +282,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define Gd { OP_G, d_mode } #define Gdq { OP_G, dq_mode } #define Gm { OP_G, m_mode } +#define Gva { OP_G, va_mode } #define Gw { OP_G, w_mode } #define Rd { OP_R, d_mode } #define Rdq { OP_R, dq_mode } @@ -287,12 +292,13 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ #define Iv { OP_I, v_mode } #define sIv { OP_sI, v_mode } -#define Iq { OP_I, q_mode } #define Iv64 { OP_I64, v_mode } +#define Id { OP_I, d_mode } #define Iw { OP_I, w_mode } #define I1 { OP_I, const_1_mode } #define Jb { OP_J, b_mode } #define Jv { OP_J, v_mode } +#define Jdqw { OP_J, dqw_mode } #define Cm { OP_C, m_mode } #define Dm { OP_D, m_mode } #define Td { OP_T, d_mode } @@ -375,11 +381,12 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define EMS { OP_EM, v_swap_mode } #define EMd { OP_EM, d_mode } #define EMx { OP_EM, x_mode } +#define EXbScalar { OP_EX, b_scalar_mode } #define EXw { OP_EX, w_mode } +#define EXwScalar { OP_EX, w_scalar_mode } #define EXd { OP_EX, d_mode } #define EXdScalar { OP_EX, d_scalar_mode } #define EXdS { OP_EX, d_swap_mode } -#define EXdScalarS { OP_EX, d_scalar_swap_mode } #define EXq { OP_EX, q_mode } #define EXqScalar { OP_EX, q_scalar_mode } #define EXqScalarS { OP_EX, q_scalar_swap_mode } @@ -394,11 +401,9 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define EXxmm_mw { OP_EX, xmm_mw_mode } #define EXxmm_md { OP_EX, xmm_md_mode } #define EXxmm_mq { OP_EX, xmm_mq_mode } -#define EXxmm_mdq { OP_EX, xmm_mdq_mode } #define EXxmmdw { OP_EX, xmmdw_mode } #define EXxmmqd { OP_EX, xmmqd_mode } #define EXymmq { OP_EX, ymmq_mode } -#define EXVexWdq { OP_EX, vex_w_dq_mode } #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode } #define EXEvexXGscat { OP_EX, evex_x_gscat_mode } #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode } @@ -407,6 +412,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define EMCq { OP_EMC, q_mode } #define MXC { OP_MXC, 0 } #define OPSUF { OP_3DNowSuffix, 0 } +#define SEP { SEP_Fixup, 0 } #define CMP { CMP_Fixup, 0 } #define XMM0 { XMM_Fixup, 0 } #define FXSAVE { FXSAVE_Fixup, 0 } @@ -419,27 +425,22 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define Vex128 { OP_VEX, vex128_mode } #define Vex256 { OP_VEX, vex256_mode } #define VexGdq { OP_VEX, dq_mode } -#define VexI4 { VEXI4_Fixup, 0} -#define EXdVex { OP_EX_Vex, d_mode } -#define EXdVexS { OP_EX_Vex, d_swap_mode } #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode } -#define EXqVex { OP_EX_Vex, q_mode } -#define EXqVexS { OP_EX_Vex, q_swap_mode } #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode } #define EXVexW { OP_EX_VexW, x_mode } #define EXdVexW { OP_EX_VexW, d_mode } #define EXqVexW { OP_EX_VexW, q_mode } #define EXVexImmW { OP_EX_VexImmW, x_mode } -#define XMVex { OP_XMM_Vex, 0 } #define XMVexScalar { OP_XMM_Vex, scalar_mode } #define XMVexW { OP_XMM_VexW, 0 } #define XMVexI4 { OP_REG_VexI4, x_mode } #define PCLMUL { PCLMUL_Fixup, 0 } -#define VZERO { VZERO_Fixup, 0 } #define VCMP { VCMP_Fixup, 0 } #define VPCMP { VPCMP_Fixup, 0 } +#define VPCOM { VPCOM_Fixup, 0 } #define EXxEVexR { OP_Rounding, evex_rounding_mode } +#define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode } #define EXxEVexS { OP_Rounding, evex_sae_mode } #define XMask { OP_Mask, mask_mode } @@ -473,6 +474,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define Evh3 { HLE_Fixup3, v_mode } #define BND { BND_Fixup, 0 } +#define NOTRACK { NOTRACK_Fixup, 0 } #define cond_jump_flag { NULL, cond_jump_mode } #define loop_jcxz_flag { NULL, loop_jcxz_mode } @@ -494,6 +496,8 @@ enum v_mode, /* operand size depends on prefixes with operand swapped */ v_swap_mode, + /* operand size depends on address prefix */ + va_mode, /* word operand */ w_mode, /* double word operand */ @@ -532,9 +536,6 @@ enum xmm_md_mode, /* XMM register or quad word memory operand */ xmm_mq_mode, - /* XMM register or double/quad word memory operand, depending on - VEX.W. */ - xmm_mdq_mode, /* 16-byte XMM, word, double word or quad word operand. */ xmmdw_mode, /* 16-byte XMM, double word, quad word operand or xmm word operand. */ @@ -551,13 +552,19 @@ enum a_mode, cond_jump_mode, loop_jcxz_mode, + movsxd_mode, v_bnd_mode, + /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */ + v_bndmk_mode, /* operand size depends on REX prefixes. */ dq_mode, - /* registers like dq_mode, memory like w_mode. */ + /* registers like dq_mode, memory like w_mode, displacements like + v_mode without considering Intel64 ISA. */ dqw_mode, - dqw_swap_mode, + /* bounds operand */ bnd_mode, + /* bounds operand with operand swapped */ + bnd_swap_mode, /* 4- or 6-byte pointer operand */ f_mode, const_1_mode, @@ -583,20 +590,22 @@ enum vex128_mode, /* 256bit vex mode */ vex256_mode, - /* operand size depends on the VEX.W bit. */ - vex_w_dq_mode, - /* Similar to vex_w_dq_mode, with VSIB dword indices. */ + /* Operand size depends on the VEX.W bit, with VSIB dword indices. */ vex_vsib_d_w_dq_mode, /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */ vex_vsib_d_w_d_mode, - /* Similar to vex_w_dq_mode, with VSIB qword indices. */ + /* Operand size depends on the VEX.W bit, with VSIB qword indices. */ vex_vsib_q_w_dq_mode, /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */ vex_vsib_q_w_d_mode, /* scalar, ignore vector length. */ scalar_mode, + /* like b_mode, ignore vector length. */ + b_scalar_mode, + /* like w_mode, ignore vector length. */ + w_scalar_mode, /* like d_mode, ignore vector length. */ d_scalar_mode, /* like d_swap_mode, ignore vector length. */ @@ -607,11 +616,13 @@ enum q_scalar_swap_mode, /* like vex_mode, ignore vector length. */ vex_scalar_mode, - /* like vex_w_dq_mode, ignore vector length. */ + /* Operand size depends on the VEX.W bit, ignore vector length. */ vex_scalar_w_dq_mode, /* Static rounding. */ evex_rounding_mode, + /* Static rounding, 64-bit mode only. */ + evex_rounding_64_mode, /* Supress all exceptions. */ evex_sae_mode, @@ -681,7 +692,8 @@ enum USE_VEX_C5_TABLE, USE_VEX_LEN_TABLE, USE_VEX_W_TABLE, - USE_EVEX_TABLE + USE_EVEX_TABLE, + USE_EVEX_LEN_TABLE }; #define FLOAT NULL, { { NULL, FLOATCODE } }, 0 @@ -701,12 +713,12 @@ enum #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I)) +#define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I)) enum { REG_80 = 0, REG_81, - REG_82, REG_83, REG_8F, REG_C0, @@ -725,6 +737,8 @@ enum REG_0F01, REG_0F0D, REG_0F18, + REG_0F1C_P_0_MOD_0, + REG_0F1E_P_1_MOD_3, REG_0F71, REG_0F72, REG_0F73, @@ -778,6 +792,8 @@ enum MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0, MOD_0F1B_PREFIX_1, + MOD_0F1C_PREFIX_0, + MOD_0F1E_PREFIX_1, MOD_0F24, MOD_0F26, MOD_0F2B_PREFIX_0, @@ -816,6 +832,12 @@ enum MOD_0FE7_PREFIX_2, MOD_0FF0_PREFIX_3, MOD_0F382A_PREFIX_2, + MOD_0F38F5_PREFIX_2, + MOD_0F38F6_PREFIX_0, + MOD_0F38F8_PREFIX_1, + MOD_0F38F8_PREFIX_2, + MOD_0F38F8_PREFIX_3, + MOD_0F38F9_PREFIX_0, MOD_62_32BIT, MOD_C4_32BIT, MOD_C5_32BIT, @@ -872,12 +894,10 @@ enum MOD_VEX_W_1_0F91_P_2_LEN_0, MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0, - MOD_VEX_W_0_0F92_P_3_LEN_0, - MOD_VEX_W_1_0F92_P_3_LEN_0, + MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0, - MOD_VEX_W_0_0F93_P_3_LEN_0, - MOD_VEX_W_1_0F93_P_3_LEN_0, + MOD_VEX_0F93_P_3_LEN_0, MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0, MOD_VEX_W_0_0F98_P_2_LEN_0, @@ -909,10 +929,6 @@ enum MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0, - MOD_EVEX_0F10_PREFIX_1, - MOD_EVEX_0F10_PREFIX_3, - MOD_EVEX_0F11_PREFIX_1, - MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, @@ -933,22 +949,32 @@ enum RM_0F01_REG_1, RM_0F01_REG_2, RM_0F01_REG_3, - RM_0F01_REG_5, - RM_0F01_REG_7, - RM_0FAE_REG_5, - RM_0FAE_REG_6, - RM_0FAE_REG_7 + RM_0F01_REG_5_MOD_3, + RM_0F01_REG_7_MOD_3, + RM_0F1E_P_1_MOD_3_REG_7, + RM_0FAE_REG_6_MOD_3_P_0, + RM_0FAE_REG_7_MOD_3, }; enum { PREFIX_90 = 0, + PREFIX_0F01_REG_3_RM_1, + PREFIX_0F01_REG_5_MOD_0, + PREFIX_0F01_REG_5_MOD_3_RM_0, + PREFIX_0F01_REG_5_MOD_3_RM_1, + PREFIX_0F01_REG_5_MOD_3_RM_2, + PREFIX_0F01_REG_7_MOD_3_RM_2, + PREFIX_0F01_REG_7_MOD_3_RM_3, + PREFIX_0F09, PREFIX_0F10, PREFIX_0F11, PREFIX_0F12, PREFIX_0F16, PREFIX_0F1A, PREFIX_0F1B, + PREFIX_0F1C, + PREFIX_0F1E, PREFIX_0F2A, PREFIX_0F2B, PREFIX_0F2C, @@ -981,22 +1007,25 @@ enum PREFIX_0F7D, PREFIX_0F7E, PREFIX_0F7F, - PREFIX_0FAE_REG_0, - PREFIX_0FAE_REG_1, - PREFIX_0FAE_REG_2, - PREFIX_0FAE_REG_3, - PREFIX_MOD_0_0FAE_REG_4, - PREFIX_MOD_3_0FAE_REG_4, - PREFIX_0FAE_REG_6, - PREFIX_0FAE_REG_7, + PREFIX_0FAE_REG_0_MOD_3, + PREFIX_0FAE_REG_1_MOD_3, + PREFIX_0FAE_REG_2_MOD_3, + PREFIX_0FAE_REG_3_MOD_3, + PREFIX_0FAE_REG_4_MOD_0, + PREFIX_0FAE_REG_4_MOD_3, + PREFIX_0FAE_REG_5_MOD_0, + PREFIX_0FAE_REG_5_MOD_3, + PREFIX_0FAE_REG_6_MOD_0, + PREFIX_0FAE_REG_6_MOD_3, + PREFIX_0FAE_REG_7_MOD_0, PREFIX_0FB8, PREFIX_0FBC, PREFIX_0FBD, PREFIX_0FC2, - PREFIX_MOD_0_0FC3, - PREFIX_MOD_0_0FC7_REG_6, - PREFIX_MOD_3_0FC7_REG_6, - PREFIX_MOD_3_0FC7_REG_7, + PREFIX_0FC3_MOD_0, + PREFIX_0FC7_REG_6_MOD_0, + PREFIX_0FC7_REG_6_MOD_3, + PREFIX_0FC7_REG_7_MOD_3, PREFIX_0FD0, PREFIX_0FD6, PREFIX_0FE6, @@ -1043,6 +1072,7 @@ enum PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD, + PREFIX_0F38CF, PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, @@ -1050,7 +1080,10 @@ enum PREFIX_0F38DF, PREFIX_0F38F0, PREFIX_0F38F1, + PREFIX_0F38F5, PREFIX_0F38F6, + PREFIX_0F38F8, + PREFIX_0F38F9, PREFIX_0F3A08, PREFIX_0F3A09, PREFIX_0F3A0A, @@ -1074,6 +1107,8 @@ enum PREFIX_0F3A62, PREFIX_0F3A63, PREFIX_0F3ACC, + PREFIX_0F3ACE, + PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F10, PREFIX_VEX_0F11, @@ -1295,6 +1330,7 @@ enum PREFIX_VEX_0F38BD, PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, + PREFIX_VEX_0F38CF, PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD, @@ -1371,6 +1407,8 @@ enum PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F, + PREFIX_VEX_0F3ACE, + PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF, PREFIX_VEX_0F3AF0, @@ -1549,15 +1587,26 @@ enum PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, + PREFIX_EVEX_0F3850, + PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853, + PREFIX_EVEX_0F3854, + PREFIX_EVEX_0F3855, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, + PREFIX_EVEX_0F3862, + PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, + PREFIX_EVEX_0F3868, + PREFIX_EVEX_0F3870, + PREFIX_EVEX_0F3871, + PREFIX_EVEX_0F3872, + PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, @@ -1575,6 +1624,7 @@ enum PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, + PREFIX_EVEX_0F388F, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, @@ -1629,6 +1679,11 @@ enum PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, + PREFIX_EVEX_0F38CF, + PREFIX_EVEX_0F38DC, + PREFIX_EVEX_0F38DD, + PREFIX_EVEX_0F38DE, + PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, @@ -1666,6 +1721,7 @@ enum PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, + PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3A50, PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, @@ -1673,14 +1729,20 @@ enum PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66, - PREFIX_EVEX_0F3A67 + PREFIX_EVEX_0F3A67, + PREFIX_EVEX_0F3A70, + PREFIX_EVEX_0F3A71, + PREFIX_EVEX_0F3A72, + PREFIX_EVEX_0F3A73, + PREFIX_EVEX_0F3ACE, + PREFIX_EVEX_0F3ACF }; enum { X86_64_06 = 0, X86_64_07, - X86_64_0D, + X86_64_0E, X86_64_16, X86_64_17, X86_64_1E, @@ -1695,15 +1757,10 @@ enum X86_64_63, X86_64_6D, X86_64_6F, - X86_64_82_REG_0, - X86_64_82_REG_1, - X86_64_82_REG_2, - X86_64_82_REG_3, - X86_64_82_REG_4, - X86_64_82_REG_5, - X86_64_82_REG_6, - X86_64_82_REG_7, + X86_64_82, X86_64_9A, + X86_64_C2, + X86_64_C3, X86_64_C4, X86_64_C5, X86_64_CE, @@ -1721,8 +1778,7 @@ enum enum { THREE_BYTE_0F38 = 0, - THREE_BYTE_0F3A, - THREE_BYTE_0F7A + THREE_BYTE_0F3A }; enum @@ -1748,11 +1804,7 @@ enum enum { - VEX_LEN_0F10_P_1 = 0, - VEX_LEN_0F10_P_3, - VEX_LEN_0F11_P_1, - VEX_LEN_0F11_P_3, - VEX_LEN_0F12_P_0_M_0, + VEX_LEN_0F12_P_0_M_0 = 0, VEX_LEN_0F12_P_0_M_1, VEX_LEN_0F12_P_2, VEX_LEN_0F13_M_0, @@ -1760,16 +1812,6 @@ enum VEX_LEN_0F16_P_0_M_1, VEX_LEN_0F16_P_2, VEX_LEN_0F17_M_0, - VEX_LEN_0F2A_P_1, - VEX_LEN_0F2A_P_3, - VEX_LEN_0F2C_P_1, - VEX_LEN_0F2C_P_3, - VEX_LEN_0F2D_P_1, - VEX_LEN_0F2D_P_3, - VEX_LEN_0F2E_P_0, - VEX_LEN_0F2E_P_2, - VEX_LEN_0F2F_P_0, - VEX_LEN_0F2F_P_2, VEX_LEN_0F41_P_0, VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, @@ -1786,25 +1828,8 @@ enum VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2, - VEX_LEN_0F51_P_1, - VEX_LEN_0F51_P_3, - VEX_LEN_0F52_P_1, - VEX_LEN_0F53_P_1, - VEX_LEN_0F58_P_1, - VEX_LEN_0F58_P_3, - VEX_LEN_0F59_P_1, - VEX_LEN_0F59_P_3, - VEX_LEN_0F5A_P_1, - VEX_LEN_0F5A_P_3, - VEX_LEN_0F5C_P_1, - VEX_LEN_0F5C_P_3, - VEX_LEN_0F5D_P_1, - VEX_LEN_0F5D_P_3, - VEX_LEN_0F5E_P_1, - VEX_LEN_0F5E_P_3, - VEX_LEN_0F5F_P_1, - VEX_LEN_0F5F_P_3, VEX_LEN_0F6E_P_2, + VEX_LEN_0F77_P_0, VEX_LEN_0F7E_P_1, VEX_LEN_0F7E_P_2, VEX_LEN_0F90_P_0, @@ -1823,8 +1848,6 @@ enum VEX_LEN_0F99_P_2, VEX_LEN_0FAE_R_2_M_0, VEX_LEN_0FAE_R_3_M_0, - VEX_LEN_0FC2_P_1, - VEX_LEN_0FC2_P_3, VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2, @@ -1836,10 +1859,6 @@ enum VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0, VEX_LEN_0F38DB_P_2, - VEX_LEN_0F38DC_P_2, - VEX_LEN_0F38DD_P_2, - VEX_LEN_0F38DE_P_2, - VEX_LEN_0F38DF_P_2, VEX_LEN_0F38F2_P_0, VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0, @@ -1855,8 +1874,6 @@ enum VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2, VEX_LEN_0F3A06_P_2, - VEX_LEN_0F3A0A_P_2, - VEX_LEN_0F3A0B_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2, VEX_LEN_0F3A16_P_2, @@ -1873,7 +1890,6 @@ enum VEX_LEN_0F3A38_P_2, VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, - VEX_LEN_0F3A44_P_2, VEX_LEN_0F3A46_P_2, VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, @@ -1903,35 +1919,57 @@ enum enum { - VEX_W_0F10_P_0 = 0, - VEX_W_0F10_P_1, - VEX_W_0F10_P_2, - VEX_W_0F10_P_3, - VEX_W_0F11_P_0, - VEX_W_0F11_P_1, - VEX_W_0F11_P_2, - VEX_W_0F11_P_3, - VEX_W_0F12_P_0_M_0, - VEX_W_0F12_P_0_M_1, - VEX_W_0F12_P_1, - VEX_W_0F12_P_2, - VEX_W_0F12_P_3, - VEX_W_0F13_M_0, - VEX_W_0F14, - VEX_W_0F15, - VEX_W_0F16_P_0_M_0, - VEX_W_0F16_P_0_M_1, - VEX_W_0F16_P_1, - VEX_W_0F16_P_2, - VEX_W_0F17_M_0, - VEX_W_0F28, - VEX_W_0F29, - VEX_W_0F2B_M_0, - VEX_W_0F2E_P_0, - VEX_W_0F2E_P_2, - VEX_W_0F2F_P_0, - VEX_W_0F2F_P_2, - VEX_W_0F41_P_0_LEN_1, + EVEX_LEN_0F6E_P_2 = 0, + EVEX_LEN_0F7E_P_1, + EVEX_LEN_0F7E_P_2, + EVEX_LEN_0FD6_P_2, + EVEX_LEN_0F3819_P_2_W_0, + EVEX_LEN_0F3819_P_2_W_1, + EVEX_LEN_0F381A_P_2_W_0, + EVEX_LEN_0F381A_P_2_W_1, + EVEX_LEN_0F381B_P_2_W_0, + EVEX_LEN_0F381B_P_2_W_1, + EVEX_LEN_0F385A_P_2_W_0, + EVEX_LEN_0F385A_P_2_W_1, + EVEX_LEN_0F385B_P_2_W_0, + EVEX_LEN_0F385B_P_2_W_1, + EVEX_LEN_0F38C6_REG_1_PREFIX_2, + EVEX_LEN_0F38C6_REG_2_PREFIX_2, + EVEX_LEN_0F38C6_REG_5_PREFIX_2, + EVEX_LEN_0F38C6_REG_6_PREFIX_2, + EVEX_LEN_0F38C7_R_1_P_2_W_0, + EVEX_LEN_0F38C7_R_1_P_2_W_1, + EVEX_LEN_0F38C7_R_2_P_2_W_0, + EVEX_LEN_0F38C7_R_2_P_2_W_1, + EVEX_LEN_0F38C7_R_5_P_2_W_0, + EVEX_LEN_0F38C7_R_5_P_2_W_1, + EVEX_LEN_0F38C7_R_6_P_2_W_0, + EVEX_LEN_0F38C7_R_6_P_2_W_1, + EVEX_LEN_0F3A18_P_2_W_0, + EVEX_LEN_0F3A18_P_2_W_1, + EVEX_LEN_0F3A19_P_2_W_0, + EVEX_LEN_0F3A19_P_2_W_1, + EVEX_LEN_0F3A1A_P_2_W_0, + EVEX_LEN_0F3A1A_P_2_W_1, + EVEX_LEN_0F3A1B_P_2_W_0, + EVEX_LEN_0F3A1B_P_2_W_1, + EVEX_LEN_0F3A23_P_2_W_0, + EVEX_LEN_0F3A23_P_2_W_1, + EVEX_LEN_0F3A38_P_2_W_0, + EVEX_LEN_0F3A38_P_2_W_1, + EVEX_LEN_0F3A39_P_2_W_0, + EVEX_LEN_0F3A39_P_2_W_1, + EVEX_LEN_0F3A3A_P_2_W_0, + EVEX_LEN_0F3A3A_P_2_W_1, + EVEX_LEN_0F3A3B_P_2_W_0, + EVEX_LEN_0F3A3B_P_2_W_1, + EVEX_LEN_0F3A43_P_2_W_0, + EVEX_LEN_0F3A43_P_2_W_1 +}; + +enum +{ + VEX_W_0F41_P_0_LEN_1 = 0, VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F42_P_2_LEN_1, @@ -1947,278 +1985,69 @@ enum VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, - VEX_W_0F50_M_0, - VEX_W_0F51_P_0, - VEX_W_0F51_P_1, - VEX_W_0F51_P_2, - VEX_W_0F51_P_3, - VEX_W_0F52_P_0, - VEX_W_0F52_P_1, - VEX_W_0F53_P_0, - VEX_W_0F53_P_1, - VEX_W_0F58_P_0, - VEX_W_0F58_P_1, - VEX_W_0F58_P_2, - VEX_W_0F58_P_3, - VEX_W_0F59_P_0, - VEX_W_0F59_P_1, - VEX_W_0F59_P_2, - VEX_W_0F59_P_3, - VEX_W_0F5A_P_0, - VEX_W_0F5A_P_1, - VEX_W_0F5A_P_3, - VEX_W_0F5B_P_0, - VEX_W_0F5B_P_1, - VEX_W_0F5B_P_2, - VEX_W_0F5C_P_0, - VEX_W_0F5C_P_1, - VEX_W_0F5C_P_2, - VEX_W_0F5C_P_3, - VEX_W_0F5D_P_0, - VEX_W_0F5D_P_1, - VEX_W_0F5D_P_2, - VEX_W_0F5D_P_3, - VEX_W_0F5E_P_0, - VEX_W_0F5E_P_1, - VEX_W_0F5E_P_2, - VEX_W_0F5E_P_3, - VEX_W_0F5F_P_0, - VEX_W_0F5F_P_1, - VEX_W_0F5F_P_2, - VEX_W_0F5F_P_3, - VEX_W_0F60_P_2, - VEX_W_0F61_P_2, - VEX_W_0F62_P_2, - VEX_W_0F63_P_2, - VEX_W_0F64_P_2, - VEX_W_0F65_P_2, - VEX_W_0F66_P_2, - VEX_W_0F67_P_2, - VEX_W_0F68_P_2, - VEX_W_0F69_P_2, - VEX_W_0F6A_P_2, - VEX_W_0F6B_P_2, - VEX_W_0F6C_P_2, - VEX_W_0F6D_P_2, - VEX_W_0F6F_P_1, - VEX_W_0F6F_P_2, - VEX_W_0F70_P_1, - VEX_W_0F70_P_2, - VEX_W_0F70_P_3, - VEX_W_0F71_R_2_P_2, - VEX_W_0F71_R_4_P_2, - VEX_W_0F71_R_6_P_2, - VEX_W_0F72_R_2_P_2, - VEX_W_0F72_R_4_P_2, - VEX_W_0F72_R_6_P_2, - VEX_W_0F73_R_2_P_2, - VEX_W_0F73_R_3_P_2, - VEX_W_0F73_R_6_P_2, - VEX_W_0F73_R_7_P_2, - VEX_W_0F74_P_2, - VEX_W_0F75_P_2, - VEX_W_0F76_P_2, - VEX_W_0F77_P_0, - VEX_W_0F7C_P_2, - VEX_W_0F7C_P_3, - VEX_W_0F7D_P_2, - VEX_W_0F7D_P_3, - VEX_W_0F7E_P_1, - VEX_W_0F7F_P_1, - VEX_W_0F7F_P_2, VEX_W_0F90_P_0_LEN_0, VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F92_P_2_LEN_0, - VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F93_P_2_LEN_0, - VEX_W_0F93_P_3_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0, - VEX_W_0FAE_R_2_M_0, - VEX_W_0FAE_R_3_M_0, - VEX_W_0FC2_P_0, - VEX_W_0FC2_P_1, - VEX_W_0FC2_P_2, - VEX_W_0FC2_P_3, - VEX_W_0FC4_P_2, - VEX_W_0FC5_P_2, - VEX_W_0FD0_P_2, - VEX_W_0FD0_P_3, - VEX_W_0FD1_P_2, - VEX_W_0FD2_P_2, - VEX_W_0FD3_P_2, - VEX_W_0FD4_P_2, - VEX_W_0FD5_P_2, - VEX_W_0FD6_P_2, - VEX_W_0FD7_P_2_M_1, - VEX_W_0FD8_P_2, - VEX_W_0FD9_P_2, - VEX_W_0FDA_P_2, - VEX_W_0FDB_P_2, - VEX_W_0FDC_P_2, - VEX_W_0FDD_P_2, - VEX_W_0FDE_P_2, - VEX_W_0FDF_P_2, - VEX_W_0FE0_P_2, - VEX_W_0FE1_P_2, - VEX_W_0FE2_P_2, - VEX_W_0FE3_P_2, - VEX_W_0FE4_P_2, - VEX_W_0FE5_P_2, - VEX_W_0FE6_P_1, - VEX_W_0FE6_P_2, - VEX_W_0FE6_P_3, - VEX_W_0FE7_P_2_M_0, - VEX_W_0FE8_P_2, - VEX_W_0FE9_P_2, - VEX_W_0FEA_P_2, - VEX_W_0FEB_P_2, - VEX_W_0FEC_P_2, - VEX_W_0FED_P_2, - VEX_W_0FEE_P_2, - VEX_W_0FEF_P_2, - VEX_W_0FF0_P_3_M_0, - VEX_W_0FF1_P_2, - VEX_W_0FF2_P_2, - VEX_W_0FF3_P_2, - VEX_W_0FF4_P_2, - VEX_W_0FF5_P_2, - VEX_W_0FF6_P_2, - VEX_W_0FF7_P_2, - VEX_W_0FF8_P_2, - VEX_W_0FF9_P_2, - VEX_W_0FFA_P_2, - VEX_W_0FFB_P_2, - VEX_W_0FFC_P_2, - VEX_W_0FFD_P_2, - VEX_W_0FFE_P_2, - VEX_W_0F3800_P_2, - VEX_W_0F3801_P_2, - VEX_W_0F3802_P_2, - VEX_W_0F3803_P_2, - VEX_W_0F3804_P_2, - VEX_W_0F3805_P_2, - VEX_W_0F3806_P_2, - VEX_W_0F3807_P_2, - VEX_W_0F3808_P_2, - VEX_W_0F3809_P_2, - VEX_W_0F380A_P_2, - VEX_W_0F380B_P_2, VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2, VEX_W_0F380F_P_2, VEX_W_0F3816_P_2, - VEX_W_0F3817_P_2, VEX_W_0F3818_P_2, VEX_W_0F3819_P_2, VEX_W_0F381A_P_2_M_0, - VEX_W_0F381C_P_2, - VEX_W_0F381D_P_2, - VEX_W_0F381E_P_2, - VEX_W_0F3820_P_2, - VEX_W_0F3821_P_2, - VEX_W_0F3822_P_2, - VEX_W_0F3823_P_2, - VEX_W_0F3824_P_2, - VEX_W_0F3825_P_2, - VEX_W_0F3828_P_2, - VEX_W_0F3829_P_2, - VEX_W_0F382A_P_2_M_0, - VEX_W_0F382B_P_2, VEX_W_0F382C_P_2_M_0, VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0, VEX_W_0F382F_P_2_M_0, - VEX_W_0F3830_P_2, - VEX_W_0F3831_P_2, - VEX_W_0F3832_P_2, - VEX_W_0F3833_P_2, - VEX_W_0F3834_P_2, - VEX_W_0F3835_P_2, VEX_W_0F3836_P_2, - VEX_W_0F3837_P_2, - VEX_W_0F3838_P_2, - VEX_W_0F3839_P_2, - VEX_W_0F383A_P_2, - VEX_W_0F383B_P_2, - VEX_W_0F383C_P_2, - VEX_W_0F383D_P_2, - VEX_W_0F383E_P_2, - VEX_W_0F383F_P_2, - VEX_W_0F3840_P_2, - VEX_W_0F3841_P_2, VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2, VEX_W_0F385A_P_2_M_0, VEX_W_0F3878_P_2, VEX_W_0F3879_P_2, - VEX_W_0F38DB_P_2, - VEX_W_0F38DC_P_2, - VEX_W_0F38DD_P_2, - VEX_W_0F38DE_P_2, - VEX_W_0F38DF_P_2, + VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2, VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2, VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2, - VEX_W_0F3A08_P_2, - VEX_W_0F3A09_P_2, - VEX_W_0F3A0A_P_2, - VEX_W_0F3A0B_P_2, - VEX_W_0F3A0C_P_2, - VEX_W_0F3A0D_P_2, - VEX_W_0F3A0E_P_2, - VEX_W_0F3A0F_P_2, - VEX_W_0F3A14_P_2, - VEX_W_0F3A15_P_2, VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, - VEX_W_0F3A20_P_2, - VEX_W_0F3A21_P_2, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2, VEX_W_0F3A39_P_2, - VEX_W_0F3A40_P_2, - VEX_W_0F3A41_P_2, - VEX_W_0F3A42_P_2, - VEX_W_0F3A44_P_2, VEX_W_0F3A46_P_2, VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2, - VEX_W_0F3A60_P_2, - VEX_W_0F3A61_P_2, - VEX_W_0F3A62_P_2, - VEX_W_0F3A63_P_2, - VEX_W_0F3ADF_P_2, + VEX_W_0F3ACE_P_2, + VEX_W_0F3ACF_P_2, EVEX_W_0F10_P_0, - EVEX_W_0F10_P_1_M_0, - EVEX_W_0F10_P_1_M_1, + EVEX_W_0F10_P_1, EVEX_W_0F10_P_2, - EVEX_W_0F10_P_3_M_0, - EVEX_W_0F10_P_3_M_1, + EVEX_W_0F10_P_3, EVEX_W_0F11_P_0, - EVEX_W_0F11_P_1_M_0, - EVEX_W_0F11_P_1_M_1, + EVEX_W_0F11_P_1, EVEX_W_0F11_P_2, - EVEX_W_0F11_P_3_M_0, - EVEX_W_0F11_P_3_M_1, + EVEX_W_0F11_P_3, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, @@ -2240,7 +2069,6 @@ enum EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, - EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, @@ -2297,7 +2125,6 @@ enum EVEX_W_0F6B_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, - EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F6F_P_3, @@ -2314,11 +2141,9 @@ enum EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_2, EVEX_W_0F7A_P_3, - EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_2, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, - EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0F7F_P_3, @@ -2388,11 +2213,23 @@ enum EVEX_W_0F3839_P_1, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, + EVEX_W_0F3852_P_1, + EVEX_W_0F3854_P_2, + EVEX_W_0F3855_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, + EVEX_W_0F3862_P_2, + EVEX_W_0F3863_P_2, EVEX_W_0F3866_P_2, + EVEX_W_0F3868_P_3, + EVEX_W_0F3870_P_2, + EVEX_W_0F3871_P_2, + EVEX_W_0F3872_P_1, + EVEX_W_0F3872_P_2, + EVEX_W_0F3872_P_3, + EVEX_W_0F3873_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, @@ -2418,14 +2255,12 @@ enum EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, - EVEX_W_0F3A16_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, - EVEX_W_0F3A22_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, @@ -2440,7 +2275,13 @@ enum EVEX_W_0F3A56_P_2, EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, - EVEX_W_0F3A67_P_2 + EVEX_W_0F3A67_P_2, + EVEX_W_0F3A70_P_2, + EVEX_W_0F3A71_P_2, + EVEX_W_0F3A72_P_2, + EVEX_W_0F3A73_P_2, + EVEX_W_0F3ACE_P_2, + EVEX_W_0F3ACF_P_2 }; typedef void (*op_rtn) (int bytemode, int sizeflag); @@ -2488,13 +2329,12 @@ struct dis386 { prefix and behave as 'S' otherwise 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) 'X' => print 's', 'd' depending on data16 prefix (for XMM) - 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and - suffix_always is true. + 'Y' unused. 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise '!' => change condition from true to false or from false to true. '%' => add 1 upper case letter to the macro. - '^' => print 'w' or 'l' depending on operand size prefix or - suffix_always is true (lcall/ljmp). + '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size + prefix or suffix_always is true (lcall/ljmp). '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending on operand size prefix. '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction @@ -2540,7 +2380,7 @@ static const struct dis386 dis386[] = { { "orS", { Gv, EvS }, 0 }, { "orB", { AL, Ib }, 0 }, { "orS", { eAX, Iv }, 0 }, - { X86_64_TABLE (X86_64_0D) }, + { X86_64_TABLE (X86_64_0E) }, { Bad_Opcode }, /* 0x0f extended opcode escape */ /* 10 */ { "adcB", { Ebh1, Gb }, 0 }, @@ -2671,7 +2511,7 @@ static const struct dis386 dis386[] = { /* 80 */ { REG_TABLE (REG_80) }, { REG_TABLE (REG_81) }, - { REG_TABLE (REG_82) }, + { X86_64_TABLE (X86_64_82) }, { REG_TABLE (REG_83) }, { "testB", { Eb, Gb }, 0 }, { "testS", { Ev, Gv }, 0 }, @@ -2743,8 +2583,8 @@ static const struct dis386 dis386[] = { /* c0 */ { REG_TABLE (REG_C0) }, { REG_TABLE (REG_C1) }, - { "retT", { Iw, BND }, 0 }, - { "retT", { BND }, 0 }, + { X86_64_TABLE (X86_64_C2) }, + { X86_64_TABLE (X86_64_C3) }, { X86_64_TABLE (X86_64_C4) }, { X86_64_TABLE (X86_64_C5) }, { REG_TABLE (REG_C6) }, @@ -2826,7 +2666,7 @@ static const struct dis386 dis386_twobyte[] = { { "sysret%LP", { XX }, 0 }, /* 08 */ { "invd", { XX }, 0 }, - { "wbinvd", { XX }, 0 }, + { PREFIX_TABLE (PREFIX_0F09) }, { Bad_Opcode }, { "ud2", { XX }, 0 }, { Bad_Opcode }, @@ -2847,9 +2687,9 @@ static const struct dis386 dis386_twobyte[] = { { "nopQ", { Ev }, 0 }, { PREFIX_TABLE (PREFIX_0F1A) }, { PREFIX_TABLE (PREFIX_0F1B) }, + { PREFIX_TABLE (PREFIX_0F1C) }, { "nopQ", { Ev }, 0 }, - { "nopQ", { Ev }, 0 }, - { "nopQ", { Ev }, 0 }, + { PREFIX_TABLE (PREFIX_0F1E) }, { "nopQ", { Ev }, 0 }, /* 20 */ { "movZ", { Rm, Cm }, 0 }, @@ -2874,8 +2714,8 @@ static const struct dis386 dis386_twobyte[] = { { "rdtsc", { XX }, 0 }, { "rdmsr", { XX }, 0 }, { "rdpmc", { XX }, 0 }, - { "sysenter", { XX }, 0 }, - { "sysexit", { XX }, 0 }, + { "sysenter", { SEP }, 0 }, + { "sysexit", { SEP }, 0 }, { Bad_Opcode }, { "getsec", { XX }, 0 }, /* 38 */ @@ -2953,7 +2793,7 @@ static const struct dis386 dis386_twobyte[] = { /* 78 */ { PREFIX_TABLE (PREFIX_0F78) }, { PREFIX_TABLE (PREFIX_0F79) }, - { THREE_BYTE_TABLE (THREE_BYTE_0F7A) }, + { Bad_Opcode }, { Bad_Opcode }, { PREFIX_TABLE (PREFIX_0F7C) }, { PREFIX_TABLE (PREFIX_0F7D) }, @@ -3024,7 +2864,7 @@ static const struct dis386 dis386_twobyte[] = { { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */ /* b8 */ { PREFIX_TABLE (PREFIX_0FB8) }, - { "ud1", { XX }, 0 }, + { "ud1S", { Gv, Ev }, 0 }, { REG_TABLE (REG_0FBA) }, { "btcS", { Evh1, Gv }, 0 }, { PREFIX_TABLE (PREFIX_0FBC) }, @@ -3102,7 +2942,7 @@ static const struct dis386 dis386_twobyte[] = { { "paddb", { MX, EM }, PREFIX_OPCODE }, { "paddw", { MX, EM }, PREFIX_OPCODE }, { "paddd", { MX, EM }, PREFIX_OPCODE }, - { Bad_Opcode }, + { "ud0S", { Gv, Ev }, 0 }, }; static const unsigned char onebyte_has_modrm[256] = { @@ -3142,11 +2982,11 @@ static const unsigned char twobyte_has_modrm[256] = { /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ - /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */ + /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */ /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ - /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */ + /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */ /* ------------------------------- */ /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ }; @@ -3409,17 +3249,6 @@ static const struct dis386 reg_table[][8] = { { "xorQ", { Evh1, Iv }, 0 }, { "cmpQ", { Ev, Iv }, 0 }, }, - /* REG_82 */ - { - { X86_64_TABLE (X86_64_82_REG_0) }, - { X86_64_TABLE (X86_64_82_REG_1) }, - { X86_64_TABLE (X86_64_82_REG_2) }, - { X86_64_TABLE (X86_64_82_REG_3) }, - { X86_64_TABLE (X86_64_82_REG_4) }, - { X86_64_TABLE (X86_64_82_REG_5) }, - { X86_64_TABLE (X86_64_82_REG_6) }, - { X86_64_TABLE (X86_64_82_REG_7) }, - }, /* REG_83 */ { { "addQ", { Evh1, sIb }, 0 }, @@ -3448,7 +3277,7 @@ static const struct dis386 reg_table[][8] = { { "rcrA", { Eb, Ib }, 0 }, { "shlA", { Eb, Ib }, 0 }, { "shrA", { Eb, Ib }, 0 }, - { Bad_Opcode }, + { "shlA", { Eb, Ib }, 0 }, { "sarA", { Eb, Ib }, 0 }, }, /* REG_C1 */ @@ -3459,7 +3288,7 @@ static const struct dis386 reg_table[][8] = { { "rcrQ", { Ev, Ib }, 0 }, { "shlQ", { Ev, Ib }, 0 }, { "shrQ", { Ev, Ib }, 0 }, - { Bad_Opcode }, + { "shlQ", { Ev, Ib }, 0 }, { "sarQ", { Ev, Ib }, 0 }, }, /* REG_C6 */ @@ -3492,7 +3321,7 @@ static const struct dis386 reg_table[][8] = { { "rcrA", { Eb, I1 }, 0 }, { "shlA", { Eb, I1 }, 0 }, { "shrA", { Eb, I1 }, 0 }, - { Bad_Opcode }, + { "shlA", { Eb, I1 }, 0 }, { "sarA", { Eb, I1 }, 0 }, }, /* REG_D1 */ @@ -3503,7 +3332,7 @@ static const struct dis386 reg_table[][8] = { { "rcrQ", { Ev, I1 }, 0 }, { "shlQ", { Ev, I1 }, 0 }, { "shrQ", { Ev, I1 }, 0 }, - { Bad_Opcode }, + { "shlQ", { Ev, I1 }, 0 }, { "sarQ", { Ev, I1 }, 0 }, }, /* REG_D2 */ @@ -3514,7 +3343,7 @@ static const struct dis386 reg_table[][8] = { { "rcrA", { Eb, CL }, 0 }, { "shlA", { Eb, CL }, 0 }, { "shrA", { Eb, CL }, 0 }, - { Bad_Opcode }, + { "shlA", { Eb, CL }, 0 }, { "sarA", { Eb, CL }, 0 }, }, /* REG_D3 */ @@ -3525,13 +3354,13 @@ static const struct dis386 reg_table[][8] = { { "rcrQ", { Ev, CL }, 0 }, { "shlQ", { Ev, CL }, 0 }, { "shrQ", { Ev, CL }, 0 }, - { Bad_Opcode }, + { "shlQ", { Ev, CL }, 0 }, { "sarQ", { Ev, CL }, 0 }, }, /* REG_F6 */ { { "testA", { Eb, Ib }, 0 }, - { Bad_Opcode }, + { "testA", { Eb, Ib }, 0 }, { "notA", { Ebh1 }, 0 }, { "negA", { Ebh1 }, 0 }, { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */ @@ -3542,7 +3371,7 @@ static const struct dis386 reg_table[][8] = { /* REG_F7 */ { { "testQ", { Ev, Iv }, 0 }, - { Bad_Opcode }, + { "testQ", { Ev, Iv }, 0 }, { "notQ", { Evh1 }, 0 }, { "negQ", { Evh1 }, 0 }, { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */ @@ -3559,9 +3388,9 @@ static const struct dis386 reg_table[][8] = { { { "incQ", { Evh1 }, 0 }, { "decQ", { Evh1 }, 0 }, - { "call{&|}", { indirEv, BND }, 0 }, + { "call{&|}", { NOTRACK, indirEv, BND }, 0 }, { MOD_TABLE (MOD_FF_REG_3) }, - { "jmp{&|}", { indirEv, BND }, 0 }, + { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 }, { MOD_TABLE (MOD_FF_REG_5) }, { "pushU", { stackEv }, 0 }, { Bad_Opcode }, @@ -3610,6 +3439,28 @@ static const struct dis386 reg_table[][8] = { { MOD_TABLE (MOD_0F18_REG_6) }, { MOD_TABLE (MOD_0F18_REG_7) }, }, + /* REG_0F1C_P_0_MOD_0 */ + { + { "cldemote", { Mb }, 0 }, + { "nopQ", { Ev }, 0 }, + { "nopQ", { Ev }, 0 }, + { "nopQ", { Ev }, 0 }, + { "nopQ", { Ev }, 0 }, + { "nopQ", { Ev }, 0 }, + { "nopQ", { Ev }, 0 }, + { "nopQ", { Ev }, 0 }, + }, + /* REG_0F1E_P_1_MOD_3 */ + { + { "nopQ", { Ev }, 0 }, + { "rdsspK", { Rdq }, PREFIX_OPCODE }, + { "nopQ", { Ev }, 0 }, + { "nopQ", { Ev }, 0 }, + { "nopQ", { Ev }, 0 }, + { "nopQ", { Ev }, 0 }, + { "nopQ", { Ev }, 0 }, + { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) }, + }, /* REG_0F71 */ { { Bad_Opcode }, @@ -3741,33 +3592,32 @@ static const struct dis386 reg_table[][8] = { }, /* REG_XOP_LWP */ { - { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 }, - { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 }, + { "lwpins", { { OP_LWP_E, 0 }, Ed, Id }, 0 }, + { "lwpval", { { OP_LWP_E, 0 }, Ed, Id }, 0 }, }, /* REG_XOP_TBM_01 */ { { Bad_Opcode }, - { "blcfill", { { OP_LWP_E, 0 }, Ev }, 0 }, - { "blsfill", { { OP_LWP_E, 0 }, Ev }, 0 }, - { "blcs", { { OP_LWP_E, 0 }, Ev }, 0 }, - { "tzmsk", { { OP_LWP_E, 0 }, Ev }, 0 }, - { "blcic", { { OP_LWP_E, 0 }, Ev }, 0 }, - { "blsic", { { OP_LWP_E, 0 }, Ev }, 0 }, - { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 }, + { "blcfill", { { OP_LWP_E, 0 }, Edq }, 0 }, + { "blsfill", { { OP_LWP_E, 0 }, Edq }, 0 }, + { "blcs", { { OP_LWP_E, 0 }, Edq }, 0 }, + { "tzmsk", { { OP_LWP_E, 0 }, Edq }, 0 }, + { "blcic", { { OP_LWP_E, 0 }, Edq }, 0 }, + { "blsic", { { OP_LWP_E, 0 }, Edq }, 0 }, + { "t1mskc", { { OP_LWP_E, 0 }, Edq }, 0 }, }, /* REG_XOP_TBM_02 */ { { Bad_Opcode }, - { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 }, + { "blcmsk", { { OP_LWP_E, 0 }, Edq }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "blci", { { OP_LWP_E, 0 }, Ev }, 0 }, + { "blci", { { OP_LWP_E, 0 }, Edq }, 0 }, }, -#define NEED_REG_TABLE -#include "i386-dis-evex.h" -#undef NEED_REG_TABLE + +#include "i386-dis-evex-reg.h" }; static const struct dis386 prefix_table[][4] = { @@ -3779,6 +3629,59 @@ static const struct dis386 prefix_table[][4] = { { NULL, { { NULL, 0 } }, PREFIX_IGNORED } }, + /* PREFIX_0F01_REG_3_MOD_1 */ + { + { "vmmcall", { Skip_MODRM }, 0 }, + { "vmgexit", { Skip_MODRM }, 0 }, + { Bad_Opcode }, + { "vmgexit", { Skip_MODRM }, 0 }, + }, + + /* PREFIX_0F01_REG_5_MOD_0 */ + { + { Bad_Opcode }, + { "rstorssp", { Mq }, PREFIX_OPCODE }, + }, + + /* PREFIX_0F01_REG_5_MOD_3_RM_0 */ + { + { "serialize", { Skip_MODRM }, PREFIX_OPCODE }, + { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE }, + { Bad_Opcode }, + { "xsuspldtrk", { Skip_MODRM }, PREFIX_OPCODE }, + }, + + /* PREFIX_0F01_REG_5_MOD_3_RM_1 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { "xresldtrk", { Skip_MODRM }, PREFIX_OPCODE }, + }, + + /* PREFIX_0F01_REG_5_MOD_3_RM_2 */ + { + { Bad_Opcode }, + { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE }, + }, + + /* PREFIX_0F01_REG_7_MOD_3_RM_2 */ + { + { "monitorx", { { OP_Monitor, 0 } }, 0 }, + { "mcommit", { Skip_MODRM }, 0 }, + }, + + /* PREFIX_0F01_REG_7_MOD_3_RM_3 */ + { + { "mwaitx", { { OP_Mwait, eBX_reg } }, 0 }, + }, + + /* PREFIX_0F09 */ + { + { "wbinvd", { XX }, 0 }, + { "wbnoinvd", { XX }, 0 }, + }, + /* PREFIX_0F10 */ { { "movups", { XM, EXx }, PREFIX_OPCODE }, @@ -3822,16 +3725,32 @@ static const struct dis386 prefix_table[][4] = { { { MOD_TABLE (MOD_0F1B_PREFIX_0) }, { MOD_TABLE (MOD_0F1B_PREFIX_1) }, - { "bndmov", { Ebnd, Gbnd }, 0 }, + { "bndmov", { EbndS, Gbnd }, 0 }, { "bndcn", { Gbnd, Ev_bnd }, 0 }, }, + /* PREFIX_0F1C */ + { + { MOD_TABLE (MOD_0F1C_PREFIX_0) }, + { "nopQ", { Ev }, PREFIX_OPCODE }, + { "nopQ", { Ev }, PREFIX_OPCODE }, + { "nopQ", { Ev }, PREFIX_OPCODE }, + }, + + /* PREFIX_0F1E */ + { + { "nopQ", { Ev }, PREFIX_OPCODE }, + { MOD_TABLE (MOD_0F1E_PREFIX_1) }, + { "nopQ", { Ev }, PREFIX_OPCODE }, + { "nopQ", { Ev }, PREFIX_OPCODE }, + }, + /* PREFIX_0F2A */ { { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE }, - { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE }, + { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE }, { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE }, - { "cvtsi2sd%LQ", { XM, Ev }, 0 }, + { "cvtsi2sd%LQ", { XM, Edq }, 0 }, }, /* PREFIX_0F2B */ @@ -3845,17 +3764,17 @@ static const struct dis386 prefix_table[][4] = { /* PREFIX_0F2C */ { { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE }, - { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE }, + { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE }, { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE }, - { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE }, + { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE }, }, /* PREFIX_0F2D */ { { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE }, - { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE }, + { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE }, { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE }, - { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE }, + { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE }, }, /* PREFIX_0F2E */ @@ -4065,50 +3984,69 @@ static const struct dis386 prefix_table[][4] = { { "movdqa", { EXxS, XM }, PREFIX_OPCODE }, }, - /* PREFIX_0FAE_REG_0 */ + /* PREFIX_0FAE_REG_0_MOD_3 */ { { Bad_Opcode }, { "rdfsbase", { Ev }, 0 }, }, - /* PREFIX_0FAE_REG_1 */ + /* PREFIX_0FAE_REG_1_MOD_3 */ { { Bad_Opcode }, { "rdgsbase", { Ev }, 0 }, }, - /* PREFIX_0FAE_REG_2 */ + /* PREFIX_0FAE_REG_2_MOD_3 */ { { Bad_Opcode }, { "wrfsbase", { Ev }, 0 }, }, - /* PREFIX_0FAE_REG_3 */ + /* PREFIX_0FAE_REG_3_MOD_3 */ { { Bad_Opcode }, { "wrgsbase", { Ev }, 0 }, }, - /* PREFIX_MOD_0_0FAE_REG_4 */ + /* PREFIX_0FAE_REG_4_MOD_0 */ { { "xsave", { FXSAVE }, 0 }, { "ptwrite%LQ", { Edq }, 0 }, }, - /* PREFIX_MOD_3_0FAE_REG_4 */ + /* PREFIX_0FAE_REG_4_MOD_3 */ { { Bad_Opcode }, { "ptwrite%LQ", { Edq }, 0 }, }, - /* PREFIX_0FAE_REG_6 */ + /* PREFIX_0FAE_REG_5_MOD_0 */ { - { "xsaveopt", { FXSAVE }, 0 }, - { Bad_Opcode }, - { "clwb", { Mb }, 0 }, + { "xrstor", { FXSAVE }, PREFIX_OPCODE }, + }, + + /* PREFIX_0FAE_REG_5_MOD_3 */ + { + { "lfence", { Skip_MODRM }, 0 }, + { "incsspK", { Rdq }, PREFIX_OPCODE }, + }, + + /* PREFIX_0FAE_REG_6_MOD_0 */ + { + { "xsaveopt", { FXSAVE }, PREFIX_OPCODE }, + { "clrssbsy", { Mq }, PREFIX_OPCODE }, + { "clwb", { Mb }, PREFIX_OPCODE }, }, - /* PREFIX_0FAE_REG_7 */ + /* PREFIX_0FAE_REG_6_MOD_3 */ + { + { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) }, + { "umonitor", { Eva }, PREFIX_OPCODE }, + { "tpause", { Edq }, PREFIX_OPCODE }, + { "umwait", { Edq }, PREFIX_OPCODE }, + }, + + /* PREFIX_0FAE_REG_7_MOD_0 */ { { "clflush", { Mb }, 0 }, { Bad_Opcode }, @@ -4143,26 +4081,26 @@ static const struct dis386 prefix_table[][4] = { { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE }, }, - /* PREFIX_MOD_0_0FC3 */ + /* PREFIX_0FC3_MOD_0 */ { - { "movntiS", { Ev, Gv }, PREFIX_OPCODE }, + { "movntiS", { Edq, Gdq }, PREFIX_OPCODE }, }, - /* PREFIX_MOD_0_0FC7_REG_6 */ + /* PREFIX_0FC7_REG_6_MOD_0 */ { { "vmptrld",{ Mq }, 0 }, { "vmxon", { Mq }, 0 }, { "vmclear",{ Mq }, 0 }, }, - /* PREFIX_MOD_3_0FC7_REG_6 */ + /* PREFIX_0FC7_REG_6_MOD_3 */ { { "rdrand", { Ev }, 0 }, { Bad_Opcode }, { "rdrand", { Ev }, 0 } }, - /* PREFIX_MOD_3_0FC7_REG_7 */ + /* PREFIX_0FC7_REG_7_MOD_3 */ { { "rdseed", { Ev }, 0 }, { "rdpid", { Em }, 0 }, @@ -4483,6 +4421,13 @@ static const struct dis386 prefix_table[][4] = { { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE }, }, + /* PREFIX_0F38CF */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE }, + }, + /* PREFIX_0F38DB */ { { Bad_Opcode }, @@ -4534,14 +4479,34 @@ static const struct dis386 prefix_table[][4] = { { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE }, }, - /* PREFIX_0F38F6 */ + /* PREFIX_0F38F5 */ { { Bad_Opcode }, + { Bad_Opcode }, + { MOD_TABLE (MOD_0F38F5_PREFIX_2) }, + }, + + /* PREFIX_0F38F6 */ + { + { MOD_TABLE (MOD_0F38F6_PREFIX_0) }, { "adoxS", { Gdq, Edq}, PREFIX_OPCODE }, { "adcxS", { Gdq, Edq}, PREFIX_OPCODE }, { Bad_Opcode }, }, + /* PREFIX_0F38F8 */ + { + { Bad_Opcode }, + { MOD_TABLE (MOD_0F38F8_PREFIX_1) }, + { MOD_TABLE (MOD_0F38F8_PREFIX_2) }, + { MOD_TABLE (MOD_0F38F8_PREFIX_3) }, + }, + + /* PREFIX_0F38F9 */ + { + { MOD_TABLE (MOD_0F38F9_PREFIX_0) }, + }, + /* PREFIX_0F3A08 */ { { Bad_Opcode }, @@ -4672,14 +4637,14 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { "pcmpestrm", { XM, EXx, Ib }, PREFIX_OPCODE }, + { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE }, }, /* PREFIX_0F3A61 */ { { Bad_Opcode }, { Bad_Opcode }, - { "pcmpestri", { XM, EXx, Ib }, PREFIX_OPCODE }, + { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE }, }, /* PREFIX_0F3A62 */ @@ -4701,6 +4666,20 @@ static const struct dis386 prefix_table[][4] = { { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE }, }, + /* PREFIX_0F3ACE */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE }, + }, + + /* PREFIX_0F3ACF */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE }, + }, + /* PREFIX_0F3ADF */ { { Bad_Opcode }, @@ -4710,71 +4689,71 @@ static const struct dis386 prefix_table[][4] = { /* PREFIX_VEX_0F10 */ { - { VEX_W_TABLE (VEX_W_0F10_P_0) }, - { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) }, - { VEX_W_TABLE (VEX_W_0F10_P_2) }, - { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) }, + { "vmovups", { XM, EXx }, 0 }, + { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 }, + { "vmovupd", { XM, EXx }, 0 }, + { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 }, }, /* PREFIX_VEX_0F11 */ { - { VEX_W_TABLE (VEX_W_0F11_P_0) }, - { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) }, - { VEX_W_TABLE (VEX_W_0F11_P_2) }, - { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) }, + { "vmovups", { EXxS, XM }, 0 }, + { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 }, + { "vmovupd", { EXxS, XM }, 0 }, + { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 }, }, /* PREFIX_VEX_0F12 */ { { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) }, - { VEX_W_TABLE (VEX_W_0F12_P_1) }, + { "vmovsldup", { XM, EXx }, 0 }, { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) }, - { VEX_W_TABLE (VEX_W_0F12_P_3) }, + { "vmovddup", { XM, EXymmq }, 0 }, }, /* PREFIX_VEX_0F16 */ { { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) }, - { VEX_W_TABLE (VEX_W_0F16_P_1) }, + { "vmovshdup", { XM, EXx }, 0 }, { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) }, }, /* PREFIX_VEX_0F2A */ { { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) }, + { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Edq }, 0 }, { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) }, + { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Edq }, 0 }, }, /* PREFIX_VEX_0F2C */ { { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) }, + { "vcvttss2si", { Gdq, EXdScalar }, 0 }, { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) }, + { "vcvttsd2si", { Gdq, EXqScalar }, 0 }, }, /* PREFIX_VEX_0F2D */ { { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) }, + { "vcvtss2si", { Gdq, EXdScalar }, 0 }, { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) }, + { "vcvtsd2si", { Gdq, EXqScalar }, 0 }, }, /* PREFIX_VEX_0F2E */ { - { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) }, + { "vucomiss", { XMScalar, EXdScalar }, 0 }, { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) }, + { "vucomisd", { XMScalar, EXqScalar }, 0 }, }, /* PREFIX_VEX_0F2F */ { - { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) }, + { "vcomiss", { XMScalar, EXdScalar }, 0 }, { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) }, + { "vcomisd", { XMScalar, EXqScalar }, 0 }, }, /* PREFIX_VEX_0F41 */ @@ -4835,183 +4814,183 @@ static const struct dis386 prefix_table[][4] = { /* PREFIX_VEX_0F51 */ { - { VEX_W_TABLE (VEX_W_0F51_P_0) }, - { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) }, - { VEX_W_TABLE (VEX_W_0F51_P_2) }, - { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) }, + { "vsqrtps", { XM, EXx }, 0 }, + { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, + { "vsqrtpd", { XM, EXx }, 0 }, + { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 }, }, /* PREFIX_VEX_0F52 */ { - { VEX_W_TABLE (VEX_W_0F52_P_0) }, - { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) }, + { "vrsqrtps", { XM, EXx }, 0 }, + { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, }, /* PREFIX_VEX_0F53 */ { - { VEX_W_TABLE (VEX_W_0F53_P_0) }, - { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) }, + { "vrcpps", { XM, EXx }, 0 }, + { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 }, }, /* PREFIX_VEX_0F58 */ { - { VEX_W_TABLE (VEX_W_0F58_P_0) }, - { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) }, - { VEX_W_TABLE (VEX_W_0F58_P_2) }, - { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) }, + { "vaddps", { XM, Vex, EXx }, 0 }, + { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 }, + { "vaddpd", { XM, Vex, EXx }, 0 }, + { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 }, }, /* PREFIX_VEX_0F59 */ { - { VEX_W_TABLE (VEX_W_0F59_P_0) }, - { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) }, - { VEX_W_TABLE (VEX_W_0F59_P_2) }, - { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) }, + { "vmulps", { XM, Vex, EXx }, 0 }, + { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 }, + { "vmulpd", { XM, Vex, EXx }, 0 }, + { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 }, }, /* PREFIX_VEX_0F5A */ { - { VEX_W_TABLE (VEX_W_0F5A_P_0) }, - { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) }, - { "vcvtpd2ps%XY", { XMM, EXx }, 0 }, - { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) }, + { "vcvtps2pd", { XM, EXxmmq }, 0 }, + { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 }, + { "vcvtpd2ps%XY",{ XMM, EXx }, 0 }, + { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 }, }, /* PREFIX_VEX_0F5B */ { - { VEX_W_TABLE (VEX_W_0F5B_P_0) }, - { VEX_W_TABLE (VEX_W_0F5B_P_1) }, - { VEX_W_TABLE (VEX_W_0F5B_P_2) }, + { "vcvtdq2ps", { XM, EXx }, 0 }, + { "vcvttps2dq", { XM, EXx }, 0 }, + { "vcvtps2dq", { XM, EXx }, 0 }, }, /* PREFIX_VEX_0F5C */ { - { VEX_W_TABLE (VEX_W_0F5C_P_0) }, - { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) }, - { VEX_W_TABLE (VEX_W_0F5C_P_2) }, - { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) }, + { "vsubps", { XM, Vex, EXx }, 0 }, + { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 }, + { "vsubpd", { XM, Vex, EXx }, 0 }, + { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 }, }, /* PREFIX_VEX_0F5D */ { - { VEX_W_TABLE (VEX_W_0F5D_P_0) }, - { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) }, - { VEX_W_TABLE (VEX_W_0F5D_P_2) }, - { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) }, + { "vminps", { XM, Vex, EXx }, 0 }, + { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 }, + { "vminpd", { XM, Vex, EXx }, 0 }, + { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 }, }, /* PREFIX_VEX_0F5E */ { - { VEX_W_TABLE (VEX_W_0F5E_P_0) }, - { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) }, - { VEX_W_TABLE (VEX_W_0F5E_P_2) }, - { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) }, + { "vdivps", { XM, Vex, EXx }, 0 }, + { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 }, + { "vdivpd", { XM, Vex, EXx }, 0 }, + { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 }, }, /* PREFIX_VEX_0F5F */ { - { VEX_W_TABLE (VEX_W_0F5F_P_0) }, - { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) }, - { VEX_W_TABLE (VEX_W_0F5F_P_2) }, - { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) }, + { "vmaxps", { XM, Vex, EXx }, 0 }, + { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 }, + { "vmaxpd", { XM, Vex, EXx }, 0 }, + { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 }, }, /* PREFIX_VEX_0F60 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F60_P_2) }, + { "vpunpcklbw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F61 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F61_P_2) }, + { "vpunpcklwd", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F62 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F62_P_2) }, + { "vpunpckldq", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F63 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F63_P_2) }, + { "vpacksswb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F64 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F64_P_2) }, + { "vpcmpgtb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F65 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F65_P_2) }, + { "vpcmpgtw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F66 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F66_P_2) }, + { "vpcmpgtd", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F67 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F67_P_2) }, + { "vpackuswb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F68 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F68_P_2) }, + { "vpunpckhbw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F69 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F69_P_2) }, + { "vpunpckhwd", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F6A */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F6A_P_2) }, + { "vpunpckhdq", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F6B */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F6B_P_2) }, + { "vpackssdw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F6C */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F6C_P_2) }, + { "vpunpcklqdq", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F6D */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F6D_P_2) }, + { "vpunpckhqdq", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F6E */ @@ -5024,128 +5003,128 @@ static const struct dis386 prefix_table[][4] = { /* PREFIX_VEX_0F6F */ { { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F6F_P_1) }, - { VEX_W_TABLE (VEX_W_0F6F_P_2) }, + { "vmovdqu", { XM, EXx }, 0 }, + { "vmovdqa", { XM, EXx }, 0 }, }, /* PREFIX_VEX_0F70 */ { { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F70_P_1) }, - { VEX_W_TABLE (VEX_W_0F70_P_2) }, - { VEX_W_TABLE (VEX_W_0F70_P_3) }, + { "vpshufhw", { XM, EXx, Ib }, 0 }, + { "vpshufd", { XM, EXx, Ib }, 0 }, + { "vpshuflw", { XM, EXx, Ib }, 0 }, }, /* PREFIX_VEX_0F71_REG_2 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) }, + { "vpsrlw", { Vex, XS, Ib }, 0 }, }, /* PREFIX_VEX_0F71_REG_4 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) }, + { "vpsraw", { Vex, XS, Ib }, 0 }, }, /* PREFIX_VEX_0F71_REG_6 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) }, + { "vpsllw", { Vex, XS, Ib }, 0 }, }, /* PREFIX_VEX_0F72_REG_2 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) }, + { "vpsrld", { Vex, XS, Ib }, 0 }, }, /* PREFIX_VEX_0F72_REG_4 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) }, + { "vpsrad", { Vex, XS, Ib }, 0 }, }, /* PREFIX_VEX_0F72_REG_6 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) }, + { "vpslld", { Vex, XS, Ib }, 0 }, }, /* PREFIX_VEX_0F73_REG_2 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) }, + { "vpsrlq", { Vex, XS, Ib }, 0 }, }, /* PREFIX_VEX_0F73_REG_3 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) }, + { "vpsrldq", { Vex, XS, Ib }, 0 }, }, /* PREFIX_VEX_0F73_REG_6 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) }, + { "vpsllq", { Vex, XS, Ib }, 0 }, }, /* PREFIX_VEX_0F73_REG_7 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) }, + { "vpslldq", { Vex, XS, Ib }, 0 }, }, /* PREFIX_VEX_0F74 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F74_P_2) }, + { "vpcmpeqb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F75 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F75_P_2) }, + { "vpcmpeqw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F76 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F76_P_2) }, + { "vpcmpeqd", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F77 */ { - { VEX_W_TABLE (VEX_W_0F77_P_0) }, + { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) }, }, /* PREFIX_VEX_0F7C */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F7C_P_2) }, - { VEX_W_TABLE (VEX_W_0F7C_P_3) }, + { "vhaddpd", { XM, Vex, EXx }, 0 }, + { "vhaddps", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F7D */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F7D_P_2) }, - { VEX_W_TABLE (VEX_W_0F7D_P_3) }, + { "vhsubpd", { XM, Vex, EXx }, 0 }, + { "vhsubps", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F7E */ @@ -5158,8 +5137,8 @@ static const struct dis386 prefix_table[][4] = { /* PREFIX_VEX_0F7F */ { { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F7F_P_1) }, - { VEX_W_TABLE (VEX_W_0F7F_P_2) }, + { "vmovdqu", { EXxS, XM }, 0 }, + { "vmovdqa", { EXxS, XM }, 0 }, }, /* PREFIX_VEX_0F90 */ @@ -5208,10 +5187,10 @@ static const struct dis386 prefix_table[][4] = { /* PREFIX_VEX_0FC2 */ { - { VEX_W_TABLE (VEX_W_0FC2_P_0) }, - { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) }, - { VEX_W_TABLE (VEX_W_0FC2_P_2) }, - { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) }, + { "vcmpps", { XM, Vex, EXx, VCMP }, 0 }, + { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 }, + { "vcmppd", { XM, Vex, EXx, VCMP }, 0 }, + { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 }, }, /* PREFIX_VEX_0FC4 */ @@ -5232,43 +5211,43 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FD0_P_2) }, - { VEX_W_TABLE (VEX_W_0FD0_P_3) }, + { "vaddsubpd", { XM, Vex, EXx }, 0 }, + { "vaddsubps", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FD1 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FD1_P_2) }, + { "vpsrlw", { XM, Vex, EXxmm }, 0 }, }, /* PREFIX_VEX_0FD2 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FD2_P_2) }, + { "vpsrld", { XM, Vex, EXxmm }, 0 }, }, /* PREFIX_VEX_0FD3 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FD3_P_2) }, + { "vpsrlq", { XM, Vex, EXxmm }, 0 }, }, /* PREFIX_VEX_0FD4 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FD4_P_2) }, + { "vpaddq", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FD5 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FD5_P_2) }, + { "vpmullw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FD6 */ @@ -5289,106 +5268,106 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FD8_P_2) }, + { "vpsubusb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FD9 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FD9_P_2) }, + { "vpsubusw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FDA */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FDA_P_2) }, + { "vpminub", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FDB */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FDB_P_2) }, + { "vpand", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FDC */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FDC_P_2) }, + { "vpaddusb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FDD */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FDD_P_2) }, + { "vpaddusw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FDE */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FDE_P_2) }, + { "vpmaxub", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FDF */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FDF_P_2) }, + { "vpandn", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FE0 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FE0_P_2) }, + { "vpavgb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FE1 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FE1_P_2) }, + { "vpsraw", { XM, Vex, EXxmm }, 0 }, }, /* PREFIX_VEX_0FE2 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FE2_P_2) }, + { "vpsrad", { XM, Vex, EXxmm }, 0 }, }, /* PREFIX_VEX_0FE3 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FE3_P_2) }, + { "vpavgw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FE4 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FE4_P_2) }, + { "vpmulhuw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FE5 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FE5_P_2) }, + { "vpmulhw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FE6 */ { { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FE6_P_1) }, - { VEX_W_TABLE (VEX_W_0FE6_P_2) }, - { VEX_W_TABLE (VEX_W_0FE6_P_3) }, + { "vcvtdq2pd", { XM, EXxmmq }, 0 }, + { "vcvttpd2dq%XY", { XMM, EXx }, 0 }, + { "vcvtpd2dq%XY", { XMM, EXx }, 0 }, }, /* PREFIX_VEX_0FE7 */ @@ -5402,56 +5381,56 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FE8_P_2) }, + { "vpsubsb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FE9 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FE9_P_2) }, + { "vpsubsw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FEA */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FEA_P_2) }, + { "vpminsw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FEB */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FEB_P_2) }, + { "vpor", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FEC */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FEC_P_2) }, + { "vpaddsb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FED */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FED_P_2) }, + { "vpaddsw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FEE */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FEE_P_2) }, + { "vpmaxsw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FEF */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FEF_P_2) }, + { "vpxor", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FF0 */ @@ -5466,42 +5445,42 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FF1_P_2) }, + { "vpsllw", { XM, Vex, EXxmm }, 0 }, }, /* PREFIX_VEX_0FF2 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FF2_P_2) }, + { "vpslld", { XM, Vex, EXxmm }, 0 }, }, /* PREFIX_VEX_0FF3 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FF3_P_2) }, + { "vpsllq", { XM, Vex, EXxmm }, 0 }, }, /* PREFIX_VEX_0FF4 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FF4_P_2) }, + { "vpmuludq", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FF5 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FF5_P_2) }, + { "vpmaddwd", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FF6 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FF6_P_2) }, + { "vpsadbw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FF7 */ @@ -5515,133 +5494,133 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FF8_P_2) }, + { "vpsubb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FF9 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FF9_P_2) }, + { "vpsubw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FFA */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FFA_P_2) }, + { "vpsubd", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FFB */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FFB_P_2) }, + { "vpsubq", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FFC */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FFC_P_2) }, + { "vpaddb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FFD */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FFD_P_2) }, + { "vpaddw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FFE */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FFE_P_2) }, + { "vpaddd", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3800 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3800_P_2) }, + { "vpshufb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3801 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3801_P_2) }, + { "vphaddw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3802 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3802_P_2) }, + { "vphaddd", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3803 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3803_P_2) }, + { "vphaddsw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3804 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3804_P_2) }, + { "vpmaddubsw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3805 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3805_P_2) }, + { "vphsubw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3806 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3806_P_2) }, + { "vphsubd", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3807 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3807_P_2) }, + { "vphsubsw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3808 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3808_P_2) }, + { "vpsignb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3809 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3809_P_2) }, + { "vpsignw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F380A */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F380A_P_2) }, + { "vpsignd", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F380B */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F380B_P_2) }, + { "vpmulhrsw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F380C */ @@ -5690,7 +5669,7 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3817_P_2) }, + { "vptest", { XM, EXx }, 0 }, }, /* PREFIX_VEX_0F3818 */ @@ -5718,77 +5697,77 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F381C_P_2) }, + { "vpabsb", { XM, EXx }, 0 }, }, /* PREFIX_VEX_0F381D */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F381D_P_2) }, + { "vpabsw", { XM, EXx }, 0 }, }, /* PREFIX_VEX_0F381E */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F381E_P_2) }, + { "vpabsd", { XM, EXx }, 0 }, }, /* PREFIX_VEX_0F3820 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3820_P_2) }, + { "vpmovsxbw", { XM, EXxmmq }, 0 }, }, /* PREFIX_VEX_0F3821 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3821_P_2) }, + { "vpmovsxbd", { XM, EXxmmqd }, 0 }, }, /* PREFIX_VEX_0F3822 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3822_P_2) }, + { "vpmovsxbq", { XM, EXxmmdw }, 0 }, }, /* PREFIX_VEX_0F3823 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3823_P_2) }, + { "vpmovsxwd", { XM, EXxmmq }, 0 }, }, /* PREFIX_VEX_0F3824 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3824_P_2) }, + { "vpmovsxwq", { XM, EXxmmqd }, 0 }, }, /* PREFIX_VEX_0F3825 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3825_P_2) }, + { "vpmovsxdq", { XM, EXxmmq }, 0 }, }, /* PREFIX_VEX_0F3828 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3828_P_2) }, + { "vpmuldq", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3829 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3829_P_2) }, + { "vpcmpeqq", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F382A */ @@ -5802,7 +5781,7 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F382B_P_2) }, + { "vpackusdw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F382C */ @@ -5837,42 +5816,42 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3830_P_2) }, + { "vpmovzxbw", { XM, EXxmmq }, 0 }, }, /* PREFIX_VEX_0F3831 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3831_P_2) }, + { "vpmovzxbd", { XM, EXxmmqd }, 0 }, }, /* PREFIX_VEX_0F3832 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3832_P_2) }, + { "vpmovzxbq", { XM, EXxmmdw }, 0 }, }, /* PREFIX_VEX_0F3833 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3833_P_2) }, + { "vpmovzxwd", { XM, EXxmmq }, 0 }, }, /* PREFIX_VEX_0F3834 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3834_P_2) }, + { "vpmovzxwq", { XM, EXxmmqd }, 0 }, }, /* PREFIX_VEX_0F3835 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3835_P_2) }, + { "vpmovzxdq", { XM, EXxmmq }, 0 }, }, /* PREFIX_VEX_0F3836 */ @@ -5886,70 +5865,70 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3837_P_2) }, + { "vpcmpgtq", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3838 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3838_P_2) }, + { "vpminsb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3839 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3839_P_2) }, + { "vpminsd", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F383A */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F383A_P_2) }, + { "vpminuw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F383B */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F383B_P_2) }, + { "vpminud", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F383C */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F383C_P_2) }, + { "vpmaxsb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F383D */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F383D_P_2) }, + { "vpmaxsd", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F383E */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F383E_P_2) }, + { "vpmaxuw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F383F */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F383F_P_2) }, + { "vpmaxud", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3840 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3840_P_2) }, + { "vpmulld", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3841 */ @@ -6268,6 +6247,13 @@ static const struct dis386 prefix_table[][4] = { { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, }, + /* PREFIX_VEX_0F38CF */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F38CF_P_2) }, + }, + /* PREFIX_VEX_0F38DB */ { { Bad_Opcode }, @@ -6279,28 +6265,28 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) }, + { "vaesenc", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F38DD */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) }, + { "vaesenclast", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F38DE */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) }, + { "vaesdec", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F38DF */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) }, + { "vaesdeclast", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F38F2 */ @@ -6393,56 +6379,56 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3A08_P_2) }, + { "vroundps", { XM, EXx, Ib }, 0 }, }, /* PREFIX_VEX_0F3A09 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3A09_P_2) }, + { "vroundpd", { XM, EXx, Ib }, 0 }, }, /* PREFIX_VEX_0F3A0A */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) }, + { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 }, }, /* PREFIX_VEX_0F3A0B */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) }, + { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 }, }, /* PREFIX_VEX_0F3A0C */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3A0C_P_2) }, + { "vblendps", { XM, Vex, EXx, Ib }, 0 }, }, /* PREFIX_VEX_0F3A0D */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3A0D_P_2) }, + { "vblendpd", { XM, Vex, EXx, Ib }, 0 }, }, /* PREFIX_VEX_0F3A0E */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3A0E_P_2) }, + { "vpblendw", { XM, Vex, EXx, Ib }, 0 }, }, /* PREFIX_VEX_0F3A0F */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3A0F_P_2) }, + { "vpalignr", { XM, Vex, EXx, Ib }, 0 }, }, /* PREFIX_VEX_0F3A14 */ @@ -6561,7 +6547,7 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3A40_P_2) }, + { "vdpps", { XM, Vex, EXx, Ib }, 0 }, }, /* PREFIX_VEX_0F3A41 */ @@ -6575,14 +6561,14 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3A42_P_2) }, + { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 }, }, /* PREFIX_VEX_0F3A44 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) }, + { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, 0 }, }, /* PREFIX_VEX_0F3A46 */ @@ -6631,28 +6617,28 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, }, /* PREFIX_VEX_0F3A5D */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, }, /* PREFIX_VEX_0F3A5E */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, }, /* PREFIX_VEX_0F3A5F */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, }, /* PREFIX_VEX_0F3A60 */ @@ -6688,14 +6674,14 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, }, /* PREFIX_VEX_0F3A69 */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, }, /* PREFIX_VEX_0F3A6A */ @@ -6716,14 +6702,14 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, }, /* PREFIX_VEX_0F3A6D */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, }, /* PREFIX_VEX_0F3A6E */ @@ -6744,14 +6730,14 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, }, /* PREFIX_VEX_0F3A79 */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, }, /* PREFIX_VEX_0F3A7A */ @@ -6772,7 +6758,7 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, { Bad_Opcode }, }, @@ -6780,7 +6766,7 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, }, /* PREFIX_VEX_0F3A7E */ @@ -6797,6 +6783,20 @@ static const struct dis386 prefix_table[][4] = { { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) }, }, + /* PREFIX_VEX_0F3ACE */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F3ACE_P_2) }, + }, + + /* PREFIX_VEX_0F3ACF */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F3ACF_P_2) }, + }, + /* PREFIX_VEX_0F3ADF */ { { Bad_Opcode }, @@ -6812,9 +6812,7 @@ static const struct dis386 prefix_table[][4] = { { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) }, }, -#define NEED_PREFIX_TABLE -#include "i386-dis-evex.h" -#undef NEED_PREFIX_TABLE +#include "i386-dis-evex-prefix.h" }; static const struct dis386 x86_64_table[][2] = { @@ -6828,7 +6826,7 @@ static const struct dis386 x86_64_table[][2] = { { "popP", { es }, 0 }, }, - /* X86_64_0D */ + /* X86_64_0E */ { { "pushP", { cs }, 0 }, }, @@ -6892,7 +6890,7 @@ static const struct dis386 x86_64_table[][2] = { /* X86_64_63 */ { { "arpl", { Ew, Gw }, 0 }, - { "movs{lq|xd}", { Gv, Ed }, 0 }, + { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 }, }, /* X86_64_6D */ @@ -6907,49 +6905,27 @@ static const struct dis386 x86_64_table[][2] = { { "outs{G|}", { indirDXr, Xz }, 0 }, }, - /* X86_64_82_REG_0 */ - { - { "addA", { Ebh1, Ib }, 0 }, - }, - - /* X86_64_82_REG_1 */ - { - { "orA", { Ebh1, Ib }, 0 }, - }, - - /* X86_64_82_REG_2 */ - { - { "adcA", { Ebh1, Ib }, 0 }, - }, - - /* X86_64_82_REG_3 */ - { - { "sbbA", { Ebh1, Ib }, 0 }, - }, - - /* X86_64_82_REG_4 */ - { - { "andA", { Ebh1, Ib }, 0 }, - }, - - /* X86_64_82_REG_5 */ + /* X86_64_82 */ { - { "subA", { Ebh1, Ib }, 0 }, + /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */ + { REG_TABLE (REG_80) }, }, - /* X86_64_82_REG_6 */ + /* X86_64_9A */ { - { "xorA", { Ebh1, Ib }, 0 }, + { "Jcall{T|}", { Ap }, 0 }, }, - /* X86_64_82_REG_7 */ + /* X86_64_C2 */ { - { "cmpA", { Eb, Ib }, 0 }, + { "retP", { Iw, BND }, 0 }, + { "ret@", { Iw, BND }, 0 }, }, - /* X86_64_9A */ + /* X86_64_C3 */ { - { "Jcall{T|}", { Ap }, 0 }, + { "retP", { BND }, 0 }, + { "ret@", { BND }, 0 }, }, /* X86_64_C4 */ @@ -7258,7 +7234,7 @@ static const struct dis386 three_byte_table[][256] = { { PREFIX_TABLE (PREFIX_0F38CC) }, { PREFIX_TABLE (PREFIX_0F38CD) }, { Bad_Opcode }, - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_0F38CF) }, /* d0 */ { Bad_Opcode }, { Bad_Opcode }, @@ -7301,12 +7277,12 @@ static const struct dis386 three_byte_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_0F38F5) }, { PREFIX_TABLE (PREFIX_0F38F6) }, { Bad_Opcode }, /* f8 */ - { Bad_Opcode }, - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_0F38F8) }, + { PREFIX_TABLE (PREFIX_0F38F9) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -7548,8 +7524,8 @@ static const struct dis386 three_byte_table[][256] = { { Bad_Opcode }, { PREFIX_TABLE (PREFIX_0F3ACC) }, { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_0F3ACE) }, + { PREFIX_TABLE (PREFIX_0F3ACF) }, /* d0 */ { Bad_Opcode }, { Bad_Opcode }, @@ -7605,8 +7581,10 @@ static const struct dis386 three_byte_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, }, +}; - /* THREE_BYTE_0F7A */ +static const struct dis386 xop_table[][256] = { + /* XOP_08 */ { /* 00 */ { Bad_Opcode }, @@ -7682,50 +7660,33 @@ static const struct dis386 three_byte_table[][256] = { { Bad_Opcode }, /* 40 */ { Bad_Opcode }, - { "phaddbw", { XM, EXq }, PREFIX_OPCODE }, - { "phaddbd", { XM, EXq }, PREFIX_OPCODE }, - { "phaddbq", { XM, EXq }, PREFIX_OPCODE }, { Bad_Opcode }, { Bad_Opcode }, - { "phaddwd", { XM, EXq }, PREFIX_OPCODE }, - { "phaddwq", { XM, EXq }, PREFIX_OPCODE }, - /* 48 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "phadddq", { XM, EXq }, PREFIX_OPCODE }, { Bad_Opcode }, { Bad_Opcode }, + /* 48 */ { Bad_Opcode }, { Bad_Opcode }, - /* 50 */ { Bad_Opcode }, - { "phaddubw", { XM, EXq }, PREFIX_OPCODE }, - { "phaddubd", { XM, EXq }, PREFIX_OPCODE }, - { "phaddubq", { XM, EXq }, PREFIX_OPCODE }, { Bad_Opcode }, { Bad_Opcode }, - { "phadduwd", { XM, EXq }, PREFIX_OPCODE }, - { "phadduwq", { XM, EXq }, PREFIX_OPCODE }, - /* 58 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "phaddudq", { XM, EXq }, PREFIX_OPCODE }, + /* 50 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* 60 */ { Bad_Opcode }, - { "phsubbw", { XM, EXq }, PREFIX_OPCODE }, - { "phsubbd", { XM, EXq }, PREFIX_OPCODE }, - { "phsubbq", { XM, EXq }, PREFIX_OPCODE }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* 58 */ { Bad_Opcode }, - /* 68 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -7733,8 +7694,8 @@ static const struct dis386 three_byte_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* 60 */ { Bad_Opcode }, - /* 70 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -7742,8 +7703,8 @@ static const struct dis386 three_byte_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* 68 */ { Bad_Opcode }, - /* 78 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -7751,8 +7712,8 @@ static const struct dis386 three_byte_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* 70 */ { Bad_Opcode }, - /* 80 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -7760,8 +7721,8 @@ static const struct dis386 three_byte_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* 78 */ { Bad_Opcode }, - /* 88 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -7769,33 +7730,50 @@ static const struct dis386 three_byte_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* 80 */ { Bad_Opcode }, - /* 90 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, + { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, + { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, + /* 88 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* 98 */ + { Bad_Opcode }, + { Bad_Opcode }, + { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, + { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, + /* 90 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, + { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, + { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, + /* 98 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* a0 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, + { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, + /* a0 */ { Bad_Opcode }, { Bad_Opcode }, + { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, + { "vpperm", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, { Bad_Opcode }, { Bad_Opcode }, + { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, { Bad_Opcode }, /* a8 */ { Bad_Opcode }, @@ -7813,7 +7791,7 @@ static const struct dis386 three_byte_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { Bad_Opcode }, + { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, { Bad_Opcode }, /* b8 */ { Bad_Opcode }, @@ -7825,10 +7803,10 @@ static const struct dis386 three_byte_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* c0 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { "vprotb", { XM, Vex_2src_1, Ib }, 0 }, + { "vprotw", { XM, Vex_2src_1, Ib }, 0 }, + { "vprotd", { XM, Vex_2src_1, Ib }, 0 }, + { "vprotq", { XM, Vex_2src_1, Ib }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -7838,10 +7816,10 @@ static const struct dis386 three_byte_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) }, + { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) }, + { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) }, + { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) }, /* d0 */ { Bad_Opcode }, { Bad_Opcode }, @@ -7874,10 +7852,10 @@ static const struct dis386 three_byte_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) }, + { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) }, + { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) }, + { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) }, /* f0 */ { Bad_Opcode }, { Bad_Opcode }, @@ -7897,15 +7875,12 @@ static const struct dis386 three_byte_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, }, -}; - -static const struct dis386 xop_table[][256] = { - /* XOP_08 */ + /* XOP_09 */ { /* 00 */ { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { REG_TABLE (REG_XOP_TBM_01) }, + { REG_TABLE (REG_XOP_TBM_02) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -7923,7 +7898,7 @@ static const struct dis386 xop_table[][256] = { /* 10 */ { Bad_Opcode }, { Bad_Opcode }, - { Bad_Opcode }, + { REG_TABLE (REG_XOP_LWPCB) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -8047,14 +8022,14 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* 80 */ + { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) }, + { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) }, + { "vfrczss", { XM, EXd }, 0 }, + { "vfrczsd", { XM, EXq }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { Bad_Opcode }, - { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, - { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, - { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, /* 88 */ { Bad_Opcode }, { Bad_Opcode }, @@ -8062,34 +8037,34 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, - { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, - /* 90 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, - { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, - { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + /* 90 */ + { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, + { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, + { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, + { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, + { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, + { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, + { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, + { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, /* 98 */ + { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, + { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, + { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, + { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* a0 */ + { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, - { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, - /* a0 */ { Bad_Opcode }, { Bad_Opcode }, - { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, - { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, { Bad_Opcode }, { Bad_Opcode }, - { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, { Bad_Opcode }, /* a8 */ { Bad_Opcode }, @@ -8107,7 +8082,7 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { Bad_Opcode }, { Bad_Opcode }, /* b8 */ { Bad_Opcode }, @@ -8119,59 +8094,59 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* c0 */ - { "vprotb", { XM, Vex_2src_1, Ib }, 0 }, - { "vprotw", { XM, Vex_2src_1, Ib }, 0 }, - { "vprotd", { XM, Vex_2src_1, Ib }, 0 }, - { "vprotq", { XM, Vex_2src_1, Ib }, 0 }, - { Bad_Opcode }, { Bad_Opcode }, + { "vphaddbw", { XM, EXxmm }, 0 }, + { "vphaddbd", { XM, EXxmm }, 0 }, + { "vphaddbq", { XM, EXxmm }, 0 }, { Bad_Opcode }, { Bad_Opcode }, + { "vphaddwd", { XM, EXxmm }, 0 }, + { "vphaddwq", { XM, EXxmm }, 0 }, /* c8 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) }, - { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) }, - { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) }, - { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) }, - /* d0 */ - { Bad_Opcode }, + { "vphadddq", { XM, EXxmm }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* d0 */ { Bad_Opcode }, + { "vphaddubw", { XM, EXxmm }, 0 }, + { "vphaddubd", { XM, EXxmm }, 0 }, + { "vphaddubq", { XM, EXxmm }, 0 }, { Bad_Opcode }, { Bad_Opcode }, + { "vphadduwd", { XM, EXxmm }, 0 }, + { "vphadduwq", { XM, EXxmm }, 0 }, /* d8 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { Bad_Opcode }, + { "vphaddudq", { XM, EXxmm }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, /* e0 */ { Bad_Opcode }, + { "vphsubbw", { XM, EXxmm }, 0 }, + { "vphsubwd", { XM, EXxmm }, 0 }, + { "vphsubdq", { XM, EXxmm }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* e8 */ + { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* e8 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) }, - { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) }, - { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) }, - { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) }, /* f0 */ { Bad_Opcode }, { Bad_Opcode }, @@ -8191,12 +8166,12 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, }, - /* XOP_09 */ + /* XOP_0A */ { /* 00 */ { Bad_Opcode }, - { REG_TABLE (REG_XOP_TBM_01) }, - { REG_TABLE (REG_XOP_TBM_02) }, + { Bad_Opcode }, + { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -8212,9 +8187,9 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* 10 */ + { "bextrS", { Gdq, Edq, Id }, 0 }, { Bad_Opcode }, - { Bad_Opcode }, - { REG_TABLE (REG_XOP_LWPCB) }, + { REG_TABLE (REG_XOP_LWP) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -8338,10 +8313,10 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* 80 */ - { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) }, - { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) }, - { "vfrczss", { XM, EXd }, 0 }, - { "vfrczsd", { XM, EXq }, 0 }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -8356,33 +8331,16 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* 90 */ - { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, - { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, - { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, - { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, - { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, - { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, - { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, - { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, - /* 98 */ - { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, - { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, - { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, - { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* a0 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* 98 */ { Bad_Opcode }, - /* a8 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -8390,8 +8348,8 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* a0 */ { Bad_Opcode }, - /* b0 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -8399,8 +8357,8 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* a8 */ { Bad_Opcode }, - /* b8 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -8408,110 +8366,88 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* b0 */ { Bad_Opcode }, - /* c0 */ { Bad_Opcode }, - { "vphaddbw", { XM, EXxmm }, 0 }, - { "vphaddbd", { XM, EXxmm }, 0 }, - { "vphaddbq", { XM, EXxmm }, 0 }, { Bad_Opcode }, { Bad_Opcode }, - { "vphaddwd", { XM, EXxmm }, 0 }, - { "vphaddwq", { XM, EXxmm }, 0 }, - /* c8 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "vphadddq", { XM, EXxmm }, 0 }, { Bad_Opcode }, + /* b8 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* d0 */ { Bad_Opcode }, - { "vphaddubw", { XM, EXxmm }, 0 }, - { "vphaddubd", { XM, EXxmm }, 0 }, - { "vphaddubq", { XM, EXxmm }, 0 }, { Bad_Opcode }, { Bad_Opcode }, - { "vphadduwd", { XM, EXxmm }, 0 }, - { "vphadduwq", { XM, EXxmm }, 0 }, - /* d8 */ { Bad_Opcode }, { Bad_Opcode }, + /* c0 */ { Bad_Opcode }, - { "vphaddudq", { XM, EXxmm }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* e0 */ { Bad_Opcode }, - { "vphsubbw", { XM, EXxmm }, 0 }, - { "vphsubwd", { XM, EXxmm }, 0 }, - { "vphsubdq", { XM, EXxmm }, 0 }, { Bad_Opcode }, { Bad_Opcode }, + /* c8 */ { Bad_Opcode }, { Bad_Opcode }, - /* e8 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* d0 */ { Bad_Opcode }, { Bad_Opcode }, - /* f0 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* d8 */ { Bad_Opcode }, { Bad_Opcode }, - /* f8 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* e0 */ { Bad_Opcode }, { Bad_Opcode }, - }, - /* XOP_0A */ - { - /* 00 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* e8 */ { Bad_Opcode }, { Bad_Opcode }, - /* 08 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* f0 */ { Bad_Opcode }, { Bad_Opcode }, - /* 10 */ - { "bextr", { Gv, Ev, Iq }, 0 }, { Bad_Opcode }, - { REG_TABLE (REG_XOP_LWP) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* 18 */ + /* f8 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -8520,7 +8456,13 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* 20 */ + }, +}; + +static const struct dis386 vex_table[][256] = { + /* VEX_0F */ + { + /* 00 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -8529,7 +8471,7 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* 28 */ + /* 08 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -8538,7 +8480,16 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* 30 */ + /* 10 */ + { PREFIX_TABLE (PREFIX_VEX_0F10) }, + { PREFIX_TABLE (PREFIX_VEX_0F11) }, + { PREFIX_TABLE (PREFIX_VEX_0F12) }, + { MOD_TABLE (MOD_VEX_0F13) }, + { "vunpcklpX", { XM, Vex, EXx }, 0 }, + { "vunpckhpX", { XM, Vex, EXx }, 0 }, + { PREFIX_TABLE (PREFIX_VEX_0F16) }, + { MOD_TABLE (MOD_VEX_0F17) }, + /* 18 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -8547,7 +8498,7 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* 38 */ + /* 20 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -8556,7 +8507,16 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* 40 */ + /* 28 */ + { "vmovapX", { XM, EXx }, 0 }, + { "vmovapX", { EXxS, XM }, 0 }, + { PREFIX_TABLE (PREFIX_VEX_0F2A) }, + { MOD_TABLE (MOD_VEX_0F2B) }, + { PREFIX_TABLE (PREFIX_VEX_0F2C) }, + { PREFIX_TABLE (PREFIX_VEX_0F2D) }, + { PREFIX_TABLE (PREFIX_VEX_0F2E) }, + { PREFIX_TABLE (PREFIX_VEX_0F2F) }, + /* 30 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -8565,7 +8525,7 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* 48 */ + /* 38 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -8574,60 +8534,78 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* 50 */ + /* 40 */ { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F41) }, + { PREFIX_TABLE (PREFIX_VEX_0F42) }, { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F44) }, + { PREFIX_TABLE (PREFIX_VEX_0F45) }, + { PREFIX_TABLE (PREFIX_VEX_0F46) }, + { PREFIX_TABLE (PREFIX_VEX_0F47) }, + /* 48 */ { Bad_Opcode }, { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F4A) }, + { PREFIX_TABLE (PREFIX_VEX_0F4B) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* 50 */ + { MOD_TABLE (MOD_VEX_0F50) }, + { PREFIX_TABLE (PREFIX_VEX_0F51) }, + { PREFIX_TABLE (PREFIX_VEX_0F52) }, + { PREFIX_TABLE (PREFIX_VEX_0F53) }, + { "vandpX", { XM, Vex, EXx }, 0 }, + { "vandnpX", { XM, Vex, EXx }, 0 }, + { "vorpX", { XM, Vex, EXx }, 0 }, + { "vxorpX", { XM, Vex, EXx }, 0 }, /* 58 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F58) }, + { PREFIX_TABLE (PREFIX_VEX_0F59) }, + { PREFIX_TABLE (PREFIX_VEX_0F5A) }, + { PREFIX_TABLE (PREFIX_VEX_0F5B) }, + { PREFIX_TABLE (PREFIX_VEX_0F5C) }, + { PREFIX_TABLE (PREFIX_VEX_0F5D) }, + { PREFIX_TABLE (PREFIX_VEX_0F5E) }, + { PREFIX_TABLE (PREFIX_VEX_0F5F) }, /* 60 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F60) }, + { PREFIX_TABLE (PREFIX_VEX_0F61) }, + { PREFIX_TABLE (PREFIX_VEX_0F62) }, + { PREFIX_TABLE (PREFIX_VEX_0F63) }, + { PREFIX_TABLE (PREFIX_VEX_0F64) }, + { PREFIX_TABLE (PREFIX_VEX_0F65) }, + { PREFIX_TABLE (PREFIX_VEX_0F66) }, + { PREFIX_TABLE (PREFIX_VEX_0F67) }, /* 68 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F68) }, + { PREFIX_TABLE (PREFIX_VEX_0F69) }, + { PREFIX_TABLE (PREFIX_VEX_0F6A) }, + { PREFIX_TABLE (PREFIX_VEX_0F6B) }, + { PREFIX_TABLE (PREFIX_VEX_0F6C) }, + { PREFIX_TABLE (PREFIX_VEX_0F6D) }, + { PREFIX_TABLE (PREFIX_VEX_0F6E) }, + { PREFIX_TABLE (PREFIX_VEX_0F6F) }, /* 70 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F70) }, + { REG_TABLE (REG_VEX_0F71) }, + { REG_TABLE (REG_VEX_0F72) }, + { REG_TABLE (REG_VEX_0F73) }, + { PREFIX_TABLE (PREFIX_VEX_0F74) }, + { PREFIX_TABLE (PREFIX_VEX_0F75) }, + { PREFIX_TABLE (PREFIX_VEX_0F76) }, + { PREFIX_TABLE (PREFIX_VEX_0F77) }, /* 78 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F7C) }, + { PREFIX_TABLE (PREFIX_VEX_0F7D) }, + { PREFIX_TABLE (PREFIX_VEX_0F7E) }, + { PREFIX_TABLE (PREFIX_VEX_0F7F) }, /* 80 */ { Bad_Opcode }, { Bad_Opcode }, @@ -8647,17 +8625,17 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* 90 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F90) }, + { PREFIX_TABLE (PREFIX_VEX_0F91) }, + { PREFIX_TABLE (PREFIX_VEX_0F92) }, + { PREFIX_TABLE (PREFIX_VEX_0F93) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, /* 98 */ - { Bad_Opcode }, - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F98) }, + { PREFIX_TABLE (PREFIX_VEX_0F99) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -8680,7 +8658,7 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { Bad_Opcode }, + { REG_TABLE (REG_VEX_0FAE) }, { Bad_Opcode }, /* b0 */ { Bad_Opcode }, @@ -8703,11 +8681,11 @@ static const struct dis386 xop_table[][256] = { /* c0 */ { Bad_Opcode }, { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0FC2) }, { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0FC4) }, + { PREFIX_TABLE (PREFIX_VEX_0FC5) }, + { "vshufpX", { XM, Vex, EXx, Ib }, 0 }, { Bad_Opcode }, /* c8 */ { Bad_Opcode }, @@ -8719,121 +8697,171 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* d0 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0FD0) }, + { PREFIX_TABLE (PREFIX_VEX_0FD1) }, + { PREFIX_TABLE (PREFIX_VEX_0FD2) }, + { PREFIX_TABLE (PREFIX_VEX_0FD3) }, + { PREFIX_TABLE (PREFIX_VEX_0FD4) }, + { PREFIX_TABLE (PREFIX_VEX_0FD5) }, + { PREFIX_TABLE (PREFIX_VEX_0FD6) }, + { PREFIX_TABLE (PREFIX_VEX_0FD7) }, /* d8 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0FD8) }, + { PREFIX_TABLE (PREFIX_VEX_0FD9) }, + { PREFIX_TABLE (PREFIX_VEX_0FDA) }, + { PREFIX_TABLE (PREFIX_VEX_0FDB) }, + { PREFIX_TABLE (PREFIX_VEX_0FDC) }, + { PREFIX_TABLE (PREFIX_VEX_0FDD) }, + { PREFIX_TABLE (PREFIX_VEX_0FDE) }, + { PREFIX_TABLE (PREFIX_VEX_0FDF) }, /* e0 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* e8 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0FE0) }, + { PREFIX_TABLE (PREFIX_VEX_0FE1) }, + { PREFIX_TABLE (PREFIX_VEX_0FE2) }, + { PREFIX_TABLE (PREFIX_VEX_0FE3) }, + { PREFIX_TABLE (PREFIX_VEX_0FE4) }, + { PREFIX_TABLE (PREFIX_VEX_0FE5) }, + { PREFIX_TABLE (PREFIX_VEX_0FE6) }, + { PREFIX_TABLE (PREFIX_VEX_0FE7) }, + /* e8 */ + { PREFIX_TABLE (PREFIX_VEX_0FE8) }, + { PREFIX_TABLE (PREFIX_VEX_0FE9) }, + { PREFIX_TABLE (PREFIX_VEX_0FEA) }, + { PREFIX_TABLE (PREFIX_VEX_0FEB) }, + { PREFIX_TABLE (PREFIX_VEX_0FEC) }, + { PREFIX_TABLE (PREFIX_VEX_0FED) }, + { PREFIX_TABLE (PREFIX_VEX_0FEE) }, + { PREFIX_TABLE (PREFIX_VEX_0FEF) }, /* f0 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0FF0) }, + { PREFIX_TABLE (PREFIX_VEX_0FF1) }, + { PREFIX_TABLE (PREFIX_VEX_0FF2) }, + { PREFIX_TABLE (PREFIX_VEX_0FF3) }, + { PREFIX_TABLE (PREFIX_VEX_0FF4) }, + { PREFIX_TABLE (PREFIX_VEX_0FF5) }, + { PREFIX_TABLE (PREFIX_VEX_0FF6) }, + { PREFIX_TABLE (PREFIX_VEX_0FF7) }, /* f8 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0FF8) }, + { PREFIX_TABLE (PREFIX_VEX_0FF9) }, + { PREFIX_TABLE (PREFIX_VEX_0FFA) }, + { PREFIX_TABLE (PREFIX_VEX_0FFB) }, + { PREFIX_TABLE (PREFIX_VEX_0FFC) }, + { PREFIX_TABLE (PREFIX_VEX_0FFD) }, + { PREFIX_TABLE (PREFIX_VEX_0FFE) }, { Bad_Opcode }, }, -}; - -static const struct dis386 vex_table[][256] = { - /* VEX_0F */ + /* VEX_0F38 */ { /* 00 */ + { PREFIX_TABLE (PREFIX_VEX_0F3800) }, + { PREFIX_TABLE (PREFIX_VEX_0F3801) }, + { PREFIX_TABLE (PREFIX_VEX_0F3802) }, + { PREFIX_TABLE (PREFIX_VEX_0F3803) }, + { PREFIX_TABLE (PREFIX_VEX_0F3804) }, + { PREFIX_TABLE (PREFIX_VEX_0F3805) }, + { PREFIX_TABLE (PREFIX_VEX_0F3806) }, + { PREFIX_TABLE (PREFIX_VEX_0F3807) }, + /* 08 */ + { PREFIX_TABLE (PREFIX_VEX_0F3808) }, + { PREFIX_TABLE (PREFIX_VEX_0F3809) }, + { PREFIX_TABLE (PREFIX_VEX_0F380A) }, + { PREFIX_TABLE (PREFIX_VEX_0F380B) }, + { PREFIX_TABLE (PREFIX_VEX_0F380C) }, + { PREFIX_TABLE (PREFIX_VEX_0F380D) }, + { PREFIX_TABLE (PREFIX_VEX_0F380E) }, + { PREFIX_TABLE (PREFIX_VEX_0F380F) }, + /* 10 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F3813) }, { Bad_Opcode }, { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F3816) }, + { PREFIX_TABLE (PREFIX_VEX_0F3817) }, + /* 18 */ + { PREFIX_TABLE (PREFIX_VEX_0F3818) }, + { PREFIX_TABLE (PREFIX_VEX_0F3819) }, + { PREFIX_TABLE (PREFIX_VEX_0F381A) }, { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F381C) }, + { PREFIX_TABLE (PREFIX_VEX_0F381D) }, + { PREFIX_TABLE (PREFIX_VEX_0F381E) }, { Bad_Opcode }, + /* 20 */ + { PREFIX_TABLE (PREFIX_VEX_0F3820) }, + { PREFIX_TABLE (PREFIX_VEX_0F3821) }, + { PREFIX_TABLE (PREFIX_VEX_0F3822) }, + { PREFIX_TABLE (PREFIX_VEX_0F3823) }, + { PREFIX_TABLE (PREFIX_VEX_0F3824) }, + { PREFIX_TABLE (PREFIX_VEX_0F3825) }, { Bad_Opcode }, - /* 08 */ { Bad_Opcode }, + /* 28 */ + { PREFIX_TABLE (PREFIX_VEX_0F3828) }, + { PREFIX_TABLE (PREFIX_VEX_0F3829) }, + { PREFIX_TABLE (PREFIX_VEX_0F382A) }, + { PREFIX_TABLE (PREFIX_VEX_0F382B) }, + { PREFIX_TABLE (PREFIX_VEX_0F382C) }, + { PREFIX_TABLE (PREFIX_VEX_0F382D) }, + { PREFIX_TABLE (PREFIX_VEX_0F382E) }, + { PREFIX_TABLE (PREFIX_VEX_0F382F) }, + /* 30 */ + { PREFIX_TABLE (PREFIX_VEX_0F3830) }, + { PREFIX_TABLE (PREFIX_VEX_0F3831) }, + { PREFIX_TABLE (PREFIX_VEX_0F3832) }, + { PREFIX_TABLE (PREFIX_VEX_0F3833) }, + { PREFIX_TABLE (PREFIX_VEX_0F3834) }, + { PREFIX_TABLE (PREFIX_VEX_0F3835) }, + { PREFIX_TABLE (PREFIX_VEX_0F3836) }, + { PREFIX_TABLE (PREFIX_VEX_0F3837) }, + /* 38 */ + { PREFIX_TABLE (PREFIX_VEX_0F3838) }, + { PREFIX_TABLE (PREFIX_VEX_0F3839) }, + { PREFIX_TABLE (PREFIX_VEX_0F383A) }, + { PREFIX_TABLE (PREFIX_VEX_0F383B) }, + { PREFIX_TABLE (PREFIX_VEX_0F383C) }, + { PREFIX_TABLE (PREFIX_VEX_0F383D) }, + { PREFIX_TABLE (PREFIX_VEX_0F383E) }, + { PREFIX_TABLE (PREFIX_VEX_0F383F) }, + /* 40 */ + { PREFIX_TABLE (PREFIX_VEX_0F3840) }, + { PREFIX_TABLE (PREFIX_VEX_0F3841) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F3845) }, + { PREFIX_TABLE (PREFIX_VEX_0F3846) }, + { PREFIX_TABLE (PREFIX_VEX_0F3847) }, + /* 48 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* 10 */ - { PREFIX_TABLE (PREFIX_VEX_0F10) }, - { PREFIX_TABLE (PREFIX_VEX_0F11) }, - { PREFIX_TABLE (PREFIX_VEX_0F12) }, - { MOD_TABLE (MOD_VEX_0F13) }, - { VEX_W_TABLE (VEX_W_0F14) }, - { VEX_W_TABLE (VEX_W_0F15) }, - { PREFIX_TABLE (PREFIX_VEX_0F16) }, - { MOD_TABLE (MOD_VEX_0F17) }, - /* 18 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* 50 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* 20 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* 58 */ + { PREFIX_TABLE (PREFIX_VEX_0F3858) }, + { PREFIX_TABLE (PREFIX_VEX_0F3859) }, + { PREFIX_TABLE (PREFIX_VEX_0F385A) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* 28 */ - { VEX_W_TABLE (VEX_W_0F28) }, - { VEX_W_TABLE (VEX_W_0F29) }, - { PREFIX_TABLE (PREFIX_VEX_0F2A) }, - { MOD_TABLE (MOD_VEX_0F2B) }, - { PREFIX_TABLE (PREFIX_VEX_0F2C) }, - { PREFIX_TABLE (PREFIX_VEX_0F2D) }, - { PREFIX_TABLE (PREFIX_VEX_0F2E) }, - { PREFIX_TABLE (PREFIX_VEX_0F2F) }, - /* 30 */ { Bad_Opcode }, + /* 60 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -8841,8 +8869,8 @@ static const struct dis386 vex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* 38 */ { Bad_Opcode }, + /* 68 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -8850,143 +8878,116 @@ static const struct dis386 vex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* 40 */ { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_VEX_0F41) }, - { PREFIX_TABLE (PREFIX_VEX_0F42) }, + /* 70 */ + { Bad_Opcode }, { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_VEX_0F44) }, - { PREFIX_TABLE (PREFIX_VEX_0F45) }, - { PREFIX_TABLE (PREFIX_VEX_0F46) }, - { PREFIX_TABLE (PREFIX_VEX_0F47) }, - /* 48 */ { Bad_Opcode }, { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_VEX_0F4A) }, - { PREFIX_TABLE (PREFIX_VEX_0F4B) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* 50 */ - { MOD_TABLE (MOD_VEX_0F50) }, - { PREFIX_TABLE (PREFIX_VEX_0F51) }, - { PREFIX_TABLE (PREFIX_VEX_0F52) }, - { PREFIX_TABLE (PREFIX_VEX_0F53) }, - { "vandpX", { XM, Vex, EXx }, 0 }, - { "vandnpX", { XM, Vex, EXx }, 0 }, - { "vorpX", { XM, Vex, EXx }, 0 }, - { "vxorpX", { XM, Vex, EXx }, 0 }, - /* 58 */ - { PREFIX_TABLE (PREFIX_VEX_0F58) }, - { PREFIX_TABLE (PREFIX_VEX_0F59) }, - { PREFIX_TABLE (PREFIX_VEX_0F5A) }, - { PREFIX_TABLE (PREFIX_VEX_0F5B) }, - { PREFIX_TABLE (PREFIX_VEX_0F5C) }, - { PREFIX_TABLE (PREFIX_VEX_0F5D) }, - { PREFIX_TABLE (PREFIX_VEX_0F5E) }, - { PREFIX_TABLE (PREFIX_VEX_0F5F) }, - /* 60 */ - { PREFIX_TABLE (PREFIX_VEX_0F60) }, - { PREFIX_TABLE (PREFIX_VEX_0F61) }, - { PREFIX_TABLE (PREFIX_VEX_0F62) }, - { PREFIX_TABLE (PREFIX_VEX_0F63) }, - { PREFIX_TABLE (PREFIX_VEX_0F64) }, - { PREFIX_TABLE (PREFIX_VEX_0F65) }, - { PREFIX_TABLE (PREFIX_VEX_0F66) }, - { PREFIX_TABLE (PREFIX_VEX_0F67) }, - /* 68 */ - { PREFIX_TABLE (PREFIX_VEX_0F68) }, - { PREFIX_TABLE (PREFIX_VEX_0F69) }, - { PREFIX_TABLE (PREFIX_VEX_0F6A) }, - { PREFIX_TABLE (PREFIX_VEX_0F6B) }, - { PREFIX_TABLE (PREFIX_VEX_0F6C) }, - { PREFIX_TABLE (PREFIX_VEX_0F6D) }, - { PREFIX_TABLE (PREFIX_VEX_0F6E) }, - { PREFIX_TABLE (PREFIX_VEX_0F6F) }, - /* 70 */ - { PREFIX_TABLE (PREFIX_VEX_0F70) }, - { REG_TABLE (REG_VEX_0F71) }, - { REG_TABLE (REG_VEX_0F72) }, - { REG_TABLE (REG_VEX_0F73) }, - { PREFIX_TABLE (PREFIX_VEX_0F74) }, - { PREFIX_TABLE (PREFIX_VEX_0F75) }, - { PREFIX_TABLE (PREFIX_VEX_0F76) }, - { PREFIX_TABLE (PREFIX_VEX_0F77) }, /* 78 */ + { PREFIX_TABLE (PREFIX_VEX_0F3878) }, + { PREFIX_TABLE (PREFIX_VEX_0F3879) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_VEX_0F7C) }, - { PREFIX_TABLE (PREFIX_VEX_0F7D) }, - { PREFIX_TABLE (PREFIX_VEX_0F7E) }, - { PREFIX_TABLE (PREFIX_VEX_0F7F) }, - /* 80 */ { Bad_Opcode }, { Bad_Opcode }, + /* 80 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* 88 */ { Bad_Opcode }, { Bad_Opcode }, + /* 88 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F388C) }, { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F388E) }, { Bad_Opcode }, /* 90 */ - { PREFIX_TABLE (PREFIX_VEX_0F90) }, - { PREFIX_TABLE (PREFIX_VEX_0F91) }, - { PREFIX_TABLE (PREFIX_VEX_0F92) }, - { PREFIX_TABLE (PREFIX_VEX_0F93) }, - { Bad_Opcode }, - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F3890) }, + { PREFIX_TABLE (PREFIX_VEX_0F3891) }, + { PREFIX_TABLE (PREFIX_VEX_0F3892) }, + { PREFIX_TABLE (PREFIX_VEX_0F3893) }, { Bad_Opcode }, { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F3896) }, + { PREFIX_TABLE (PREFIX_VEX_0F3897) }, /* 98 */ - { PREFIX_TABLE (PREFIX_VEX_0F98) }, - { PREFIX_TABLE (PREFIX_VEX_0F99) }, - { Bad_Opcode }, - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F3898) }, + { PREFIX_TABLE (PREFIX_VEX_0F3899) }, + { PREFIX_TABLE (PREFIX_VEX_0F389A) }, + { PREFIX_TABLE (PREFIX_VEX_0F389B) }, + { PREFIX_TABLE (PREFIX_VEX_0F389C) }, + { PREFIX_TABLE (PREFIX_VEX_0F389D) }, + { PREFIX_TABLE (PREFIX_VEX_0F389E) }, + { PREFIX_TABLE (PREFIX_VEX_0F389F) }, + /* a0 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* a0 */ { Bad_Opcode }, { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F38A6) }, + { PREFIX_TABLE (PREFIX_VEX_0F38A7) }, + /* a8 */ + { PREFIX_TABLE (PREFIX_VEX_0F38A8) }, + { PREFIX_TABLE (PREFIX_VEX_0F38A9) }, + { PREFIX_TABLE (PREFIX_VEX_0F38AA) }, + { PREFIX_TABLE (PREFIX_VEX_0F38AB) }, + { PREFIX_TABLE (PREFIX_VEX_0F38AC) }, + { PREFIX_TABLE (PREFIX_VEX_0F38AD) }, + { PREFIX_TABLE (PREFIX_VEX_0F38AE) }, + { PREFIX_TABLE (PREFIX_VEX_0F38AF) }, + /* b0 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* a8 */ - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F38B6) }, + { PREFIX_TABLE (PREFIX_VEX_0F38B7) }, + /* b8 */ + { PREFIX_TABLE (PREFIX_VEX_0F38B8) }, + { PREFIX_TABLE (PREFIX_VEX_0F38B9) }, + { PREFIX_TABLE (PREFIX_VEX_0F38BA) }, + { PREFIX_TABLE (PREFIX_VEX_0F38BB) }, + { PREFIX_TABLE (PREFIX_VEX_0F38BC) }, + { PREFIX_TABLE (PREFIX_VEX_0F38BD) }, + { PREFIX_TABLE (PREFIX_VEX_0F38BE) }, + { PREFIX_TABLE (PREFIX_VEX_0F38BF) }, + /* c0 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { REG_TABLE (REG_VEX_0FAE) }, { Bad_Opcode }, - /* b0 */ { Bad_Opcode }, { Bad_Opcode }, + /* c8 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* b8 */ { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F38CF) }, + /* d0 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -8994,16 +8995,17 @@ static const struct dis386 vex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* c0 */ { Bad_Opcode }, + /* d8 */ { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_VEX_0FC2) }, { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_VEX_0FC4) }, - { PREFIX_TABLE (PREFIX_VEX_0FC5) }, - { "vshufpX", { XM, Vex, EXx, Ib }, 0 }, { Bad_Opcode }, - /* c8 */ + { PREFIX_TABLE (PREFIX_VEX_0F38DB) }, + { PREFIX_TABLE (PREFIX_VEX_0F38DC) }, + { PREFIX_TABLE (PREFIX_VEX_0F38DD) }, + { PREFIX_TABLE (PREFIX_VEX_0F38DE) }, + { PREFIX_TABLE (PREFIX_VEX_0F38DF) }, + /* e0 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -9012,173 +9014,82 @@ static const struct dis386 vex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* d0 */ - { PREFIX_TABLE (PREFIX_VEX_0FD0) }, - { PREFIX_TABLE (PREFIX_VEX_0FD1) }, - { PREFIX_TABLE (PREFIX_VEX_0FD2) }, - { PREFIX_TABLE (PREFIX_VEX_0FD3) }, - { PREFIX_TABLE (PREFIX_VEX_0FD4) }, - { PREFIX_TABLE (PREFIX_VEX_0FD5) }, - { PREFIX_TABLE (PREFIX_VEX_0FD6) }, - { PREFIX_TABLE (PREFIX_VEX_0FD7) }, - /* d8 */ - { PREFIX_TABLE (PREFIX_VEX_0FD8) }, - { PREFIX_TABLE (PREFIX_VEX_0FD9) }, - { PREFIX_TABLE (PREFIX_VEX_0FDA) }, - { PREFIX_TABLE (PREFIX_VEX_0FDB) }, - { PREFIX_TABLE (PREFIX_VEX_0FDC) }, - { PREFIX_TABLE (PREFIX_VEX_0FDD) }, - { PREFIX_TABLE (PREFIX_VEX_0FDE) }, - { PREFIX_TABLE (PREFIX_VEX_0FDF) }, - /* e0 */ - { PREFIX_TABLE (PREFIX_VEX_0FE0) }, - { PREFIX_TABLE (PREFIX_VEX_0FE1) }, - { PREFIX_TABLE (PREFIX_VEX_0FE2) }, - { PREFIX_TABLE (PREFIX_VEX_0FE3) }, - { PREFIX_TABLE (PREFIX_VEX_0FE4) }, - { PREFIX_TABLE (PREFIX_VEX_0FE5) }, - { PREFIX_TABLE (PREFIX_VEX_0FE6) }, - { PREFIX_TABLE (PREFIX_VEX_0FE7) }, /* e8 */ - { PREFIX_TABLE (PREFIX_VEX_0FE8) }, - { PREFIX_TABLE (PREFIX_VEX_0FE9) }, - { PREFIX_TABLE (PREFIX_VEX_0FEA) }, - { PREFIX_TABLE (PREFIX_VEX_0FEB) }, - { PREFIX_TABLE (PREFIX_VEX_0FEC) }, - { PREFIX_TABLE (PREFIX_VEX_0FED) }, - { PREFIX_TABLE (PREFIX_VEX_0FEE) }, - { PREFIX_TABLE (PREFIX_VEX_0FEF) }, - /* f0 */ - { PREFIX_TABLE (PREFIX_VEX_0FF0) }, - { PREFIX_TABLE (PREFIX_VEX_0FF1) }, - { PREFIX_TABLE (PREFIX_VEX_0FF2) }, - { PREFIX_TABLE (PREFIX_VEX_0FF3) }, - { PREFIX_TABLE (PREFIX_VEX_0FF4) }, - { PREFIX_TABLE (PREFIX_VEX_0FF5) }, - { PREFIX_TABLE (PREFIX_VEX_0FF6) }, - { PREFIX_TABLE (PREFIX_VEX_0FF7) }, - /* f8 */ - { PREFIX_TABLE (PREFIX_VEX_0FF8) }, - { PREFIX_TABLE (PREFIX_VEX_0FF9) }, - { PREFIX_TABLE (PREFIX_VEX_0FFA) }, - { PREFIX_TABLE (PREFIX_VEX_0FFB) }, - { PREFIX_TABLE (PREFIX_VEX_0FFC) }, - { PREFIX_TABLE (PREFIX_VEX_0FFD) }, - { PREFIX_TABLE (PREFIX_VEX_0FFE) }, { Bad_Opcode }, - }, - /* VEX_0F38 */ - { - /* 00 */ - { PREFIX_TABLE (PREFIX_VEX_0F3800) }, - { PREFIX_TABLE (PREFIX_VEX_0F3801) }, - { PREFIX_TABLE (PREFIX_VEX_0F3802) }, - { PREFIX_TABLE (PREFIX_VEX_0F3803) }, - { PREFIX_TABLE (PREFIX_VEX_0F3804) }, - { PREFIX_TABLE (PREFIX_VEX_0F3805) }, - { PREFIX_TABLE (PREFIX_VEX_0F3806) }, - { PREFIX_TABLE (PREFIX_VEX_0F3807) }, - /* 08 */ - { PREFIX_TABLE (PREFIX_VEX_0F3808) }, - { PREFIX_TABLE (PREFIX_VEX_0F3809) }, - { PREFIX_TABLE (PREFIX_VEX_0F380A) }, - { PREFIX_TABLE (PREFIX_VEX_0F380B) }, - { PREFIX_TABLE (PREFIX_VEX_0F380C) }, - { PREFIX_TABLE (PREFIX_VEX_0F380D) }, - { PREFIX_TABLE (PREFIX_VEX_0F380E) }, - { PREFIX_TABLE (PREFIX_VEX_0F380F) }, - /* 10 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_VEX_0F3813) }, { Bad_Opcode }, { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_VEX_0F3816) }, - { PREFIX_TABLE (PREFIX_VEX_0F3817) }, - /* 18 */ - { PREFIX_TABLE (PREFIX_VEX_0F3818) }, - { PREFIX_TABLE (PREFIX_VEX_0F3819) }, - { PREFIX_TABLE (PREFIX_VEX_0F381A) }, { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_VEX_0F381C) }, - { PREFIX_TABLE (PREFIX_VEX_0F381D) }, - { PREFIX_TABLE (PREFIX_VEX_0F381E) }, { Bad_Opcode }, - /* 20 */ - { PREFIX_TABLE (PREFIX_VEX_0F3820) }, - { PREFIX_TABLE (PREFIX_VEX_0F3821) }, - { PREFIX_TABLE (PREFIX_VEX_0F3822) }, - { PREFIX_TABLE (PREFIX_VEX_0F3823) }, - { PREFIX_TABLE (PREFIX_VEX_0F3824) }, - { PREFIX_TABLE (PREFIX_VEX_0F3825) }, + /* f0 */ { Bad_Opcode }, { Bad_Opcode }, - /* 28 */ - { PREFIX_TABLE (PREFIX_VEX_0F3828) }, - { PREFIX_TABLE (PREFIX_VEX_0F3829) }, - { PREFIX_TABLE (PREFIX_VEX_0F382A) }, - { PREFIX_TABLE (PREFIX_VEX_0F382B) }, - { PREFIX_TABLE (PREFIX_VEX_0F382C) }, - { PREFIX_TABLE (PREFIX_VEX_0F382D) }, - { PREFIX_TABLE (PREFIX_VEX_0F382E) }, - { PREFIX_TABLE (PREFIX_VEX_0F382F) }, - /* 30 */ - { PREFIX_TABLE (PREFIX_VEX_0F3830) }, - { PREFIX_TABLE (PREFIX_VEX_0F3831) }, - { PREFIX_TABLE (PREFIX_VEX_0F3832) }, - { PREFIX_TABLE (PREFIX_VEX_0F3833) }, - { PREFIX_TABLE (PREFIX_VEX_0F3834) }, - { PREFIX_TABLE (PREFIX_VEX_0F3835) }, - { PREFIX_TABLE (PREFIX_VEX_0F3836) }, - { PREFIX_TABLE (PREFIX_VEX_0F3837) }, - /* 38 */ - { PREFIX_TABLE (PREFIX_VEX_0F3838) }, - { PREFIX_TABLE (PREFIX_VEX_0F3839) }, - { PREFIX_TABLE (PREFIX_VEX_0F383A) }, - { PREFIX_TABLE (PREFIX_VEX_0F383B) }, - { PREFIX_TABLE (PREFIX_VEX_0F383C) }, - { PREFIX_TABLE (PREFIX_VEX_0F383D) }, - { PREFIX_TABLE (PREFIX_VEX_0F383E) }, - { PREFIX_TABLE (PREFIX_VEX_0F383F) }, - /* 40 */ - { PREFIX_TABLE (PREFIX_VEX_0F3840) }, - { PREFIX_TABLE (PREFIX_VEX_0F3841) }, + { PREFIX_TABLE (PREFIX_VEX_0F38F2) }, + { REG_TABLE (REG_VEX_0F38F3) }, { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F38F5) }, + { PREFIX_TABLE (PREFIX_VEX_0F38F6) }, + { PREFIX_TABLE (PREFIX_VEX_0F38F7) }, + /* f8 */ { Bad_Opcode }, { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_VEX_0F3845) }, - { PREFIX_TABLE (PREFIX_VEX_0F3846) }, - { PREFIX_TABLE (PREFIX_VEX_0F3847) }, - /* 48 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + }, + /* VEX_0F3A */ + { + /* 00 */ + { PREFIX_TABLE (PREFIX_VEX_0F3A00) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A01) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A02) }, { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F3A04) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A05) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A06) }, { Bad_Opcode }, - /* 50 */ + /* 08 */ + { PREFIX_TABLE (PREFIX_VEX_0F3A08) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A09) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A0A) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A0B) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A0C) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A0D) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A0E) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A0F) }, + /* 10 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F3A14) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A15) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A16) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A17) }, + /* 18 */ + { PREFIX_TABLE (PREFIX_VEX_0F3A18) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A19) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F3A1D) }, { Bad_Opcode }, - /* 58 */ - { PREFIX_TABLE (PREFIX_VEX_0F3858) }, - { PREFIX_TABLE (PREFIX_VEX_0F3859) }, - { PREFIX_TABLE (PREFIX_VEX_0F385A) }, { Bad_Opcode }, + /* 20 */ + { PREFIX_TABLE (PREFIX_VEX_0F3A20) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A21) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A22) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* 60 */ { Bad_Opcode }, + /* 28 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -9186,107 +9097,107 @@ static const struct dis386 vex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* 68 */ { Bad_Opcode }, + /* 30 */ + { PREFIX_TABLE (PREFIX_VEX_0F3A30) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A31) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A32) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A33) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* 38 */ + { PREFIX_TABLE (PREFIX_VEX_0F3A38) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A39) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* 70 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* 40 */ + { PREFIX_TABLE (PREFIX_VEX_0F3A40) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A41) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A42) }, { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F3A44) }, { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F3A46) }, { Bad_Opcode }, + /* 48 */ + { PREFIX_TABLE (PREFIX_VEX_0F3A48) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A49) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A4A) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A4B) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A4C) }, { Bad_Opcode }, { Bad_Opcode }, - /* 78 */ - { PREFIX_TABLE (PREFIX_VEX_0F3878) }, - { PREFIX_TABLE (PREFIX_VEX_0F3879) }, { Bad_Opcode }, + /* 50 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* 80 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* 58 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F3A5C) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A5D) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A5E) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A5F) }, + /* 60 */ + { PREFIX_TABLE (PREFIX_VEX_0F3A60) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A61) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A62) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A63) }, { Bad_Opcode }, - /* 88 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* 68 */ + { PREFIX_TABLE (PREFIX_VEX_0F3A68) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A69) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A6A) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A6B) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A6C) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A6D) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A6E) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A6F) }, + /* 70 */ { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_VEX_0F388C) }, { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_VEX_0F388E) }, { Bad_Opcode }, - /* 90 */ - { PREFIX_TABLE (PREFIX_VEX_0F3890) }, - { PREFIX_TABLE (PREFIX_VEX_0F3891) }, - { PREFIX_TABLE (PREFIX_VEX_0F3892) }, - { PREFIX_TABLE (PREFIX_VEX_0F3893) }, - { Bad_Opcode }, - { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_VEX_0F3896) }, - { PREFIX_TABLE (PREFIX_VEX_0F3897) }, - /* 98 */ - { PREFIX_TABLE (PREFIX_VEX_0F3898) }, - { PREFIX_TABLE (PREFIX_VEX_0F3899) }, - { PREFIX_TABLE (PREFIX_VEX_0F389A) }, - { PREFIX_TABLE (PREFIX_VEX_0F389B) }, - { PREFIX_TABLE (PREFIX_VEX_0F389C) }, - { PREFIX_TABLE (PREFIX_VEX_0F389D) }, - { PREFIX_TABLE (PREFIX_VEX_0F389E) }, - { PREFIX_TABLE (PREFIX_VEX_0F389F) }, - /* a0 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* 78 */ + { PREFIX_TABLE (PREFIX_VEX_0F3A78) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A79) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A7A) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A7B) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A7C) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A7D) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A7E) }, + { PREFIX_TABLE (PREFIX_VEX_0F3A7F) }, + /* 80 */ { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_VEX_0F38A6) }, - { PREFIX_TABLE (PREFIX_VEX_0F38A7) }, - /* a8 */ - { PREFIX_TABLE (PREFIX_VEX_0F38A8) }, - { PREFIX_TABLE (PREFIX_VEX_0F38A9) }, - { PREFIX_TABLE (PREFIX_VEX_0F38AA) }, - { PREFIX_TABLE (PREFIX_VEX_0F38AB) }, - { PREFIX_TABLE (PREFIX_VEX_0F38AC) }, - { PREFIX_TABLE (PREFIX_VEX_0F38AD) }, - { PREFIX_TABLE (PREFIX_VEX_0F38AE) }, - { PREFIX_TABLE (PREFIX_VEX_0F38AF) }, - /* b0 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_VEX_0F38B6) }, - { PREFIX_TABLE (PREFIX_VEX_0F38B7) }, - /* b8 */ - { PREFIX_TABLE (PREFIX_VEX_0F38B8) }, - { PREFIX_TABLE (PREFIX_VEX_0F38B9) }, - { PREFIX_TABLE (PREFIX_VEX_0F38BA) }, - { PREFIX_TABLE (PREFIX_VEX_0F38BB) }, - { PREFIX_TABLE (PREFIX_VEX_0F38BC) }, - { PREFIX_TABLE (PREFIX_VEX_0F38BD) }, - { PREFIX_TABLE (PREFIX_VEX_0F38BE) }, - { PREFIX_TABLE (PREFIX_VEX_0F38BF) }, - /* c0 */ { Bad_Opcode }, + /* 88 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -9294,8 +9205,8 @@ static const struct dis386 vex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* c8 */ { Bad_Opcode }, + /* 90 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -9303,8 +9214,8 @@ static const struct dis386 vex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* d0 */ { Bad_Opcode }, + /* 98 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -9312,101 +9223,62 @@ static const struct dis386 vex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* d8 */ { Bad_Opcode }, + /* a0 */ { Bad_Opcode }, { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_VEX_0F38DB) }, - { PREFIX_TABLE (PREFIX_VEX_0F38DC) }, - { PREFIX_TABLE (PREFIX_VEX_0F38DD) }, - { PREFIX_TABLE (PREFIX_VEX_0F38DE) }, - { PREFIX_TABLE (PREFIX_VEX_0F38DF) }, - /* e0 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* a8 */ { Bad_Opcode }, { Bad_Opcode }, - /* e8 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* b0 */ { Bad_Opcode }, { Bad_Opcode }, - /* f0 */ { Bad_Opcode }, { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_VEX_0F38F2) }, - { REG_TABLE (REG_VEX_0F38F3) }, { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_VEX_0F38F5) }, - { PREFIX_TABLE (PREFIX_VEX_0F38F6) }, - { PREFIX_TABLE (PREFIX_VEX_0F38F7) }, - /* f8 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* b8 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - }, - /* VEX_0F3A */ - { - /* 00 */ - { PREFIX_TABLE (PREFIX_VEX_0F3A00) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A01) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A02) }, { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_VEX_0F3A04) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A05) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A06) }, { Bad_Opcode }, - /* 08 */ - { PREFIX_TABLE (PREFIX_VEX_0F3A08) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A09) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A0A) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A0B) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A0C) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A0D) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A0E) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A0F) }, - /* 10 */ { Bad_Opcode }, + /* c0 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_VEX_0F3A14) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A15) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A16) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A17) }, - /* 18 */ - { PREFIX_TABLE (PREFIX_VEX_0F3A18) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A19) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_VEX_0F3A1D) }, { Bad_Opcode }, { Bad_Opcode }, - /* 20 */ - { PREFIX_TABLE (PREFIX_VEX_0F3A20) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A21) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A22) }, + /* c8 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* 28 */ { Bad_Opcode }, + { PREFIX_TABLE(PREFIX_VEX_0F3ACE) }, + { PREFIX_TABLE(PREFIX_VEX_0F3ACF) }, + /* d0 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -9414,43 +9286,26 @@ static const struct dis386 vex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* 30 */ - { PREFIX_TABLE (PREFIX_VEX_0F3A30) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A31) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A32) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A33) }, { Bad_Opcode }, + /* d8 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* 38 */ - { PREFIX_TABLE (PREFIX_VEX_0F3A38) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A39) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F3ADF) }, + /* e0 */ { Bad_Opcode }, { Bad_Opcode }, - /* 40 */ - { PREFIX_TABLE (PREFIX_VEX_0F3A40) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A41) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A42) }, { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_VEX_0F3A44) }, { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_VEX_0F3A46) }, { Bad_Opcode }, - /* 48 */ - { PREFIX_TABLE (PREFIX_VEX_0F3A48) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A49) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A4A) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A4B) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A4C) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* 50 */ + /* e8 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -9459,34 +9314,17 @@ static const struct dis386 vex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - /* 58 */ + /* f0 */ + { PREFIX_TABLE (PREFIX_VEX_0F3AF0) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_VEX_0F3A5C) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A5D) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A5E) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A5F) }, - /* 60 */ - { PREFIX_TABLE (PREFIX_VEX_0F3A60) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A61) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A62) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A63) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + /* f8 */ { Bad_Opcode }, - /* 68 */ - { PREFIX_TABLE (PREFIX_VEX_0F3A68) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A69) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A6A) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A6B) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A6C) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A6D) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A6E) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A6F) }, - /* 70 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -9494,2006 +9332,772 @@ static const struct dis386 vex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, + }, +}; + +#include "i386-dis-evex.h" + +static const struct dis386 vex_len_table[][2] = { + /* VEX_LEN_0F12_P_0_M_0 */ + { + { "vmovlps", { XM, Vex128, EXq }, 0 }, + }, + + /* VEX_LEN_0F12_P_0_M_1 */ + { + { "vmovhlps", { XM, Vex128, EXq }, 0 }, + }, + + /* VEX_LEN_0F12_P_2 */ + { + { "vmovlpd", { XM, Vex128, EXq }, 0 }, + }, + + /* VEX_LEN_0F13_M_0 */ + { + { "vmovlpX", { EXq, XM }, 0 }, + }, + + /* VEX_LEN_0F16_P_0_M_0 */ + { + { "vmovhps", { XM, Vex128, EXq }, 0 }, + }, + + /* VEX_LEN_0F16_P_0_M_1 */ + { + { "vmovlhps", { XM, Vex128, EXq }, 0 }, + }, + + /* VEX_LEN_0F16_P_2 */ + { + { "vmovhpd", { XM, Vex128, EXq }, 0 }, + }, + + /* VEX_LEN_0F17_M_0 */ + { + { "vmovhpX", { EXq, XM }, 0 }, + }, + + /* VEX_LEN_0F41_P_0 */ + { { Bad_Opcode }, - /* 78 */ - { PREFIX_TABLE (PREFIX_VEX_0F3A78) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A79) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A7A) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A7B) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A7C) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A7D) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A7E) }, - { PREFIX_TABLE (PREFIX_VEX_0F3A7F) }, - /* 80 */ + { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) }, + }, + /* VEX_LEN_0F41_P_2 */ + { { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) }, + }, + /* VEX_LEN_0F42_P_0 */ + { { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) }, + }, + /* VEX_LEN_0F42_P_2 */ + { { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) }, + }, + /* VEX_LEN_0F44_P_0 */ + { + { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) }, + }, + /* VEX_LEN_0F44_P_2 */ + { + { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) }, + }, + /* VEX_LEN_0F45_P_0 */ + { { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) }, + }, + /* VEX_LEN_0F45_P_2 */ + { { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) }, + }, + /* VEX_LEN_0F46_P_0 */ + { { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) }, + }, + /* VEX_LEN_0F46_P_2 */ + { { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) }, + }, + /* VEX_LEN_0F47_P_0 */ + { { Bad_Opcode }, - /* 88 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* 90 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* 98 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* a0 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* a8 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* b0 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* b8 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* c0 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* c8 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* d0 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* d8 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_VEX_0F3ADF) }, - /* e0 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* e8 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* f0 */ - { PREFIX_TABLE (PREFIX_VEX_0F3AF0) }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* f8 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - }, -}; - -#define NEED_OPCODE_TABLE -#include "i386-dis-evex.h" -#undef NEED_OPCODE_TABLE -static const struct dis386 vex_len_table[][2] = { - /* VEX_LEN_0F10_P_1 */ - { - { VEX_W_TABLE (VEX_W_0F10_P_1) }, - { VEX_W_TABLE (VEX_W_0F10_P_1) }, - }, - - /* VEX_LEN_0F10_P_3 */ - { - { VEX_W_TABLE (VEX_W_0F10_P_3) }, - { VEX_W_TABLE (VEX_W_0F10_P_3) }, - }, - - /* VEX_LEN_0F11_P_1 */ - { - { VEX_W_TABLE (VEX_W_0F11_P_1) }, - { VEX_W_TABLE (VEX_W_0F11_P_1) }, - }, - - /* VEX_LEN_0F11_P_3 */ - { - { VEX_W_TABLE (VEX_W_0F11_P_3) }, - { VEX_W_TABLE (VEX_W_0F11_P_3) }, - }, - - /* VEX_LEN_0F12_P_0_M_0 */ - { - { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) }, - }, - - /* VEX_LEN_0F12_P_0_M_1 */ - { - { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) }, - }, - - /* VEX_LEN_0F12_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F12_P_2) }, - }, - - /* VEX_LEN_0F13_M_0 */ - { - { VEX_W_TABLE (VEX_W_0F13_M_0) }, - }, - - /* VEX_LEN_0F16_P_0_M_0 */ - { - { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) }, - }, - - /* VEX_LEN_0F16_P_0_M_1 */ - { - { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) }, - }, - - /* VEX_LEN_0F16_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F16_P_2) }, - }, - - /* VEX_LEN_0F17_M_0 */ - { - { VEX_W_TABLE (VEX_W_0F17_M_0) }, - }, - - /* VEX_LEN_0F2A_P_1 */ - { - { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 }, - { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 }, - }, - - /* VEX_LEN_0F2A_P_3 */ - { - { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 }, - { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 }, - }, - - /* VEX_LEN_0F2C_P_1 */ - { - { "vcvttss2siY", { Gv, EXdScalar }, 0 }, - { "vcvttss2siY", { Gv, EXdScalar }, 0 }, - }, - - /* VEX_LEN_0F2C_P_3 */ - { - { "vcvttsd2siY", { Gv, EXqScalar }, 0 }, - { "vcvttsd2siY", { Gv, EXqScalar }, 0 }, - }, - - /* VEX_LEN_0F2D_P_1 */ - { - { "vcvtss2siY", { Gv, EXdScalar }, 0 }, - { "vcvtss2siY", { Gv, EXdScalar }, 0 }, - }, - - /* VEX_LEN_0F2D_P_3 */ - { - { "vcvtsd2siY", { Gv, EXqScalar }, 0 }, - { "vcvtsd2siY", { Gv, EXqScalar }, 0 }, - }, - - /* VEX_LEN_0F2E_P_0 */ - { - { VEX_W_TABLE (VEX_W_0F2E_P_0) }, - { VEX_W_TABLE (VEX_W_0F2E_P_0) }, - }, - - /* VEX_LEN_0F2E_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F2E_P_2) }, - { VEX_W_TABLE (VEX_W_0F2E_P_2) }, - }, - - /* VEX_LEN_0F2F_P_0 */ - { - { VEX_W_TABLE (VEX_W_0F2F_P_0) }, - { VEX_W_TABLE (VEX_W_0F2F_P_0) }, - }, - - /* VEX_LEN_0F2F_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F2F_P_2) }, - { VEX_W_TABLE (VEX_W_0F2F_P_2) }, - }, - - /* VEX_LEN_0F41_P_0 */ - { - { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) }, - }, - /* VEX_LEN_0F41_P_2 */ - { - { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) }, - }, - /* VEX_LEN_0F42_P_0 */ - { - { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) }, - }, - /* VEX_LEN_0F42_P_2 */ - { - { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) }, - }, - /* VEX_LEN_0F44_P_0 */ - { - { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) }, - }, - /* VEX_LEN_0F44_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) }, - }, - /* VEX_LEN_0F45_P_0 */ - { - { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) }, + { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) }, }, - /* VEX_LEN_0F45_P_2 */ + /* VEX_LEN_0F47_P_2 */ { { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) }, + { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) }, }, - /* VEX_LEN_0F46_P_0 */ + /* VEX_LEN_0F4A_P_0 */ { - { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) }, - }, - /* VEX_LEN_0F46_P_2 */ - { - { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) }, - }, - /* VEX_LEN_0F47_P_0 */ - { - { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) }, - }, - /* VEX_LEN_0F47_P_2 */ - { - { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) }, - }, - /* VEX_LEN_0F4A_P_0 */ - { - { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) }, - }, - /* VEX_LEN_0F4A_P_2 */ - { - { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) }, - }, - /* VEX_LEN_0F4B_P_0 */ - { - { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) }, - }, - /* VEX_LEN_0F4B_P_2 */ - { - { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) }, - }, - - /* VEX_LEN_0F51_P_1 */ - { - { VEX_W_TABLE (VEX_W_0F51_P_1) }, - { VEX_W_TABLE (VEX_W_0F51_P_1) }, - }, - - /* VEX_LEN_0F51_P_3 */ - { - { VEX_W_TABLE (VEX_W_0F51_P_3) }, - { VEX_W_TABLE (VEX_W_0F51_P_3) }, - }, - - /* VEX_LEN_0F52_P_1 */ - { - { VEX_W_TABLE (VEX_W_0F52_P_1) }, - { VEX_W_TABLE (VEX_W_0F52_P_1) }, - }, - - /* VEX_LEN_0F53_P_1 */ - { - { VEX_W_TABLE (VEX_W_0F53_P_1) }, - { VEX_W_TABLE (VEX_W_0F53_P_1) }, - }, - - /* VEX_LEN_0F58_P_1 */ - { - { VEX_W_TABLE (VEX_W_0F58_P_1) }, - { VEX_W_TABLE (VEX_W_0F58_P_1) }, - }, - - /* VEX_LEN_0F58_P_3 */ - { - { VEX_W_TABLE (VEX_W_0F58_P_3) }, - { VEX_W_TABLE (VEX_W_0F58_P_3) }, - }, - - /* VEX_LEN_0F59_P_1 */ - { - { VEX_W_TABLE (VEX_W_0F59_P_1) }, - { VEX_W_TABLE (VEX_W_0F59_P_1) }, - }, - - /* VEX_LEN_0F59_P_3 */ - { - { VEX_W_TABLE (VEX_W_0F59_P_3) }, - { VEX_W_TABLE (VEX_W_0F59_P_3) }, - }, - - /* VEX_LEN_0F5A_P_1 */ - { - { VEX_W_TABLE (VEX_W_0F5A_P_1) }, - { VEX_W_TABLE (VEX_W_0F5A_P_1) }, - }, - - /* VEX_LEN_0F5A_P_3 */ - { - { VEX_W_TABLE (VEX_W_0F5A_P_3) }, - { VEX_W_TABLE (VEX_W_0F5A_P_3) }, - }, - - /* VEX_LEN_0F5C_P_1 */ - { - { VEX_W_TABLE (VEX_W_0F5C_P_1) }, - { VEX_W_TABLE (VEX_W_0F5C_P_1) }, - }, - - /* VEX_LEN_0F5C_P_3 */ - { - { VEX_W_TABLE (VEX_W_0F5C_P_3) }, - { VEX_W_TABLE (VEX_W_0F5C_P_3) }, - }, - - /* VEX_LEN_0F5D_P_1 */ - { - { VEX_W_TABLE (VEX_W_0F5D_P_1) }, - { VEX_W_TABLE (VEX_W_0F5D_P_1) }, - }, - - /* VEX_LEN_0F5D_P_3 */ - { - { VEX_W_TABLE (VEX_W_0F5D_P_3) }, - { VEX_W_TABLE (VEX_W_0F5D_P_3) }, - }, - - /* VEX_LEN_0F5E_P_1 */ - { - { VEX_W_TABLE (VEX_W_0F5E_P_1) }, - { VEX_W_TABLE (VEX_W_0F5E_P_1) }, - }, - - /* VEX_LEN_0F5E_P_3 */ - { - { VEX_W_TABLE (VEX_W_0F5E_P_3) }, - { VEX_W_TABLE (VEX_W_0F5E_P_3) }, - }, - - /* VEX_LEN_0F5F_P_1 */ - { - { VEX_W_TABLE (VEX_W_0F5F_P_1) }, - { VEX_W_TABLE (VEX_W_0F5F_P_1) }, - }, - - /* VEX_LEN_0F5F_P_3 */ - { - { VEX_W_TABLE (VEX_W_0F5F_P_3) }, - { VEX_W_TABLE (VEX_W_0F5F_P_3) }, - }, - - /* VEX_LEN_0F6E_P_2 */ - { - { "vmovK", { XMScalar, Edq }, 0 }, - { "vmovK", { XMScalar, Edq }, 0 }, - }, - - /* VEX_LEN_0F7E_P_1 */ - { - { VEX_W_TABLE (VEX_W_0F7E_P_1) }, - { VEX_W_TABLE (VEX_W_0F7E_P_1) }, - }, - - /* VEX_LEN_0F7E_P_2 */ - { - { "vmovK", { Edq, XMScalar }, 0 }, - { "vmovK", { Edq, XMScalar }, 0 }, - }, - - /* VEX_LEN_0F90_P_0 */ - { - { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) }, - }, - - /* VEX_LEN_0F90_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) }, - }, - - /* VEX_LEN_0F91_P_0 */ - { - { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) }, - }, - - /* VEX_LEN_0F91_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) }, - }, - - /* VEX_LEN_0F92_P_0 */ - { - { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) }, - }, - - /* VEX_LEN_0F92_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) }, - }, - - /* VEX_LEN_0F92_P_3 */ - { - { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) }, - }, - - /* VEX_LEN_0F93_P_0 */ - { - { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) }, - }, - - /* VEX_LEN_0F93_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) }, - }, - - /* VEX_LEN_0F93_P_3 */ - { - { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) }, - }, - - /* VEX_LEN_0F98_P_0 */ - { - { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) }, - }, - - /* VEX_LEN_0F98_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) }, - }, - - /* VEX_LEN_0F99_P_0 */ - { - { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) }, - }, - - /* VEX_LEN_0F99_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) }, - }, - - /* VEX_LEN_0FAE_R_2_M_0 */ - { - { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) }, - }, - - /* VEX_LEN_0FAE_R_3_M_0 */ - { - { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) }, - }, - - /* VEX_LEN_0FC2_P_1 */ - { - { VEX_W_TABLE (VEX_W_0FC2_P_1) }, - { VEX_W_TABLE (VEX_W_0FC2_P_1) }, - }, - - /* VEX_LEN_0FC2_P_3 */ - { - { VEX_W_TABLE (VEX_W_0FC2_P_3) }, - { VEX_W_TABLE (VEX_W_0FC2_P_3) }, - }, - - /* VEX_LEN_0FC4_P_2 */ - { - { VEX_W_TABLE (VEX_W_0FC4_P_2) }, - }, - - /* VEX_LEN_0FC5_P_2 */ - { - { VEX_W_TABLE (VEX_W_0FC5_P_2) }, - }, - - /* VEX_LEN_0FD6_P_2 */ - { - { VEX_W_TABLE (VEX_W_0FD6_P_2) }, - { VEX_W_TABLE (VEX_W_0FD6_P_2) }, - }, - - /* VEX_LEN_0FF7_P_2 */ - { - { VEX_W_TABLE (VEX_W_0FF7_P_2) }, - }, - - /* VEX_LEN_0F3816_P_2 */ - { - { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3816_P_2) }, - }, - - /* VEX_LEN_0F3819_P_2 */ - { - { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3819_P_2) }, - }, - - /* VEX_LEN_0F381A_P_2_M_0 */ - { - { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) }, - }, - - /* VEX_LEN_0F3836_P_2 */ - { - { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3836_P_2) }, - }, - - /* VEX_LEN_0F3841_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F3841_P_2) }, - }, - - /* VEX_LEN_0F385A_P_2_M_0 */ - { - { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) }, - }, - - /* VEX_LEN_0F38DB_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F38DB_P_2) }, - }, - - /* VEX_LEN_0F38DC_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F38DC_P_2) }, - }, - - /* VEX_LEN_0F38DD_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F38DD_P_2) }, - }, - - /* VEX_LEN_0F38DE_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F38DE_P_2) }, - }, - - /* VEX_LEN_0F38DF_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F38DF_P_2) }, - }, - - /* VEX_LEN_0F38F2_P_0 */ - { - { "andnS", { Gdq, VexGdq, Edq }, 0 }, - }, - - /* VEX_LEN_0F38F3_R_1_P_0 */ - { - { "blsrS", { VexGdq, Edq }, 0 }, - }, - - /* VEX_LEN_0F38F3_R_2_P_0 */ - { - { "blsmskS", { VexGdq, Edq }, 0 }, - }, - - /* VEX_LEN_0F38F3_R_3_P_0 */ - { - { "blsiS", { VexGdq, Edq }, 0 }, - }, - - /* VEX_LEN_0F38F5_P_0 */ - { - { "bzhiS", { Gdq, Edq, VexGdq }, 0 }, - }, - - /* VEX_LEN_0F38F5_P_1 */ - { - { "pextS", { Gdq, VexGdq, Edq }, 0 }, - }, - - /* VEX_LEN_0F38F5_P_3 */ - { - { "pdepS", { Gdq, VexGdq, Edq }, 0 }, - }, - - /* VEX_LEN_0F38F6_P_3 */ - { - { "mulxS", { Gdq, VexGdq, Edq }, 0 }, - }, - - /* VEX_LEN_0F38F7_P_0 */ - { - { "bextrS", { Gdq, Edq, VexGdq }, 0 }, - }, - - /* VEX_LEN_0F38F7_P_1 */ - { - { "sarxS", { Gdq, Edq, VexGdq }, 0 }, - }, - - /* VEX_LEN_0F38F7_P_2 */ - { - { "shlxS", { Gdq, Edq, VexGdq }, 0 }, - }, - - /* VEX_LEN_0F38F7_P_3 */ - { - { "shrxS", { Gdq, Edq, VexGdq }, 0 }, - }, - - /* VEX_LEN_0F3A00_P_2 */ - { - { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3A00_P_2) }, - }, - - /* VEX_LEN_0F3A01_P_2 */ - { - { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3A01_P_2) }, - }, - - /* VEX_LEN_0F3A06_P_2 */ - { - { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3A06_P_2) }, - }, - - /* VEX_LEN_0F3A0A_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, - { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, - }, - - /* VEX_LEN_0F3A0B_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, - { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, - }, - - /* VEX_LEN_0F3A14_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F3A14_P_2) }, - }, - - /* VEX_LEN_0F3A15_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F3A15_P_2) }, - }, - - /* VEX_LEN_0F3A16_P_2 */ - { - { "vpextrK", { Edq, XM, Ib }, 0 }, - }, - - /* VEX_LEN_0F3A17_P_2 */ - { - { "vextractps", { Edqd, XM, Ib }, 0 }, - }, - - /* VEX_LEN_0F3A18_P_2 */ - { - { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3A18_P_2) }, - }, - - /* VEX_LEN_0F3A19_P_2 */ - { - { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3A19_P_2) }, - }, - - /* VEX_LEN_0F3A20_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F3A20_P_2) }, - }, - - /* VEX_LEN_0F3A21_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F3A21_P_2) }, - }, - - /* VEX_LEN_0F3A22_P_2 */ - { - { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 }, - }, - - /* VEX_LEN_0F3A30_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) }, - }, - - /* VEX_LEN_0F3A31_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) }, - }, - - /* VEX_LEN_0F3A32_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) }, - }, - - /* VEX_LEN_0F3A33_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) }, - }, - - /* VEX_LEN_0F3A38_P_2 */ - { - { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3A38_P_2) }, - }, - - /* VEX_LEN_0F3A39_P_2 */ - { - { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3A39_P_2) }, - }, - - /* VEX_LEN_0F3A41_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F3A41_P_2) }, - }, - - /* VEX_LEN_0F3A44_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F3A44_P_2) }, - }, - - /* VEX_LEN_0F3A46_P_2 */ - { - { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3A46_P_2) }, - }, - - /* VEX_LEN_0F3A60_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F3A60_P_2) }, - }, - - /* VEX_LEN_0F3A61_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F3A61_P_2) }, - }, - - /* VEX_LEN_0F3A62_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F3A62_P_2) }, - }, - - /* VEX_LEN_0F3A63_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F3A63_P_2) }, - }, - - /* VEX_LEN_0F3A6A_P_2 */ - { - { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, - }, - - /* VEX_LEN_0F3A6B_P_2 */ - { - { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, - }, - - /* VEX_LEN_0F3A6E_P_2 */ - { - { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, - }, - - /* VEX_LEN_0F3A6F_P_2 */ - { - { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, - }, - - /* VEX_LEN_0F3A7A_P_2 */ - { - { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, - }, - - /* VEX_LEN_0F3A7B_P_2 */ - { - { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, - }, - - /* VEX_LEN_0F3A7E_P_2 */ - { - { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, - }, - - /* VEX_LEN_0F3A7F_P_2 */ - { - { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, - }, - - /* VEX_LEN_0F3ADF_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F3ADF_P_2) }, - }, - - /* VEX_LEN_0F3AF0_P_3 */ - { - { "rorxS", { Gdq, Edq, Ib }, 0 }, - }, - - /* VEX_LEN_0FXOP_08_CC */ - { - { "vpcomb", { XM, Vex128, EXx, Ib }, 0 }, - }, - - /* VEX_LEN_0FXOP_08_CD */ - { - { "vpcomw", { XM, Vex128, EXx, Ib }, 0 }, - }, - - /* VEX_LEN_0FXOP_08_CE */ - { - { "vpcomd", { XM, Vex128, EXx, Ib }, 0 }, - }, - - /* VEX_LEN_0FXOP_08_CF */ - { - { "vpcomq", { XM, Vex128, EXx, Ib }, 0 }, - }, - - /* VEX_LEN_0FXOP_08_EC */ - { - { "vpcomub", { XM, Vex128, EXx, Ib }, 0 }, - }, - - /* VEX_LEN_0FXOP_08_ED */ - { - { "vpcomuw", { XM, Vex128, EXx, Ib }, 0 }, - }, - - /* VEX_LEN_0FXOP_08_EE */ - { - { "vpcomud", { XM, Vex128, EXx, Ib }, 0 }, - }, - - /* VEX_LEN_0FXOP_08_EF */ - { - { "vpcomuq", { XM, Vex128, EXx, Ib }, 0 }, - }, - - /* VEX_LEN_0FXOP_09_80 */ - { - { "vfrczps", { XM, EXxmm }, 0 }, - { "vfrczps", { XM, EXymmq }, 0 }, - }, - - /* VEX_LEN_0FXOP_09_81 */ - { - { "vfrczpd", { XM, EXxmm }, 0 }, - { "vfrczpd", { XM, EXymmq }, 0 }, - }, -}; - -static const struct dis386 vex_w_table[][2] = { - { - /* VEX_W_0F10_P_0 */ - { "vmovups", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F10_P_1 */ - { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 }, - }, - { - /* VEX_W_0F10_P_2 */ - { "vmovupd", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F10_P_3 */ - { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 }, - }, - { - /* VEX_W_0F11_P_0 */ - { "vmovups", { EXxS, XM }, 0 }, - }, - { - /* VEX_W_0F11_P_1 */ - { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 }, - }, - { - /* VEX_W_0F11_P_2 */ - { "vmovupd", { EXxS, XM }, 0 }, - }, - { - /* VEX_W_0F11_P_3 */ - { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 }, - }, - { - /* VEX_W_0F12_P_0_M_0 */ - { "vmovlps", { XM, Vex128, EXq }, 0 }, - }, - { - /* VEX_W_0F12_P_0_M_1 */ - { "vmovhlps", { XM, Vex128, EXq }, 0 }, - }, - { - /* VEX_W_0F12_P_1 */ - { "vmovsldup", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F12_P_2 */ - { "vmovlpd", { XM, Vex128, EXq }, 0 }, - }, - { - /* VEX_W_0F12_P_3 */ - { "vmovddup", { XM, EXymmq }, 0 }, - }, - { - /* VEX_W_0F13_M_0 */ - { "vmovlpX", { EXq, XM }, 0 }, - }, - { - /* VEX_W_0F14 */ - { "vunpcklpX", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F15 */ - { "vunpckhpX", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F16_P_0_M_0 */ - { "vmovhps", { XM, Vex128, EXq }, 0 }, - }, - { - /* VEX_W_0F16_P_0_M_1 */ - { "vmovlhps", { XM, Vex128, EXq }, 0 }, - }, - { - /* VEX_W_0F16_P_1 */ - { "vmovshdup", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F16_P_2 */ - { "vmovhpd", { XM, Vex128, EXq }, 0 }, - }, - { - /* VEX_W_0F17_M_0 */ - { "vmovhpX", { EXq, XM }, 0 }, - }, - { - /* VEX_W_0F28 */ - { "vmovapX", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F29 */ - { "vmovapX", { EXxS, XM }, 0 }, - }, - { - /* VEX_W_0F2B_M_0 */ - { "vmovntpX", { Mx, XM }, 0 }, - }, - { - /* VEX_W_0F2E_P_0 */ - { "vucomiss", { XMScalar, EXdScalar }, 0 }, - }, - { - /* VEX_W_0F2E_P_2 */ - { "vucomisd", { XMScalar, EXqScalar }, 0 }, - }, - { - /* VEX_W_0F2F_P_0 */ - { "vcomiss", { XMScalar, EXdScalar }, 0 }, - }, - { - /* VEX_W_0F2F_P_2 */ - { "vcomisd", { XMScalar, EXqScalar }, 0 }, - }, - { - /* VEX_W_0F41_P_0_LEN_1 */ - { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) }, - { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) }, - }, - { - /* VEX_W_0F41_P_2_LEN_1 */ - { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) }, - { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) } - }, - { - /* VEX_W_0F42_P_0_LEN_1 */ - { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) }, - { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) }, - }, - { - /* VEX_W_0F42_P_2_LEN_1 */ - { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) }, - { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) }, - }, - { - /* VEX_W_0F44_P_0_LEN_0 */ - { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) }, - { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) }, - }, - { - /* VEX_W_0F44_P_2_LEN_0 */ - { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) }, - { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) }, - }, - { - /* VEX_W_0F45_P_0_LEN_1 */ - { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) }, - { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) }, - }, - { - /* VEX_W_0F45_P_2_LEN_1 */ - { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) }, - { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) }, - }, - { - /* VEX_W_0F46_P_0_LEN_1 */ - { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) }, - { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) }, - }, - { - /* VEX_W_0F46_P_2_LEN_1 */ - { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) }, - { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) }, - }, - { - /* VEX_W_0F47_P_0_LEN_1 */ - { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) }, - { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) }, - }, - { - /* VEX_W_0F47_P_2_LEN_1 */ - { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) }, - { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) }, - }, - { - /* VEX_W_0F4A_P_0_LEN_1 */ - { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) }, - { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) }, - }, - { - /* VEX_W_0F4A_P_2_LEN_1 */ - { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) }, - { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) }, - }, - { - /* VEX_W_0F4B_P_0_LEN_1 */ - { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) }, - { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) }, - }, - { - /* VEX_W_0F4B_P_2_LEN_1 */ - { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) }, - }, - { - /* VEX_W_0F50_M_0 */ - { "vmovmskpX", { Gdq, XS }, 0 }, - }, - { - /* VEX_W_0F51_P_0 */ - { "vsqrtps", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F51_P_1 */ - { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, - }, - { - /* VEX_W_0F51_P_2 */ - { "vsqrtpd", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F51_P_3 */ - { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 }, - }, - { - /* VEX_W_0F52_P_0 */ - { "vrsqrtps", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F52_P_1 */ - { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, - }, - { - /* VEX_W_0F53_P_0 */ - { "vrcpps", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F53_P_1 */ - { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 }, - }, - { - /* VEX_W_0F58_P_0 */ - { "vaddps", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F58_P_1 */ - { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 }, - }, - { - /* VEX_W_0F58_P_2 */ - { "vaddpd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F58_P_3 */ - { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 }, - }, - { - /* VEX_W_0F59_P_0 */ - { "vmulps", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F59_P_1 */ - { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 }, - }, - { - /* VEX_W_0F59_P_2 */ - { "vmulpd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F59_P_3 */ - { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 }, - }, - { - /* VEX_W_0F5A_P_0 */ - { "vcvtps2pd", { XM, EXxmmq }, 0 }, - }, - { - /* VEX_W_0F5A_P_1 */ - { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 }, - }, - { - /* VEX_W_0F5A_P_3 */ - { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 }, - }, - { - /* VEX_W_0F5B_P_0 */ - { "vcvtdq2ps", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F5B_P_1 */ - { "vcvttps2dq", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F5B_P_2 */ - { "vcvtps2dq", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F5C_P_0 */ - { "vsubps", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F5C_P_1 */ - { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 }, - }, - { - /* VEX_W_0F5C_P_2 */ - { "vsubpd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F5C_P_3 */ - { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 }, - }, - { - /* VEX_W_0F5D_P_0 */ - { "vminps", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F5D_P_1 */ - { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 }, - }, - { - /* VEX_W_0F5D_P_2 */ - { "vminpd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F5D_P_3 */ - { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 }, - }, - { - /* VEX_W_0F5E_P_0 */ - { "vdivps", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F5E_P_1 */ - { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 }, - }, - { - /* VEX_W_0F5E_P_2 */ - { "vdivpd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F5E_P_3 */ - { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 }, - }, - { - /* VEX_W_0F5F_P_0 */ - { "vmaxps", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F5F_P_1 */ - { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 }, - }, - { - /* VEX_W_0F5F_P_2 */ - { "vmaxpd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F5F_P_3 */ - { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 }, - }, - { - /* VEX_W_0F60_P_2 */ - { "vpunpcklbw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F61_P_2 */ - { "vpunpcklwd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F62_P_2 */ - { "vpunpckldq", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F63_P_2 */ - { "vpacksswb", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F64_P_2 */ - { "vpcmpgtb", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F65_P_2 */ - { "vpcmpgtw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F66_P_2 */ - { "vpcmpgtd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F67_P_2 */ - { "vpackuswb", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F68_P_2 */ - { "vpunpckhbw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F69_P_2 */ - { "vpunpckhwd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F6A_P_2 */ - { "vpunpckhdq", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F6B_P_2 */ - { "vpackssdw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F6C_P_2 */ - { "vpunpcklqdq", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F6D_P_2 */ - { "vpunpckhqdq", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F6F_P_1 */ - { "vmovdqu", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F6F_P_2 */ - { "vmovdqa", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F70_P_1 */ - { "vpshufhw", { XM, EXx, Ib }, 0 }, - }, - { - /* VEX_W_0F70_P_2 */ - { "vpshufd", { XM, EXx, Ib }, 0 }, - }, - { - /* VEX_W_0F70_P_3 */ - { "vpshuflw", { XM, EXx, Ib }, 0 }, - }, - { - /* VEX_W_0F71_R_2_P_2 */ - { "vpsrlw", { Vex, XS, Ib }, 0 }, - }, - { - /* VEX_W_0F71_R_4_P_2 */ - { "vpsraw", { Vex, XS, Ib }, 0 }, - }, - { - /* VEX_W_0F71_R_6_P_2 */ - { "vpsllw", { Vex, XS, Ib }, 0 }, - }, - { - /* VEX_W_0F72_R_2_P_2 */ - { "vpsrld", { Vex, XS, Ib }, 0 }, - }, - { - /* VEX_W_0F72_R_4_P_2 */ - { "vpsrad", { Vex, XS, Ib }, 0 }, - }, - { - /* VEX_W_0F72_R_6_P_2 */ - { "vpslld", { Vex, XS, Ib }, 0 }, - }, - { - /* VEX_W_0F73_R_2_P_2 */ - { "vpsrlq", { Vex, XS, Ib }, 0 }, - }, - { - /* VEX_W_0F73_R_3_P_2 */ - { "vpsrldq", { Vex, XS, Ib }, 0 }, - }, - { - /* VEX_W_0F73_R_6_P_2 */ - { "vpsllq", { Vex, XS, Ib }, 0 }, - }, - { - /* VEX_W_0F73_R_7_P_2 */ - { "vpslldq", { Vex, XS, Ib }, 0 }, - }, - { - /* VEX_W_0F74_P_2 */ - { "vpcmpeqb", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F75_P_2 */ - { "vpcmpeqw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F76_P_2 */ - { "vpcmpeqd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F77_P_0 */ - { "", { VZERO }, 0 }, - }, - { - /* VEX_W_0F7C_P_2 */ - { "vhaddpd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F7C_P_3 */ - { "vhaddps", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F7D_P_2 */ - { "vhsubpd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F7D_P_3 */ - { "vhsubps", { XM, Vex, EXx }, 0 }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) }, }, + /* VEX_LEN_0F4A_P_2 */ { - /* VEX_W_0F7E_P_1 */ - { "vmovq", { XMScalar, EXqScalar }, 0 }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) }, }, + /* VEX_LEN_0F4B_P_0 */ { - /* VEX_W_0F7F_P_1 */ - { "vmovdqu", { EXxS, XM }, 0 }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) }, }, + /* VEX_LEN_0F4B_P_2 */ { - /* VEX_W_0F7F_P_2 */ - { "vmovdqa", { EXxS, XM }, 0 }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) }, }, + + /* VEX_LEN_0F6E_P_2 */ { - /* VEX_W_0F90_P_0_LEN_0 */ - { "kmovw", { MaskG, MaskE }, 0 }, - { "kmovq", { MaskG, MaskE }, 0 }, + { "vmovK", { XMScalar, Edq }, 0 }, }, + + /* VEX_LEN_0F77_P_1 */ { - /* VEX_W_0F90_P_2_LEN_0 */ - { "kmovb", { MaskG, MaskBDE }, 0 }, - { "kmovd", { MaskG, MaskBDE }, 0 }, + { "vzeroupper", { XX }, 0 }, + { "vzeroall", { XX }, 0 }, }, + + /* VEX_LEN_0F7E_P_1 */ { - /* VEX_W_0F91_P_0_LEN_0 */ - { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) }, - { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) }, + { "vmovq", { XMScalar, EXqScalar }, 0 }, }, + + /* VEX_LEN_0F7E_P_2 */ { - /* VEX_W_0F91_P_2_LEN_0 */ - { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) }, - { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) }, + { "vmovK", { Edq, XMScalar }, 0 }, }, + + /* VEX_LEN_0F90_P_0 */ { - /* VEX_W_0F92_P_0_LEN_0 */ - { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) }, + { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) }, }, + + /* VEX_LEN_0F90_P_2 */ { - /* VEX_W_0F92_P_2_LEN_0 */ - { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) }, + { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) }, }, + + /* VEX_LEN_0F91_P_0 */ { - /* VEX_W_0F92_P_3_LEN_0 */ - { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) }, - { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) }, + { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) }, }, + + /* VEX_LEN_0F91_P_2 */ { - /* VEX_W_0F93_P_0_LEN_0 */ - { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) }, + { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) }, }, + + /* VEX_LEN_0F92_P_0 */ { - /* VEX_W_0F93_P_2_LEN_0 */ - { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) }, + { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) }, }, + + /* VEX_LEN_0F92_P_2 */ { - /* VEX_W_0F93_P_3_LEN_0 */ - { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) }, - { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) }, + { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) }, }, + + /* VEX_LEN_0F92_P_3 */ { - /* VEX_W_0F98_P_0_LEN_0 */ - { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) }, - { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) }, + { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) }, }, + + /* VEX_LEN_0F93_P_0 */ { - /* VEX_W_0F98_P_2_LEN_0 */ - { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) }, - { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) }, + { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) }, }, + + /* VEX_LEN_0F93_P_2 */ { - /* VEX_W_0F99_P_0_LEN_0 */ - { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) }, - { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) }, + { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) }, }, + + /* VEX_LEN_0F93_P_3 */ { - /* VEX_W_0F99_P_2_LEN_0 */ - { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) }, - { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) }, + { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) }, }, + + /* VEX_LEN_0F98_P_0 */ { - /* VEX_W_0FAE_R_2_M_0 */ - { "vldmxcsr", { Md }, 0 }, + { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) }, }, + + /* VEX_LEN_0F98_P_2 */ { - /* VEX_W_0FAE_R_3_M_0 */ - { "vstmxcsr", { Md }, 0 }, + { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) }, }, + + /* VEX_LEN_0F99_P_0 */ { - /* VEX_W_0FC2_P_0 */ - { "vcmpps", { XM, Vex, EXx, VCMP }, 0 }, + { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) }, }, + + /* VEX_LEN_0F99_P_2 */ { - /* VEX_W_0FC2_P_1 */ - { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 }, + { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) }, }, + + /* VEX_LEN_0FAE_R_2_M_0 */ { - /* VEX_W_0FC2_P_2 */ - { "vcmppd", { XM, Vex, EXx, VCMP }, 0 }, + { "vldmxcsr", { Md }, 0 }, }, + + /* VEX_LEN_0FAE_R_3_M_0 */ { - /* VEX_W_0FC2_P_3 */ - { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 }, + { "vstmxcsr", { Md }, 0 }, }, + + /* VEX_LEN_0FC4_P_2 */ { - /* VEX_W_0FC4_P_2 */ { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 }, }, + + /* VEX_LEN_0FC5_P_2 */ { - /* VEX_W_0FC5_P_2 */ { "vpextrw", { Gdq, XS, Ib }, 0 }, }, + + /* VEX_LEN_0FD6_P_2 */ { - /* VEX_W_0FD0_P_2 */ - { "vaddsubpd", { XM, Vex, EXx }, 0 }, + { "vmovq", { EXqScalarS, XMScalar }, 0 }, }, + + /* VEX_LEN_0FF7_P_2 */ { - /* VEX_W_0FD0_P_3 */ - { "vaddsubps", { XM, Vex, EXx }, 0 }, + { "vmaskmovdqu", { XM, XS }, 0 }, }, + + /* VEX_LEN_0F3816_P_2 */ { - /* VEX_W_0FD1_P_2 */ - { "vpsrlw", { XM, Vex, EXxmm }, 0 }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F3816_P_2) }, }, + + /* VEX_LEN_0F3819_P_2 */ { - /* VEX_W_0FD2_P_2 */ - { "vpsrld", { XM, Vex, EXxmm }, 0 }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F3819_P_2) }, }, + + /* VEX_LEN_0F381A_P_2_M_0 */ { - /* VEX_W_0FD3_P_2 */ - { "vpsrlq", { XM, Vex, EXxmm }, 0 }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) }, }, + + /* VEX_LEN_0F3836_P_2 */ { - /* VEX_W_0FD4_P_2 */ - { "vpaddq", { XM, Vex, EXx }, 0 }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F3836_P_2) }, }, + + /* VEX_LEN_0F3841_P_2 */ { - /* VEX_W_0FD5_P_2 */ - { "vpmullw", { XM, Vex, EXx }, 0 }, + { "vphminposuw", { XM, EXx }, 0 }, }, + + /* VEX_LEN_0F385A_P_2_M_0 */ { - /* VEX_W_0FD6_P_2 */ - { "vmovq", { EXqScalarS, XMScalar }, 0 }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) }, }, + + /* VEX_LEN_0F38DB_P_2 */ { - /* VEX_W_0FD7_P_2_M_1 */ - { "vpmovmskb", { Gdq, XS }, 0 }, + { "vaesimc", { XM, EXx }, 0 }, }, + + /* VEX_LEN_0F38F2_P_0 */ { - /* VEX_W_0FD8_P_2 */ - { "vpsubusb", { XM, Vex, EXx }, 0 }, + { "andnS", { Gdq, VexGdq, Edq }, 0 }, }, + + /* VEX_LEN_0F38F3_R_1_P_0 */ { - /* VEX_W_0FD9_P_2 */ - { "vpsubusw", { XM, Vex, EXx }, 0 }, + { "blsrS", { VexGdq, Edq }, 0 }, }, + + /* VEX_LEN_0F38F3_R_2_P_0 */ { - /* VEX_W_0FDA_P_2 */ - { "vpminub", { XM, Vex, EXx }, 0 }, + { "blsmskS", { VexGdq, Edq }, 0 }, }, + + /* VEX_LEN_0F38F3_R_3_P_0 */ { - /* VEX_W_0FDB_P_2 */ - { "vpand", { XM, Vex, EXx }, 0 }, + { "blsiS", { VexGdq, Edq }, 0 }, }, + + /* VEX_LEN_0F38F5_P_0 */ { - /* VEX_W_0FDC_P_2 */ - { "vpaddusb", { XM, Vex, EXx }, 0 }, + { "bzhiS", { Gdq, Edq, VexGdq }, 0 }, }, + + /* VEX_LEN_0F38F5_P_1 */ { - /* VEX_W_0FDD_P_2 */ - { "vpaddusw", { XM, Vex, EXx }, 0 }, + { "pextS", { Gdq, VexGdq, Edq }, 0 }, }, + + /* VEX_LEN_0F38F5_P_3 */ { - /* VEX_W_0FDE_P_2 */ - { "vpmaxub", { XM, Vex, EXx }, 0 }, + { "pdepS", { Gdq, VexGdq, Edq }, 0 }, }, + + /* VEX_LEN_0F38F6_P_3 */ { - /* VEX_W_0FDF_P_2 */ - { "vpandn", { XM, Vex, EXx }, 0 }, + { "mulxS", { Gdq, VexGdq, Edq }, 0 }, }, + + /* VEX_LEN_0F38F7_P_0 */ { - /* VEX_W_0FE0_P_2 */ - { "vpavgb", { XM, Vex, EXx }, 0 }, + { "bextrS", { Gdq, Edq, VexGdq }, 0 }, }, + + /* VEX_LEN_0F38F7_P_1 */ { - /* VEX_W_0FE1_P_2 */ - { "vpsraw", { XM, Vex, EXxmm }, 0 }, + { "sarxS", { Gdq, Edq, VexGdq }, 0 }, }, + + /* VEX_LEN_0F38F7_P_2 */ { - /* VEX_W_0FE2_P_2 */ - { "vpsrad", { XM, Vex, EXxmm }, 0 }, + { "shlxS", { Gdq, Edq, VexGdq }, 0 }, }, + + /* VEX_LEN_0F38F7_P_3 */ { - /* VEX_W_0FE3_P_2 */ - { "vpavgw", { XM, Vex, EXx }, 0 }, + { "shrxS", { Gdq, Edq, VexGdq }, 0 }, }, + + /* VEX_LEN_0F3A00_P_2 */ { - /* VEX_W_0FE4_P_2 */ - { "vpmulhuw", { XM, Vex, EXx }, 0 }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F3A00_P_2) }, }, + + /* VEX_LEN_0F3A01_P_2 */ { - /* VEX_W_0FE5_P_2 */ - { "vpmulhw", { XM, Vex, EXx }, 0 }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F3A01_P_2) }, }, + + /* VEX_LEN_0F3A06_P_2 */ { - /* VEX_W_0FE6_P_1 */ - { "vcvtdq2pd", { XM, EXxmmq }, 0 }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F3A06_P_2) }, }, + + /* VEX_LEN_0F3A14_P_2 */ { - /* VEX_W_0FE6_P_2 */ - { "vcvttpd2dq%XY", { XMM, EXx }, 0 }, + { "vpextrb", { Edqb, XM, Ib }, 0 }, }, + + /* VEX_LEN_0F3A15_P_2 */ { - /* VEX_W_0FE6_P_3 */ - { "vcvtpd2dq%XY", { XMM, EXx }, 0 }, + { "vpextrw", { Edqw, XM, Ib }, 0 }, }, + + /* VEX_LEN_0F3A16_P_2 */ { - /* VEX_W_0FE7_P_2_M_0 */ - { "vmovntdq", { Mx, XM }, 0 }, + { "vpextrK", { Edq, XM, Ib }, 0 }, }, + + /* VEX_LEN_0F3A17_P_2 */ { - /* VEX_W_0FE8_P_2 */ - { "vpsubsb", { XM, Vex, EXx }, 0 }, + { "vextractps", { Edqd, XM, Ib }, 0 }, }, + + /* VEX_LEN_0F3A18_P_2 */ { - /* VEX_W_0FE9_P_2 */ - { "vpsubsw", { XM, Vex, EXx }, 0 }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F3A18_P_2) }, }, + + /* VEX_LEN_0F3A19_P_2 */ { - /* VEX_W_0FEA_P_2 */ - { "vpminsw", { XM, Vex, EXx }, 0 }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F3A19_P_2) }, }, + + /* VEX_LEN_0F3A20_P_2 */ { - /* VEX_W_0FEB_P_2 */ - { "vpor", { XM, Vex, EXx }, 0 }, + { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 }, }, + + /* VEX_LEN_0F3A21_P_2 */ { - /* VEX_W_0FEC_P_2 */ - { "vpaddsb", { XM, Vex, EXx }, 0 }, + { "vinsertps", { XM, Vex128, EXd, Ib }, 0 }, }, + + /* VEX_LEN_0F3A22_P_2 */ { - /* VEX_W_0FED_P_2 */ - { "vpaddsw", { XM, Vex, EXx }, 0 }, + { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 }, }, + + /* VEX_LEN_0F3A30_P_2 */ { - /* VEX_W_0FEE_P_2 */ - { "vpmaxsw", { XM, Vex, EXx }, 0 }, + { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) }, }, + + /* VEX_LEN_0F3A31_P_2 */ { - /* VEX_W_0FEF_P_2 */ - { "vpxor", { XM, Vex, EXx }, 0 }, + { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) }, }, + + /* VEX_LEN_0F3A32_P_2 */ { - /* VEX_W_0FF0_P_3_M_0 */ - { "vlddqu", { XM, M }, 0 }, + { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) }, }, + + /* VEX_LEN_0F3A33_P_2 */ { - /* VEX_W_0FF1_P_2 */ - { "vpsllw", { XM, Vex, EXxmm }, 0 }, + { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) }, }, + + /* VEX_LEN_0F3A38_P_2 */ { - /* VEX_W_0FF2_P_2 */ - { "vpslld", { XM, Vex, EXxmm }, 0 }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F3A38_P_2) }, }, + + /* VEX_LEN_0F3A39_P_2 */ { - /* VEX_W_0FF3_P_2 */ - { "vpsllq", { XM, Vex, EXxmm }, 0 }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F3A39_P_2) }, }, + + /* VEX_LEN_0F3A41_P_2 */ { - /* VEX_W_0FF4_P_2 */ - { "vpmuludq", { XM, Vex, EXx }, 0 }, + { "vdppd", { XM, Vex128, EXx, Ib }, 0 }, }, + + /* VEX_LEN_0F3A46_P_2 */ { - /* VEX_W_0FF5_P_2 */ - { "vpmaddwd", { XM, Vex, EXx }, 0 }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F3A46_P_2) }, }, + + /* VEX_LEN_0F3A60_P_2 */ { - /* VEX_W_0FF6_P_2 */ - { "vpsadbw", { XM, Vex, EXx }, 0 }, + { "vpcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 }, }, + + /* VEX_LEN_0F3A61_P_2 */ { - /* VEX_W_0FF7_P_2 */ - { "vmaskmovdqu", { XM, XS }, 0 }, + { "vpcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 }, }, + + /* VEX_LEN_0F3A62_P_2 */ { - /* VEX_W_0FF8_P_2 */ - { "vpsubb", { XM, Vex, EXx }, 0 }, + { "vpcmpistrm", { XM, EXx, Ib }, 0 }, }, + + /* VEX_LEN_0F3A63_P_2 */ { - /* VEX_W_0FF9_P_2 */ - { "vpsubw", { XM, Vex, EXx }, 0 }, + { "vpcmpistri", { XM, EXx, Ib }, 0 }, }, + + /* VEX_LEN_0F3A6A_P_2 */ { - /* VEX_W_0FFA_P_2 */ - { "vpsubd", { XM, Vex, EXx }, 0 }, + { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, }, + + /* VEX_LEN_0F3A6B_P_2 */ { - /* VEX_W_0FFB_P_2 */ - { "vpsubq", { XM, Vex, EXx }, 0 }, + { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, }, + + /* VEX_LEN_0F3A6E_P_2 */ { - /* VEX_W_0FFC_P_2 */ - { "vpaddb", { XM, Vex, EXx }, 0 }, + { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, }, + + /* VEX_LEN_0F3A6F_P_2 */ { - /* VEX_W_0FFD_P_2 */ - { "vpaddw", { XM, Vex, EXx }, 0 }, + { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, }, + + /* VEX_LEN_0F3A7A_P_2 */ { - /* VEX_W_0FFE_P_2 */ - { "vpaddd", { XM, Vex, EXx }, 0 }, + { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, }, + + /* VEX_LEN_0F3A7B_P_2 */ { - /* VEX_W_0F3800_P_2 */ - { "vpshufb", { XM, Vex, EXx }, 0 }, + { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, }, + + /* VEX_LEN_0F3A7E_P_2 */ { - /* VEX_W_0F3801_P_2 */ - { "vphaddw", { XM, Vex, EXx }, 0 }, + { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, }, + + /* VEX_LEN_0F3A7F_P_2 */ { - /* VEX_W_0F3802_P_2 */ - { "vphaddd", { XM, Vex, EXx }, 0 }, + { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, }, + + /* VEX_LEN_0F3ADF_P_2 */ { - /* VEX_W_0F3803_P_2 */ - { "vphaddsw", { XM, Vex, EXx }, 0 }, + { "vaeskeygenassist", { XM, EXx, Ib }, 0 }, }, + + /* VEX_LEN_0F3AF0_P_3 */ { - /* VEX_W_0F3804_P_2 */ - { "vpmaddubsw", { XM, Vex, EXx }, 0 }, + { "rorxS", { Gdq, Edq, Ib }, 0 }, }, + + /* VEX_LEN_0FXOP_08_CC */ { - /* VEX_W_0F3805_P_2 */ - { "vphsubw", { XM, Vex, EXx }, 0 }, + { "vpcomb", { XM, Vex128, EXx, VPCOM }, 0 }, }, + + /* VEX_LEN_0FXOP_08_CD */ { - /* VEX_W_0F3806_P_2 */ - { "vphsubd", { XM, Vex, EXx }, 0 }, + { "vpcomw", { XM, Vex128, EXx, VPCOM }, 0 }, }, + + /* VEX_LEN_0FXOP_08_CE */ { - /* VEX_W_0F3807_P_2 */ - { "vphsubsw", { XM, Vex, EXx }, 0 }, + { "vpcomd", { XM, Vex128, EXx, VPCOM }, 0 }, }, + + /* VEX_LEN_0FXOP_08_CF */ { - /* VEX_W_0F3808_P_2 */ - { "vpsignb", { XM, Vex, EXx }, 0 }, + { "vpcomq", { XM, Vex128, EXx, VPCOM }, 0 }, }, + + /* VEX_LEN_0FXOP_08_EC */ { - /* VEX_W_0F3809_P_2 */ - { "vpsignw", { XM, Vex, EXx }, 0 }, + { "vpcomub", { XM, Vex128, EXx, VPCOM }, 0 }, }, + + /* VEX_LEN_0FXOP_08_ED */ { - /* VEX_W_0F380A_P_2 */ - { "vpsignd", { XM, Vex, EXx }, 0 }, + { "vpcomuw", { XM, Vex128, EXx, VPCOM }, 0 }, }, + + /* VEX_LEN_0FXOP_08_EE */ { - /* VEX_W_0F380B_P_2 */ - { "vpmulhrsw", { XM, Vex, EXx }, 0 }, + { "vpcomud", { XM, Vex128, EXx, VPCOM }, 0 }, }, + + /* VEX_LEN_0FXOP_08_EF */ { - /* VEX_W_0F380C_P_2 */ - { "vpermilps", { XM, Vex, EXx }, 0 }, + { "vpcomuq", { XM, Vex128, EXx, VPCOM }, 0 }, }, + + /* VEX_LEN_0FXOP_09_80 */ { - /* VEX_W_0F380D_P_2 */ - { "vpermilpd", { XM, Vex, EXx }, 0 }, + { "vfrczps", { XM, EXxmm }, 0 }, + { "vfrczps", { XM, EXymmq }, 0 }, }, + + /* VEX_LEN_0FXOP_09_81 */ { - /* VEX_W_0F380E_P_2 */ - { "vtestps", { XM, EXx }, 0 }, + { "vfrczpd", { XM, EXxmm }, 0 }, + { "vfrczpd", { XM, EXymmq }, 0 }, }, +}; + +#include "i386-dis-evex-len.h" + +static const struct dis386 vex_w_table[][2] = { { - /* VEX_W_0F380F_P_2 */ - { "vtestpd", { XM, EXx }, 0 }, + /* VEX_W_0F41_P_0_LEN_1 */ + { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) }, + { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) }, }, { - /* VEX_W_0F3816_P_2 */ - { "vpermps", { XM, Vex, EXx }, 0 }, + /* VEX_W_0F41_P_2_LEN_1 */ + { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) }, + { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) } }, { - /* VEX_W_0F3817_P_2 */ - { "vptest", { XM, EXx }, 0 }, + /* VEX_W_0F42_P_0_LEN_1 */ + { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) }, + { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) }, }, { - /* VEX_W_0F3818_P_2 */ - { "vbroadcastss", { XM, EXxmm_md }, 0 }, + /* VEX_W_0F42_P_2_LEN_1 */ + { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) }, + { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) }, }, { - /* VEX_W_0F3819_P_2 */ - { "vbroadcastsd", { XM, EXxmm_mq }, 0 }, + /* VEX_W_0F44_P_0_LEN_0 */ + { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) }, + { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) }, }, { - /* VEX_W_0F381A_P_2_M_0 */ - { "vbroadcastf128", { XM, Mxmm }, 0 }, + /* VEX_W_0F44_P_2_LEN_0 */ + { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) }, + { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) }, }, { - /* VEX_W_0F381C_P_2 */ - { "vpabsb", { XM, EXx }, 0 }, + /* VEX_W_0F45_P_0_LEN_1 */ + { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) }, + { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) }, }, { - /* VEX_W_0F381D_P_2 */ - { "vpabsw", { XM, EXx }, 0 }, + /* VEX_W_0F45_P_2_LEN_1 */ + { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) }, + { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) }, }, { - /* VEX_W_0F381E_P_2 */ - { "vpabsd", { XM, EXx }, 0 }, + /* VEX_W_0F46_P_0_LEN_1 */ + { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) }, + { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) }, }, { - /* VEX_W_0F3820_P_2 */ - { "vpmovsxbw", { XM, EXxmmq }, 0 }, + /* VEX_W_0F46_P_2_LEN_1 */ + { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) }, + { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) }, }, { - /* VEX_W_0F3821_P_2 */ - { "vpmovsxbd", { XM, EXxmmqd }, 0 }, + /* VEX_W_0F47_P_0_LEN_1 */ + { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) }, + { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) }, }, { - /* VEX_W_0F3822_P_2 */ - { "vpmovsxbq", { XM, EXxmmdw }, 0 }, + /* VEX_W_0F47_P_2_LEN_1 */ + { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) }, + { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) }, }, { - /* VEX_W_0F3823_P_2 */ - { "vpmovsxwd", { XM, EXxmmq }, 0 }, + /* VEX_W_0F4A_P_0_LEN_1 */ + { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) }, + { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) }, }, { - /* VEX_W_0F3824_P_2 */ - { "vpmovsxwq", { XM, EXxmmqd }, 0 }, + /* VEX_W_0F4A_P_2_LEN_1 */ + { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) }, + { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) }, }, { - /* VEX_W_0F3825_P_2 */ - { "vpmovsxdq", { XM, EXxmmq }, 0 }, + /* VEX_W_0F4B_P_0_LEN_1 */ + { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) }, + { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) }, }, { - /* VEX_W_0F3828_P_2 */ - { "vpmuldq", { XM, Vex, EXx }, 0 }, + /* VEX_W_0F4B_P_2_LEN_1 */ + { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) }, }, { - /* VEX_W_0F3829_P_2 */ - { "vpcmpeqq", { XM, Vex, EXx }, 0 }, + /* VEX_W_0F90_P_0_LEN_0 */ + { "kmovw", { MaskG, MaskE }, 0 }, + { "kmovq", { MaskG, MaskE }, 0 }, }, { - /* VEX_W_0F382A_P_2_M_0 */ - { "vmovntdqa", { XM, Mx }, 0 }, + /* VEX_W_0F90_P_2_LEN_0 */ + { "kmovb", { MaskG, MaskBDE }, 0 }, + { "kmovd", { MaskG, MaskBDE }, 0 }, }, { - /* VEX_W_0F382B_P_2 */ - { "vpackusdw", { XM, Vex, EXx }, 0 }, + /* VEX_W_0F91_P_0_LEN_0 */ + { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) }, + { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) }, }, { - /* VEX_W_0F382C_P_2_M_0 */ - { "vmaskmovps", { XM, Vex, Mx }, 0 }, + /* VEX_W_0F91_P_2_LEN_0 */ + { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) }, + { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) }, }, { - /* VEX_W_0F382D_P_2_M_0 */ - { "vmaskmovpd", { XM, Vex, Mx }, 0 }, + /* VEX_W_0F92_P_0_LEN_0 */ + { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) }, }, { - /* VEX_W_0F382E_P_2_M_0 */ - { "vmaskmovps", { Mx, Vex, XM }, 0 }, + /* VEX_W_0F92_P_2_LEN_0 */ + { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) }, }, { - /* VEX_W_0F382F_P_2_M_0 */ - { "vmaskmovpd", { Mx, Vex, XM }, 0 }, + /* VEX_W_0F93_P_0_LEN_0 */ + { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) }, }, { - /* VEX_W_0F3830_P_2 */ - { "vpmovzxbw", { XM, EXxmmq }, 0 }, + /* VEX_W_0F93_P_2_LEN_0 */ + { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) }, }, { - /* VEX_W_0F3831_P_2 */ - { "vpmovzxbd", { XM, EXxmmqd }, 0 }, + /* VEX_W_0F98_P_0_LEN_0 */ + { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) }, + { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) }, }, { - /* VEX_W_0F3832_P_2 */ - { "vpmovzxbq", { XM, EXxmmdw }, 0 }, + /* VEX_W_0F98_P_2_LEN_0 */ + { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) }, + { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) }, }, { - /* VEX_W_0F3833_P_2 */ - { "vpmovzxwd", { XM, EXxmmq }, 0 }, + /* VEX_W_0F99_P_0_LEN_0 */ + { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) }, + { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) }, }, { - /* VEX_W_0F3834_P_2 */ - { "vpmovzxwq", { XM, EXxmmqd }, 0 }, + /* VEX_W_0F99_P_2_LEN_0 */ + { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) }, + { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) }, }, { - /* VEX_W_0F3835_P_2 */ - { "vpmovzxdq", { XM, EXxmmq }, 0 }, + /* VEX_W_0F380C_P_2 */ + { "vpermilps", { XM, Vex, EXx }, 0 }, }, { - /* VEX_W_0F3836_P_2 */ - { "vpermd", { XM, Vex, EXx }, 0 }, + /* VEX_W_0F380D_P_2 */ + { "vpermilpd", { XM, Vex, EXx }, 0 }, }, { - /* VEX_W_0F3837_P_2 */ - { "vpcmpgtq", { XM, Vex, EXx }, 0 }, + /* VEX_W_0F380E_P_2 */ + { "vtestps", { XM, EXx }, 0 }, }, { - /* VEX_W_0F3838_P_2 */ - { "vpminsb", { XM, Vex, EXx }, 0 }, + /* VEX_W_0F380F_P_2 */ + { "vtestpd", { XM, EXx }, 0 }, }, { - /* VEX_W_0F3839_P_2 */ - { "vpminsd", { XM, Vex, EXx }, 0 }, + /* VEX_W_0F3816_P_2 */ + { "vpermps", { XM, Vex, EXx }, 0 }, }, { - /* VEX_W_0F383A_P_2 */ - { "vpminuw", { XM, Vex, EXx }, 0 }, + /* VEX_W_0F3818_P_2 */ + { "vbroadcastss", { XM, EXxmm_md }, 0 }, }, { - /* VEX_W_0F383B_P_2 */ - { "vpminud", { XM, Vex, EXx }, 0 }, + /* VEX_W_0F3819_P_2 */ + { "vbroadcastsd", { XM, EXxmm_mq }, 0 }, }, { - /* VEX_W_0F383C_P_2 */ - { "vpmaxsb", { XM, Vex, EXx }, 0 }, + /* VEX_W_0F381A_P_2_M_0 */ + { "vbroadcastf128", { XM, Mxmm }, 0 }, }, { - /* VEX_W_0F383D_P_2 */ - { "vpmaxsd", { XM, Vex, EXx }, 0 }, + /* VEX_W_0F382C_P_2_M_0 */ + { "vmaskmovps", { XM, Vex, Mx }, 0 }, }, { - /* VEX_W_0F383E_P_2 */ - { "vpmaxuw", { XM, Vex, EXx }, 0 }, + /* VEX_W_0F382D_P_2_M_0 */ + { "vmaskmovpd", { XM, Vex, Mx }, 0 }, }, { - /* VEX_W_0F383F_P_2 */ - { "vpmaxud", { XM, Vex, EXx }, 0 }, + /* VEX_W_0F382E_P_2_M_0 */ + { "vmaskmovps", { Mx, Vex, XM }, 0 }, }, { - /* VEX_W_0F3840_P_2 */ - { "vpmulld", { XM, Vex, EXx }, 0 }, + /* VEX_W_0F382F_P_2_M_0 */ + { "vmaskmovpd", { Mx, Vex, XM }, 0 }, }, { - /* VEX_W_0F3841_P_2 */ - { "vphminposuw", { XM, EXx }, 0 }, + /* VEX_W_0F3836_P_2 */ + { "vpermd", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F3846_P_2 */ @@ -11520,24 +10124,8 @@ static const struct dis386 vex_w_table[][2] = { { "vpbroadcastw", { XM, EXxmm_mw }, 0 }, }, { - /* VEX_W_0F38DB_P_2 */ - { "vaesimc", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F38DC_P_2 */ - { "vaesenc", { XM, Vex128, EXx }, 0 }, - }, - { - /* VEX_W_0F38DD_P_2 */ - { "vaesenclast", { XM, Vex128, EXx }, 0 }, - }, - { - /* VEX_W_0F38DE_P_2 */ - { "vaesdec", { XM, Vex128, EXx }, 0 }, - }, - { - /* VEX_W_0F38DF_P_2 */ - { "vaesdeclast", { XM, Vex128, EXx }, 0 }, + /* VEX_W_0F38CF_P_2 */ + { "vgf2p8mulb", { XM, Vex, EXx }, 0 }, }, { /* VEX_W_0F3A00_P_2 */ @@ -11565,46 +10153,6 @@ static const struct dis386 vex_w_table[][2] = { /* VEX_W_0F3A06_P_2 */ { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 }, }, - { - /* VEX_W_0F3A08_P_2 */ - { "vroundps", { XM, EXx, Ib }, 0 }, - }, - { - /* VEX_W_0F3A09_P_2 */ - { "vroundpd", { XM, EXx, Ib }, 0 }, - }, - { - /* VEX_W_0F3A0A_P_2 */ - { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 }, - }, - { - /* VEX_W_0F3A0B_P_2 */ - { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 }, - }, - { - /* VEX_W_0F3A0C_P_2 */ - { "vblendps", { XM, Vex, EXx, Ib }, 0 }, - }, - { - /* VEX_W_0F3A0D_P_2 */ - { "vblendpd", { XM, Vex, EXx, Ib }, 0 }, - }, - { - /* VEX_W_0F3A0E_P_2 */ - { "vpblendw", { XM, Vex, EXx, Ib }, 0 }, - }, - { - /* VEX_W_0F3A0F_P_2 */ - { "vpalignr", { XM, Vex, EXx, Ib }, 0 }, - }, - { - /* VEX_W_0F3A14_P_2 */ - { "vpextrb", { Edqb, XM, Ib }, 0 }, - }, - { - /* VEX_W_0F3A15_P_2 */ - { "vpextrw", { Edqw, XM, Ib }, 0 }, - }, { /* VEX_W_0F3A18_P_2 */ { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 }, @@ -11613,14 +10161,6 @@ static const struct dis386 vex_w_table[][2] = { /* VEX_W_0F3A19_P_2 */ { "vextractf128", { EXxmm, XM, Ib }, 0 }, }, - { - /* VEX_W_0F3A20_P_2 */ - { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 }, - }, - { - /* VEX_W_0F3A21_P_2 */ - { "vinsertps", { XM, Vex128, EXd, Ib }, 0 }, - }, { /* VEX_W_0F3A30_P_2_LEN_0 */ { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) }, @@ -11649,22 +10189,6 @@ static const struct dis386 vex_w_table[][2] = { /* VEX_W_0F3A39_P_2 */ { "vextracti128", { EXxmm, XM, Ib }, 0 }, }, - { - /* VEX_W_0F3A40_P_2 */ - { "vdpps", { XM, Vex, EXx, Ib }, 0 }, - }, - { - /* VEX_W_0F3A41_P_2 */ - { "vdppd", { XM, Vex128, EXx, Ib }, 0 }, - }, - { - /* VEX_W_0F3A42_P_2 */ - { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 }, - }, - { - /* VEX_W_0F3A44_P_2 */ - { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL }, 0 }, - }, { /* VEX_W_0F3A46_P_2 */ { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 }, @@ -11692,28 +10216,17 @@ static const struct dis386 vex_w_table[][2] = { { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 }, }, { - /* VEX_W_0F3A60_P_2 */ - { "vpcmpestrm", { XM, EXx, Ib }, 0 }, - }, - { - /* VEX_W_0F3A61_P_2 */ - { "vpcmpestri", { XM, EXx, Ib }, 0 }, - }, - { - /* VEX_W_0F3A62_P_2 */ - { "vpcmpistrm", { XM, EXx, Ib }, 0 }, - }, - { - /* VEX_W_0F3A63_P_2 */ - { "vpcmpistri", { XM, EXx, Ib }, 0 }, + /* VEX_W_0F3ACE_P_2 */ + { Bad_Opcode }, + { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 }, }, { - /* VEX_W_0F3ADF_P_2 */ - { "vaeskeygenassist", { XM, EXx, Ib }, 0 }, + /* VEX_W_0F3ACF_P_2 */ + { Bad_Opcode }, + { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, 0 }, }, -#define NEED_VEX_W_TABLE -#include "i386-dis-evex.h" -#undef NEED_VEX_W_TABLE + +#include "i386-dis-evex-w.h" }; static const struct dis386 mod_table[][2] = { @@ -11761,13 +10274,13 @@ static const struct dis386 mod_table[][2] = { }, { /* MOD_0F01_REG_5 */ - { Bad_Opcode }, - { RM_TABLE (RM_0F01_REG_5) }, + { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) }, + { RM_TABLE (RM_0F01_REG_5_MOD_3) }, }, { /* MOD_0F01_REG_7 */ { "invlpg", { Mb }, 0 }, - { RM_TABLE (RM_0F01_REG_7) }, + { RM_TABLE (RM_0F01_REG_7_MOD_3) }, }, { /* MOD_0F12_PREFIX_0 */ @@ -11821,18 +10334,28 @@ static const struct dis386 mod_table[][2] = { }, { /* MOD_0F1A_PREFIX_0 */ - { "bndldx", { Gbnd, Ev_bnd }, 0 }, + { "bndldx", { Gbnd, Mv_bnd }, 0 }, { "nopQ", { Ev }, 0 }, }, { /* MOD_0F1B_PREFIX_0 */ - { "bndstx", { Ev_bnd, Gbnd }, 0 }, + { "bndstx", { Mv_bnd, Gbnd }, 0 }, { "nopQ", { Ev }, 0 }, }, { /* MOD_0F1B_PREFIX_1 */ - { "bndmk", { Gbnd, Ev_bnd }, 0 }, + { "bndmk", { Gbnd, Mv_bnd }, 0 }, + { "nopQ", { Ev }, 0 }, + }, + { + /* MOD_0F1C_PREFIX_0 */ + { REG_TABLE (REG_0F1C_P_0_MOD_0) }, + { "nopQ", { Ev }, 0 }, + }, + { + /* MOD_0F1E_PREFIX_1 */ { "nopQ", { Ev }, 0 }, + { REG_TABLE (REG_0F1E_P_1_MOD_3) }, }, { /* MOD_0F24 */ @@ -11918,42 +10441,42 @@ static const struct dis386 mod_table[][2] = { { /* MOD_0FAE_REG_0 */ { "fxsave", { FXSAVE }, 0 }, - { PREFIX_TABLE (PREFIX_0FAE_REG_0) }, + { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) }, }, { /* MOD_0FAE_REG_1 */ { "fxrstor", { FXSAVE }, 0 }, - { PREFIX_TABLE (PREFIX_0FAE_REG_1) }, + { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) }, }, { /* MOD_0FAE_REG_2 */ { "ldmxcsr", { Md }, 0 }, - { PREFIX_TABLE (PREFIX_0FAE_REG_2) }, + { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) }, }, { /* MOD_0FAE_REG_3 */ { "stmxcsr", { Md }, 0 }, - { PREFIX_TABLE (PREFIX_0FAE_REG_3) }, + { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) }, }, { /* MOD_0FAE_REG_4 */ - { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) }, - { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) }, + { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) }, + { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) }, }, { /* MOD_0FAE_REG_5 */ - { "xrstor", { FXSAVE }, 0 }, - { RM_TABLE (RM_0FAE_REG_5) }, + { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) }, + { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) }, }, { /* MOD_0FAE_REG_6 */ - { PREFIX_TABLE (PREFIX_0FAE_REG_6) }, - { RM_TABLE (RM_0FAE_REG_6) }, + { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) }, + { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) }, }, { /* MOD_0FAE_REG_7 */ - { PREFIX_TABLE (PREFIX_0FAE_REG_7) }, - { RM_TABLE (RM_0FAE_REG_7) }, + { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) }, + { RM_TABLE (RM_0FAE_REG_7_MOD_3) }, }, { /* MOD_0FB2 */ @@ -11969,7 +10492,7 @@ static const struct dis386 mod_table[][2] = { }, { /* MOD_0FC3 */ - { PREFIX_TABLE (PREFIX_MOD_0_0FC3) }, + { PREFIX_TABLE (PREFIX_0FC3_MOD_0) }, }, { /* MOD_0FC7_REG_3 */ @@ -11985,13 +10508,13 @@ static const struct dis386 mod_table[][2] = { }, { /* MOD_0FC7_REG_6 */ - { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) }, - { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) } + { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) }, + { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) } }, { /* MOD_0FC7_REG_7 */ { "vmptrst", { Mq }, 0 }, - { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) } + { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) } }, { /* MOD_0FD7 */ @@ -12010,6 +10533,30 @@ static const struct dis386 mod_table[][2] = { /* MOD_0F382A_PREFIX_2 */ { "movntdqa", { XM, Mx }, 0 }, }, + { + /* MOD_0F38F5_PREFIX_2 */ + { "wrussK", { M, Gdq }, PREFIX_OPCODE }, + }, + { + /* MOD_0F38F6_PREFIX_0 */ + { "wrssK", { M, Gdq }, PREFIX_OPCODE }, + }, + { + /* MOD_0F38F8_PREFIX_1 */ + { "enqcmds", { Gva, M }, PREFIX_OPCODE }, + }, + { + /* MOD_0F38F8_PREFIX_2 */ + { "movdir64b", { Gva, M }, PREFIX_OPCODE }, + }, + { + /* MOD_0F38F8_PREFIX_3 */ + { "enqcmd", { Gva, M }, PREFIX_OPCODE }, + }, + { + /* MOD_0F38F9_PREFIX_0 */ + { "movdiri", { Ev, Gv }, PREFIX_OPCODE }, + }, { /* MOD_62_32BIT */ { "bound{S|}", { Gv, Ma }, 0 }, @@ -12045,7 +10592,7 @@ static const struct dis386 mod_table[][2] = { }, { /* MOD_VEX_0F2B */ - { VEX_W_TABLE (VEX_W_0F2B_M_0) }, + { "vmovntpX", { Mx, XM }, 0 }, }, { /* MOD_VEX_W_0_0F41_P_0_LEN_1 */ @@ -12205,7 +10752,7 @@ static const struct dis386 mod_table[][2] = { { /* MOD_VEX_0F50 */ { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F50_M_0) }, + { "vmovmskpX", { Gdq, XS }, 0 }, }, { /* MOD_VEX_0F71_REG_2 */ @@ -12288,14 +10835,9 @@ static const struct dis386 mod_table[][2] = { { "kmovb", { MaskG, Rdq }, 0 }, }, { - /* MOD_VEX_W_0_0F92_P_3_LEN_0 */ - { Bad_Opcode }, - { "kmovd", { MaskG, Rdq }, 0 }, - }, - { - /* MOD_VEX_W_1_0F92_P_3_LEN_0 */ + /* MOD_VEX_0F92_P_3_LEN_0 */ { Bad_Opcode }, - { "kmovq", { MaskG, Rdq }, 0 }, + { "kmovK", { MaskG, Rdq }, 0 }, }, { /* MOD_VEX_W_0_0F93_P_0_LEN_0 */ @@ -12308,14 +10850,9 @@ static const struct dis386 mod_table[][2] = { { "kmovb", { Gdq, MaskR }, 0 }, }, { - /* MOD_VEX_W_0_0F93_P_3_LEN_0 */ - { Bad_Opcode }, - { "kmovd", { Gdq, MaskR }, 0 }, - }, - { - /* MOD_VEX_W_1_0F93_P_3_LEN_0 */ + /* MOD_VEX_0F93_P_3_LEN_0 */ { Bad_Opcode }, - { "kmovq", { Gdq, MaskR }, 0 }, + { "kmovK", { Gdq, MaskR }, 0 }, }, { /* MOD_VEX_W_0_0F98_P_0_LEN_0 */ @@ -12368,15 +10905,15 @@ static const struct dis386 mod_table[][2] = { { /* MOD_VEX_0FD7_PREFIX_2 */ { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) }, + { "vpmovmskb", { Gdq, XS }, 0 }, }, { /* MOD_VEX_0FE7_PREFIX_2 */ - { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) }, + { "vmovntdq", { Mx, XM }, 0 }, }, { /* MOD_VEX_0FF0_PREFIX_3 */ - { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) }, + { "vlddqu", { XM, M }, 0 }, }, { /* MOD_VEX_0F381A_PREFIX_2 */ @@ -12384,7 +10921,7 @@ static const struct dis386 mod_table[][2] = { }, { /* MOD_VEX_0F382A_PREFIX_2 */ - { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) }, + { "vmovntdqa", { XM, Mx }, 0 }, }, { /* MOD_VEX_0F382C_PREFIX_2 */ @@ -12454,9 +10991,8 @@ static const struct dis386 mod_table[][2] = { { Bad_Opcode }, { "kshiftlq", { MaskG, MaskR, Ib }, 0 }, }, -#define NEED_MOD_TABLE -#include "i386-dis-evex.h" -#undef NEED_MOD_TABLE + +#include "i386-dis-evex-mod.h" }; static const struct dis386 rm_table[][8] = { @@ -12466,15 +11002,16 @@ static const struct dis386 rm_table[][8] = { }, { /* RM_C7_REG_7 */ - { "xbeginT", { Skip_MODRM, Jv }, 0 }, + { "xbeginT", { Skip_MODRM, Jdqw }, 0 }, }, { /* RM_0F01_REG_0 */ - { Bad_Opcode }, + { "enclv", { Skip_MODRM }, 0 }, { "vmcall", { Skip_MODRM }, 0 }, { "vmlaunch", { Skip_MODRM }, 0 }, { "vmresume", { Skip_MODRM }, 0 }, { "vmxoff", { Skip_MODRM }, 0 }, + { "pconfig", { Skip_MODRM }, 0 }, }, { /* RM_0F01_REG_1 */ @@ -12501,7 +11038,7 @@ static const struct dis386 rm_table[][8] = { { /* RM_0F01_REG_3 */ { "vmrun", { Skip_MODRM }, 0 }, - { "vmmcall", { Skip_MODRM }, 0 }, + { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) }, { "vmload", { Skip_MODRM }, 0 }, { "vmsave", { Skip_MODRM }, 0 }, { "stgi", { Skip_MODRM }, 0 }, @@ -12510,10 +11047,10 @@ static const struct dis386 rm_table[][8] = { { "invlpga", { Skip_MODRM }, 0 }, }, { - /* RM_0F01_REG_5 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + /* RM_0F01_REG_5_MOD_3 */ + { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) }, + { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) }, + { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -12521,23 +11058,31 @@ static const struct dis386 rm_table[][8] = { { "wrpkru", { Skip_MODRM }, 0 }, }, { - /* RM_0F01_REG_7 */ + /* RM_0F01_REG_7_MOD_3 */ { "swapgs", { Skip_MODRM }, 0 }, { "rdtscp", { Skip_MODRM }, 0 }, - { "monitorx", { { OP_Monitor, 0 } }, 0 }, - { "mwaitx", { { OP_Mwaitx, 0 } }, 0 }, + { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) }, + { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) }, { "clzero", { Skip_MODRM }, 0 }, + { "rdpru", { Skip_MODRM }, 0 }, }, { - /* RM_0FAE_REG_5 */ - { "lfence", { Skip_MODRM }, 0 }, + /* RM_0F1E_P_1_MOD_3_REG_7 */ + { "nopQ", { Ev }, 0 }, + { "nopQ", { Ev }, 0 }, + { "endbr64", { Skip_MODRM }, PREFIX_OPCODE }, + { "endbr32", { Skip_MODRM }, PREFIX_OPCODE }, + { "nopQ", { Ev }, 0 }, + { "nopQ", { Ev }, 0 }, + { "nopQ", { Ev }, 0 }, + { "nopQ", { Ev }, 0 }, }, { - /* RM_0FAE_REG_6 */ + /* RM_0FAE_REG_6_MOD_3 */ { "mfence", { Skip_MODRM }, 0 }, }, { - /* RM_0FAE_REG_7 */ + /* RM_0FAE_REG_7_MOD_3 */ { "sfence", { Skip_MODRM }, 0 }, }, @@ -12551,6 +11096,10 @@ static const struct dis386 rm_table[][8] = { #define XACQUIRE_PREFIX (0xf2 | 0x200) #define XRELEASE_PREFIX (0xf3 | 0x400) #define BND_PREFIX (0xf2 | 0x400) +#define NOTRACK_PREFIX (0x3e | 0x100) + +/* Remember if the current op is a jump instruction. */ +static bfd_boolean op_is_jump = FALSE; static int ckprefix (void) @@ -12769,6 +11318,8 @@ prefix_name (int pref, int sizeflag) return "xrelease"; case BND_PREFIX: return "bnd"; + case NOTRACK_PREFIX: + return "notrack"; default: return NULL; } @@ -12799,7 +11350,7 @@ static char scale_char; enum x86_64_isa { - amd64 = 0, + amd64 = 1, intel64 }; @@ -12990,6 +11541,29 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) dp = &vex_len_table[dp->op[1].bytemode][vindex]; break; + case USE_EVEX_LEN_TABLE: + if (!vex.evex) + abort (); + + switch (vex.length) + { + case 128: + vindex = 0; + break; + case 256: + vindex = 1; + break; + case 512: + vindex = 2; + break; + default: + abort (); + break; + } + + dp = &evex_len_table[dp->op[1].bytemode][vindex]; + break; + case USE_XOP_8F_TABLE: FETCH_DATA (info, codep + 3); /* All bits in the REX prefix are ignored. */ @@ -13018,18 +11592,16 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) rex |= REX_W; vex.register_specifier = (~(*codep >> 3)) & 0xf; - if (address_mode != mode_64bit - && vex.register_specifier > 0x7) + if (address_mode != mode_64bit) { - dp = &bad_opcode; - return dp; + /* In 16/32-bit mode REX_B is silently ignored. */ + rex &= ~REX_B; } vex.length = (*codep & 0x4) ? 256 : 128; switch ((*codep & 0x3)) { case 0: - vex.prefix = 0; break; case 1: vex.prefix = DATA_PREFIX_OPCODE; @@ -13081,21 +11653,19 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) { if (vex.w) rex |= REX_W; - vex.register_specifier = (~(*codep >> 3)) & 0xf; } else { /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit is ignored, other REX bits are 0 and the highest bit in - VEX.vvvv is also ignored. */ + VEX.vvvv is also ignored (but we mustn't clear it here). */ rex = 0; - vex.register_specifier = (~(*codep >> 3)) & 0x7; } + vex.register_specifier = (~(*codep >> 3)) & 0xf; vex.length = (*codep & 0x4) ? 256 : 128; switch ((*codep & 0x3)) { case 0: - vex.prefix = 0; break; case 1: vex.prefix = DATA_PREFIX_OPCODE; @@ -13113,8 +11683,8 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) vindex = *codep++; dp = &vex_table[vex_table_index][vindex]; end_codep = codep; - /* There is no MODRM byte for VEX [82|77]. */ - if (vindex != 0x77 && vindex != 0x82) + /* There is no MODRM byte for VEX0F 77. */ + if (vex_table_index != VEX_0F || vindex != 0x77) { FETCH_DATA (info, codep + 1); modrm.mod = (*codep >> 6) & 3; @@ -13133,12 +11703,10 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in VEX.vvvv is 1. */ vex.register_specifier = (~(*codep >> 3)) & 0xf; - vex.w = 0; vex.length = (*codep & 0x4) ? 256 : 128; switch ((*codep & 0x3)) { case 0: - vex.prefix = 0; break; case 1: vex.prefix = DATA_PREFIX_OPCODE; @@ -13156,8 +11724,8 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) vindex = *codep++; dp = &vex_table[dp->op[1].bytemode][vindex]; end_codep = codep; - /* There is no MODRM byte for VEX [82|77]. */ - if (vindex != 0x77 && vindex != 0x82) + /* There is no MODRM byte for VEX 77. */ + if (vindex != 0x77) { FETCH_DATA (info, codep + 1); modrm.mod = (*codep >> 6) & 3; @@ -13205,14 +11773,6 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) rex |= REX_W; vex.register_specifier = (~(*codep >> 3)) & 0xf; - if (address_mode != mode_64bit) - { - /* In 16/32-bit mode silently ignore following bits. */ - rex &= ~REX_B; - vex.r = 1; - vex.v = 1; - vex.register_specifier &= 0x7; - } /* The U bit. */ if (!(*codep & 0x4)) @@ -13221,7 +11781,6 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) switch ((*codep & 0x3)) { case 0: - vex.prefix = 0; break; case 1: vex.prefix = DATA_PREFIX_OPCODE; @@ -13245,6 +11804,14 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) vex.mask_register_specifier = *codep & 0x7; vex.zeroing = *codep & 0x80; + if (address_mode != mode_64bit) + { + /* In 16/32-bit mode silently ignore following bits. */ + rex &= ~REX_B; + vex.r = 1; + vex.v = 1; + } + need_vex = 1; need_vex_reg = 1; codep++; @@ -13571,7 +12138,7 @@ print_insn (bfd_vma pc, disassemble_info *info) need_vex = 0; need_vex_reg = 0; vex_w_done = 0; - vex.evex = 0; + memset (&vex, 0, sizeof (vex)); if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) { @@ -13608,6 +12175,58 @@ print_insn (bfd_vma pc, disassemble_info *info) } } + /* Clear instruction information. */ + if (the_info) + { + the_info->insn_info_valid = 0; + the_info->branch_delay_insns = 0; + the_info->data_size = 0; + the_info->insn_type = dis_noninsn; + the_info->target = 0; + the_info->target2 = 0; + } + + /* Reset jump operation indicator. */ + op_is_jump = FALSE; + + { + int jump_detection = 0; + + /* Extract flags. */ + for (i = 0; i < MAX_OPERANDS; ++i) + { + if ((dp->op[i].rtn == OP_J) + || (dp->op[i].rtn == OP_indirE)) + jump_detection |= 1; + else if ((dp->op[i].rtn == BND_Fixup) + || (!dp->op[i].rtn && !dp->op[i].bytemode)) + jump_detection |= 2; + else if ((dp->op[i].bytemode == cond_jump_mode) + || (dp->op[i].bytemode == loop_jcxz_mode)) + jump_detection |= 4; + } + + /* Determine if this is a jump or branch. */ + if ((jump_detection & 0x3) == 0x3) + { + op_is_jump = TRUE; + if (jump_detection & 0x4) + the_info->insn_type = dis_condbranch; + else + the_info->insn_type = + (dp->name && !strncmp(dp->name, "call", 4)) + ? dis_jsr : dis_branch; + } + } + + /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which + are all 0s in inverted form. */ + if (need_vex && vex.register_specifier != 0) + { + (*info->fprintf_func) (info->stream, "(bad)"); + return end_codep - priv.the_buffer; + } + /* Check if the REX prefix is used. */ if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0) all_prefixes[last_rex_prefix] = 0; @@ -13713,7 +12332,19 @@ print_insn (bfd_vma pc, disassemble_info *info) if (needcomma) (*info->fprintf_func) (info->stream, ","); if (op_index[i] != -1 && !op_riprel[i]) - (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info); + { + bfd_vma target = (bfd_vma) op_address[op_index[i]]; + + if (the_info && op_is_jump) + { + the_info->insn_info_valid = 1; + the_info->branch_delay_insns = 0; + the_info->data_size = 0; + the_info->target = target; + the_info->target2 = 0; + } + (*info->print_address_func) (target, info); + } else (*info->fprintf_func) (info->stream, "%s", op_txt[i]); needcomma = 1; @@ -13786,19 +12417,19 @@ static const char *float_mem[] = { "fNsaveIC", "fNstsw", /* de */ - "fiadd", - "fimul", - "ficom", - "ficomp", - "fisub", - "fisubr", - "fidiv", - "fidivr", + "fiadd{s|}", + "fimul{s|}", + "ficom{s|}", + "ficomp{s|}", + "fisub{s|}", + "fisubr{s|}", + "fidiv{s|}", + "fidivr{s|}", /* df */ - "fild", - "fisttp", - "fist", - "fistp", + "fild{s|}", + "fisttp{s|}", + "fist{s|}", + "fistp{s|}", "fbld", "fild{ll|}", "fbstp", @@ -13883,15 +12514,15 @@ static const unsigned char float_mem_mode[] = { #define ST { OP_ST, 0 } #define STi { OP_STi, 0 } -#define FGRPd9_2 NULL, { { NULL, 0 } }, 0 -#define FGRPd9_4 NULL, { { NULL, 1 } }, 0 -#define FGRPd9_5 NULL, { { NULL, 2 } }, 0 -#define FGRPd9_6 NULL, { { NULL, 3 } }, 0 -#define FGRPd9_7 NULL, { { NULL, 4 } }, 0 -#define FGRPda_5 NULL, { { NULL, 5 } }, 0 -#define FGRPdb_4 NULL, { { NULL, 6 } }, 0 -#define FGRPde_3 NULL, { { NULL, 7 } }, 0 -#define FGRPdf_4 NULL, { { NULL, 8 } }, 0 +#define FGRPd9_2 NULL, { { NULL, 1 } }, 0 +#define FGRPd9_4 NULL, { { NULL, 2 } }, 0 +#define FGRPd9_5 NULL, { { NULL, 3 } }, 0 +#define FGRPd9_6 NULL, { { NULL, 4 } }, 0 +#define FGRPd9_7 NULL, { { NULL, 5 } }, 0 +#define FGRPda_5 NULL, { { NULL, 6 } }, 0 +#define FGRPdb_4 NULL, { { NULL, 7 } }, 0 +#define FGRPde_3 NULL, { { NULL, 8 } }, 0 +#define FGRPdf_4 NULL, { { NULL, 9 } }, 0 static const struct dis386 float_reg[][8] = { /* d8 */ @@ -13944,10 +12575,10 @@ static const struct dis386 float_reg[][8] = { { "fmul", { STi, ST }, 0 }, { Bad_Opcode }, { Bad_Opcode }, - { "fsub!M", { STi, ST }, 0 }, - { "fsubM", { STi, ST }, 0 }, - { "fdiv!M", { STi, ST }, 0 }, - { "fdivM", { STi, ST }, 0 }, + { "fsub{!M|r}", { STi, ST }, 0 }, + { "fsub{M|}", { STi, ST }, 0 }, + { "fdiv{!M|r}", { STi, ST }, 0 }, + { "fdiv{M|}", { STi, ST }, 0 }, }, /* dd */ { @@ -13966,10 +12597,10 @@ static const struct dis386 float_reg[][8] = { { "fmulp", { STi, ST }, 0 }, { Bad_Opcode }, { FGRPde_3 }, - { "fsub!Mp", { STi, ST }, 0 }, - { "fsubMp", { STi, ST }, 0 }, - { "fdiv!Mp", { STi, ST }, 0 }, - { "fdivMp", { STi, ST }, 0 }, + { "fsub{!M|r}p", { STi, ST }, 0 }, + { "fsub{M|}p", { STi, ST }, 0 }, + { "fdiv{!M|r}p", { STi, ST }, 0 }, + { "fdiv{M|}p", { STi, ST }, 0 }, }, /* df */ { @@ -13985,48 +12616,53 @@ static const struct dis386 float_reg[][8] = { }; static char *fgrps[][8] = { - /* d9_2 0 */ + /* Bad opcode 0 */ + { + "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", + }, + + /* d9_2 1 */ { "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", }, - /* d9_4 1 */ + /* d9_4 2 */ { "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", }, - /* d9_5 2 */ + /* d9_5 3 */ { "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", }, - /* d9_6 3 */ + /* d9_6 4 */ { "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", }, - /* d9_7 4 */ + /* d9_7 5 */ { "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", }, - /* da_5 5 */ + /* da_5 6 */ { "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", }, - /* db_4 6 */ + /* db_4 7 */ { "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", }, - /* de_3 7 */ + /* de_3 8 */ { "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", }, - /* df_4 8 */ + /* df_4 9 */ { "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", }, @@ -14175,7 +12811,7 @@ putop (const char *in_template, int sizeflag) case 'B': if (l == 0 && len == 1) { -case_B: + case_B: if (intel_syntax) break; if (sizeflag & SUFFIX_ALWAYS) @@ -14340,7 +12976,7 @@ case_B: SAVE_LAST (*p); break; } -case_L: + case_L: if (intel_syntax) break; if (sizeflag & SUFFIX_ALWAYS) @@ -14389,7 +13025,7 @@ case_L: case 'P': if (l == 0 && len == 1) { -case_P: + case_P: if (intel_syntax) { if ((rex & REX_W) == 0 @@ -14459,7 +13095,7 @@ case_P: case 'Q': if (l == 0 && len == 1) { -case_Q: + case_Q: if (intel_syntax && !alt) break; USED_REX (REX_W); @@ -14550,7 +13186,7 @@ case_Q: case 'S': if (l == 0 && len == 1) { -case_S: + case_S: if (intel_syntax) break; if (sizeflag & SUFFIX_ALWAYS) @@ -14612,16 +13248,7 @@ case_S: break; case 'Y': if (l == 0 && len == 1) - { - if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) - break; - if (rex & REX_W) - { - USED_REX (REX_W); - *obufp++ = 'q'; - } - break; - } + abort (); else { if (l != 1 || len != 2 || last[0] != 'X') @@ -14689,6 +13316,12 @@ case_S: case '^': if (intel_syntax) break; + if (isa64 == intel64 && (rex & REX_W)) + { + USED_REX (REX_W); + *obufp++ = 'q'; + break; + } if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) { if (sizeflag & DFLAG) @@ -14893,7 +13526,6 @@ intel_operand_size (int bytemode, int sizeflag) case w_mode: case dw_mode: case dqw_mode: - case dqw_swap_mode: oappend ("WORD PTR "); break; case indir_v_mode: @@ -14939,6 +13571,13 @@ intel_operand_size (int bytemode, int sizeflag) oappend ("DWORD PTR "); used_prefixes |= (prefixes & PREFIX_DATA); break; + case movsxd_mode: + if (!(sizeflag & DFLAG) && isa64 == intel64) + oappend ("WORD PTR "); + else + oappend ("DWORD PTR "); + used_prefixes |= (prefixes & PREFIX_DATA); + break; case d_mode: case d_scalar_mode: case d_scalar_swap_mode: @@ -14972,6 +13611,8 @@ intel_operand_size (int bytemode, int sizeflag) case x_swap_mode: case evex_x_gscat_mode: case evex_x_nobcst_mode: + case b_scalar_mode: + case w_scalar_mode: if (need_vex) { switch (vex.length) @@ -15152,8 +13793,6 @@ intel_operand_size (int bytemode, int sizeflag) case o_mode: oappend ("OWORD PTR "); break; - case xmm_mdq_mode: - case vex_w_dq_mode: case vex_scalar_w_dq_mode: if (!need_vex) abort (); @@ -15231,6 +13870,7 @@ intel_operand_size (int bytemode, int sizeflag) oappend ("WORD PTR "); break; case v_bnd_mode: + case v_bndmk_mode: default: break; } @@ -15248,8 +13888,8 @@ OP_E_register (int bytemode, int sizeflag) if ((sizeflag & SUFFIX_ALWAYS) && (bytemode == b_swap_mode - || bytemode == v_swap_mode - || bytemode == dqw_swap_mode)) + || bytemode == bnd_swap_mode + || bytemode == v_swap_mode)) swap_operand (); switch (bytemode) @@ -15278,6 +13918,12 @@ OP_E_register (int bytemode, int sizeflag) names = address_mode == mode_64bit ? names64 : names32; break; case bnd_mode: + case bnd_swap_mode: + if (reg > 0x3) + { + oappend ("(bad)"); + return; + } names = names_bnd; break; case indir_v_mode: @@ -15301,7 +13947,6 @@ OP_E_register (int bytemode, int sizeflag) case dqb_mode: case dqd_mode: case dqw_mode: - case dqw_swap_mode: USED_REX (REX_W); if (rex & REX_W) names = names64; @@ -15316,6 +13961,28 @@ OP_E_register (int bytemode, int sizeflag) used_prefixes |= (prefixes & PREFIX_DATA); } break; + case movsxd_mode: + if (!(sizeflag & DFLAG) && isa64 == intel64) + names = names16; + else + names = names32; + used_prefixes |= (prefixes & PREFIX_DATA); + break; + case va_mode: + names = (address_mode == mode_64bit + ? names64 : names32); + if (!(prefixes & PREFIX_ADDR)) + names = (address_mode == mode_16bit + ? names16 : names); + else + { + /* Remove "addr16/addr32". */ + all_prefixes[last_addr_prefix] = 0; + names = (address_mode != mode_32bit + ? names32 : names16); + used_prefixes |= PREFIX_ADDR; + } + break; case mask_bd_mode: case mask_mode: if (reg > 0x7) @@ -15357,19 +14024,25 @@ OP_E_memory (int bytemode, int sizeflag) { case dqw_mode: case dw_mode: - case dqw_swap_mode: shift = 1; break; case dqb_mode: case db_mode: shift = 0; break; + case dq_mode: + if (address_mode != mode_64bit) + { + shift = 2; + break; + } + /* fall through */ + case vex_scalar_w_dq_mode: case vex_vsib_d_w_dq_mode: case vex_vsib_d_w_d_mode: case vex_vsib_q_w_dq_mode: case vex_vsib_q_w_d_mode: case evex_x_gscat_mode: - case xmm_mdq_mode: shift = vex.w ? 3 : 2; break; case x_mode: @@ -15422,9 +14095,11 @@ OP_E_memory (int bytemode, int sizeflag) case d_scalar_swap_mode: shift = 2; break; + case w_scalar_mode: case xmm_mw_mode: shift = 1; break; + case b_scalar_mode: case xmm_mb_mode: shift = 0; break; @@ -15464,12 +14139,15 @@ OP_E_memory (int bytemode, int sizeflag) int havebase; int haveindex; int needindex; + int needaddr32; int base, rbase; int vindex = 0; int scale = 0; int addr32flag = !((sizeflag & AFLAG) || bytemode == v_bnd_mode - || bytemode == bnd_mode); + || bytemode == v_bndmk_mode + || bytemode == bnd_mode + || bytemode == bnd_swap_mode); const char **indexes64 = names64; const char **indexes32 = names32; @@ -15544,6 +14222,11 @@ OP_E_memory (int bytemode, int sizeflag) if (address_mode == mode_64bit && !havesib) riprel = 1; disp = get32s (); + if (riprel && bytemode == v_bndmk_mode) + { + oappend ("(bad)"); + return; + } } break; case 1: @@ -15559,12 +14242,27 @@ OP_E_memory (int bytemode, int sizeflag) break; } - /* In 32bit mode, we need index register to tell [offset] from - [eiz*1 + offset]. */ - needindex = (havesib - && !havebase - && !haveindex - && address_mode == mode_32bit); + needindex = 0; + needaddr32 = 0; + if (havesib + && !havebase + && !haveindex + && address_mode != mode_16bit) + { + if (address_mode == mode_64bit) + { + /* Display eiz instead of addr32. */ + needindex = addr32flag; + needaddr32 = 1; + } + else + { + /* In 32-bit mode, we need index register to tell [offset] + from [eiz*1 + offset]. */ + needindex = 1; + } + } + havedisp = (havebase || needindex || (havesib && (haveindex || scale != 0))); @@ -15584,9 +14282,12 @@ OP_E_memory (int bytemode, int sizeflag) } } - if ((havebase || haveindex || riprel) - && (bytemode != v_bnd_mode) - && (bytemode != bnd_mode)) + if ((havebase || haveindex || needindex || needaddr32 || riprel) + && (address_mode != mode_64bit + || ((bytemode != v_bnd_mode) + && (bytemode != v_bndmk_mode) + && (bytemode != bnd_mode) + && (bytemode != bnd_swap_mode)))) used_prefixes |= PREFIX_ADDR; if (havedisp || (intel_syntax && riprel)) @@ -15667,6 +14368,14 @@ OP_E_memory (int bytemode, int sizeflag) } } } + else if (bytemode == v_bnd_mode + || bytemode == v_bndmk_mode + || bytemode == bnd_mode + || bytemode == bnd_swap_mode) + { + oappend ("(bad)"); + return; + } else { /* 16 bit address mode */ @@ -15686,6 +14395,8 @@ OP_E_memory (int bytemode, int sizeflag) disp = *codep++; if ((disp & 0x80) != 0) disp -= 0x100; + if (vex.evex && shift > 0) + disp <<= shift; break; case 2: disp = get16 (); @@ -15800,6 +14511,7 @@ static void OP_G (int bytemode, int sizeflag) { int add = 0; + const char **names; USED_REX (REX_R); if (rex & REX_R) add += 8; @@ -15824,6 +14536,11 @@ OP_G (int bytemode, int sizeflag) oappend (names64[modrm.reg + add]); break; case bnd_mode: + if (modrm.reg > 0x3) + { + oappend ("(bad)"); + return; + } oappend (names_bnd[modrm.reg]); break; case v_mode: @@ -15831,19 +14548,38 @@ OP_G (int bytemode, int sizeflag) case dqb_mode: case dqd_mode: case dqw_mode: - case dqw_swap_mode: + case movsxd_mode: USED_REX (REX_W); if (rex & REX_W) oappend (names64[modrm.reg + add]); else { - if ((sizeflag & DFLAG) || bytemode != v_mode) + if ((sizeflag & DFLAG) + || (bytemode != v_mode && bytemode != movsxd_mode)) oappend (names32[modrm.reg + add]); else oappend (names16[modrm.reg + add]); used_prefixes |= (prefixes & PREFIX_DATA); } break; + case va_mode: + names = (address_mode == mode_64bit + ? names64 : names32); + if (!(prefixes & PREFIX_ADDR)) + { + if (address_mode == mode_16bit) + names = names16; + } + else + { + /* Remove "addr16/addr32". */ + all_prefixes[last_addr_prefix] = 0; + names = (address_mode != mode_32bit + ? names32 : names16); + used_prefixes |= PREFIX_ADDR; + } + oappend (names[modrm.reg + add]); + break; case m_mode: if (address_mode == mode_64bit) oappend (names64[modrm.reg + add]); @@ -16083,13 +14819,6 @@ OP_I (int bytemode, int sizeflag) op = *codep++; mask = 0xff; break; - case q_mode: - if (address_mode == mode_64bit) - { - op = get32s (); - break; - } - /* Fall through. */ case v_mode: USED_REX (REX_W); if (rex & REX_W) @@ -16109,6 +14838,10 @@ OP_I (int bytemode, int sizeflag) used_prefixes |= (prefixes & PREFIX_DATA); } break; + case d_mode: + mask = 0xffffffff; + op = get32 (); + break; case w_mode: mask = 0xfffff; op = get16 (); @@ -16132,53 +14865,16 @@ OP_I (int bytemode, int sizeflag) static void OP_I64 (int bytemode, int sizeflag) { - bfd_signed_vma op; - bfd_signed_vma mask = -1; - - if (address_mode != mode_64bit) + if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W)) { OP_I (bytemode, sizeflag); return; } - switch (bytemode) - { - case b_mode: - FETCH_DATA (the_info, codep + 1); - op = *codep++; - mask = 0xff; - break; - case v_mode: - USED_REX (REX_W); - if (rex & REX_W) - op = get64 (); - else - { - if (sizeflag & DFLAG) - { - op = get32 (); - mask = 0xffffffff; - } - else - { - op = get16 (); - mask = 0xfffff; - } - used_prefixes |= (prefixes & PREFIX_DATA); - } - break; - case w_mode: - mask = 0xfffff; - op = get16 (); - break; - default: - oappend (INTERNAL_DISASSEMBLER_ERROR); - return; - } + USED_REX (REX_W); - op &= mask; scratchbuf[0] = '$'; - print_operand_value (scratchbuf + 1, 1, op); + print_operand_value (scratchbuf + 1, 1, get64 ()); oappend_maybe_intel (scratchbuf); scratchbuf[0] = '\0'; } @@ -16252,11 +14948,13 @@ OP_J (int bytemode, int sizeflag) disp -= 0x100; break; case v_mode: - if (isa64 == amd64) + if (isa64 != intel64) + case dqw_mode: USED_REX (REX_W); if ((sizeflag & DFLAG) || (address_mode == mode_64bit - && (isa64 != amd64 || (rex & REX_W)))) + && ((isa64 == intel64 && bytemode != dqw_mode) + || (rex & REX_W)))) disp = get32s (); else { @@ -16273,7 +14971,7 @@ OP_J (int bytemode, int sizeflag) & ~((bfd_vma) 0xffff)); } if (address_mode != mode_64bit - || (isa64 == amd64 && !(rex & REX_W))) + || (isa64 != intel64 && !(rex & REX_W))) used_prefixes |= (prefixes & PREFIX_DATA); break; default: @@ -16686,7 +15384,6 @@ OP_EX (int bytemode, int sizeflag) if ((sizeflag & SUFFIX_ALWAYS) && (bytemode == x_swap_mode || bytemode == d_swap_mode - || bytemode == dqw_swap_mode || bytemode == d_scalar_swap_mode || bytemode == q_swap_mode || bytemode == q_scalar_swap_mode)) @@ -16700,7 +15397,6 @@ OP_EX (int bytemode, int sizeflag) && bytemode != xmm_mw_mode && bytemode != xmm_md_mode && bytemode != xmm_mq_mode - && bytemode != xmm_mdq_mode && bytemode != xmmq_mode && bytemode != evex_half_bcst_xmmq_mode && bytemode != ymm_mode @@ -16943,35 +15639,15 @@ CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) } static void -OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED, - int sizeflag ATTRIBUTE_UNUSED) -{ - /* mwaitx %eax,%ecx,%ebx */ - if (!intel_syntax) - { - const char **names = (address_mode == mode_64bit - ? names64 : names32); - strcpy (op_out[0], names[0]); - strcpy (op_out[1], names[1]); - strcpy (op_out[2], names[3]); - two_source_ops = 1; - } - /* Skip mod/rm byte. */ - MODRM_CHECK; - codep++; -} - -static void -OP_Mwait (int bytemode ATTRIBUTE_UNUSED, - int sizeflag ATTRIBUTE_UNUSED) +OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED) { - /* mwait %eax,%ecx */ + /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */ if (!intel_syntax) { - const char **names = (address_mode == mode_64bit - ? names64 : names32); - strcpy (op_out[0], names[0]); - strcpy (op_out[1], names[1]); + strcpy (op_out[0], names32[0]); + strcpy (op_out[1], names32[1]); + if (bytemode == eBX_reg) + strcpy (op_out[2], names32[3]); two_source_ops = 1; } /* Skip mod/rm byte. */ @@ -16983,27 +15659,25 @@ static void OP_Monitor (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) { - /* monitor %eax,%ecx,%edx" */ + /* monitor %{e,r,}ax,%ecx,%edx" */ if (!intel_syntax) { - const char **op1_names; const char **names = (address_mode == mode_64bit ? names64 : names32); - if (!(prefixes & PREFIX_ADDR)) - op1_names = (address_mode == mode_16bit - ? names16 : names); - else + if (prefixes & PREFIX_ADDR) { /* Remove "addr16/addr32". */ all_prefixes[last_addr_prefix] = 0; - op1_names = (address_mode != mode_32bit - ? names32 : names16); + names = (address_mode != mode_32bit + ? names32 : names16); used_prefixes |= PREFIX_ADDR; } - strcpy (op_out[0], op1_names[0]); - strcpy (op_out[1], names[1]); - strcpy (op_out[2], names[2]); + else if (address_mode == mode_16bit) + names = names16; + strcpy (op_out[0], names[0]); + strcpy (op_out[1], names32[1]); + strcpy (op_out[2], names32[2]); two_source_ops = 1; } /* Skip mod/rm byte. */ @@ -17046,6 +15720,18 @@ REP_Fixup (int bytemode, int sizeflag) } } +static void +SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) +{ + if ( isa64 != amd64 ) + return; + + obufp = obuf; + BadOp (); + mnemonicendp = obufp; + ++codep; +} + /* For BND-prefixed instructions 0xF2 prefix should be displayed as "bnd". */ @@ -17056,6 +15742,23 @@ BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) all_prefixes[last_repnz_prefix] = BND_PREFIX; } +/* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as + "notrack". */ + +static void +NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED, + int sizeflag ATTRIBUTE_UNUSED) +{ + if (active_seg_prefix == PREFIX_DS + && (address_mode != mode_64bit || last_data_prefix < 0)) + { + /* NOTRACK prefix is only valid on indirect branch instructions. + NB: DATA prefix is unsupported for Intel64. */ + active_seg_prefix = 0; + all_prefixes[last_seg_prefix] = NOTRACK_PREFIX; + } +} + /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as "xacquire"/"xrelease" for memory operand if there is a LOCK prefix. */ @@ -17190,7 +15893,7 @@ CRC32_Fixup (int bytemode, int sizeflag) mnemonicendp = p; *p = '\0'; -skip: + skip: if (modrm.mod == 3) { int add; @@ -17240,6 +15943,27 @@ FXSAVE_Fixup (int bytemode, int sizeflag) OP_M (bytemode, sizeflag); } +static void +PCMPESTR_Fixup (int bytemode, int sizeflag) +{ + /* Add proper suffix to "{,v}pcmpestr{i,m}". */ + if (!intel_syntax) + { + char *p = mnemonicendp; + + USED_REX (REX_W); + if (rex & REX_W) + *p++ = 'q'; + else if (sizeflag & SUFFIX_ALWAYS) + *p++ = 'l'; + + *p = '\0'; + mnemonicendp = p; + } + + OP_EX (bytemode, sizeflag); +} + /* Display the destination register operand for instructions with VEX. */ @@ -17256,11 +15980,11 @@ OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) return; reg = vex.register_specifier; - if (vex.evex) - { - if (!vex.v) - reg += 16; - } + vex.register_specifier = 0; + if (address_mode != mode_64bit) + reg &= 7; + else if (vex.evex && !vex.v) + reg += 16; if (bytemode == vex_scalar_mode) { @@ -17280,7 +16004,7 @@ OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) names = names_xmm; break; case dq_mode: - if (vex.w) + if (rex & REX_W) names = names64; else names = names32; @@ -17320,7 +16044,8 @@ OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) names = names_mask; break; default: - abort (); + /* See PR binutils/20893 for a reproducer. */ + oappend ("(bad)"); return; } break; @@ -17444,8 +16169,8 @@ OP_EX_VexReg (int bytemode, int sizeflag, int reg) if (rex & REX_B) reg += 8; } - else if (reg > 7 && address_mode != mode_64bit) - BadOp (); + if (address_mode != mode_64bit) + reg &= 7; } switch (vex.length) @@ -17537,7 +16262,14 @@ OP_Vex_2src_1 (int bytemode, int sizeflag) } if (vex.w) - oappend (names_xmm[vex.register_specifier]); + { + unsigned int reg = vex.register_specifier; + vex.register_specifier = 0; + + if (address_mode != mode_64bit) + reg &= 7; + oappend (names_xmm[reg]); + } else OP_Vex_2src (bytemode, sizeflag); } @@ -17548,7 +16280,14 @@ OP_Vex_2src_2 (int bytemode, int sizeflag) if (vex.w) OP_Vex_2src (bytemode, sizeflag); else - oappend (names_xmm[vex.register_specifier]); + { + unsigned int reg = vex.register_specifier; + vex.register_specifier = 0; + + if (address_mode != mode_64bit) + reg &= 7; + oappend (names_xmm[reg]); + } } static void @@ -17558,8 +16297,6 @@ OP_EX_VexW (int bytemode, int sizeflag) if (!vex_w_done) { - vex_w_done = 1; - /* Skip mod/rm byte. */ MODRM_CHECK; codep++; @@ -17574,16 +16311,10 @@ OP_EX_VexW (int bytemode, int sizeflag) } OP_EX_VexReg (bytemode, sizeflag, reg); -} -static void -VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED, - int sizeflag ATTRIBUTE_UNUSED) -{ - /* Skip the immediate byte and check for invalid bits. */ - FETCH_DATA (the_info, codep + 1); - if (*codep++ & 0xf) - BadOp (); + if (vex_w_done) + codep++; + vex_w_done = 1; } static void @@ -17598,12 +16329,9 @@ OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) if (bytemode != x_mode) abort (); - if (reg & 0xf) - BadOp (); - reg >>= 4; - if (reg > 7 && address_mode != mode_64bit) - BadOp (); + if (address_mode != mode_64bit) + reg &= 7; switch (vex.length) { @@ -17632,11 +16360,7 @@ static void OP_EX_Vex (int bytemode, int sizeflag) { if (modrm.mod != 3) - { - if (vex.register_specifier != 0) - BadOp (); - need_vex_reg = 0; - } + need_vex_reg = 0; OP_EX (bytemode, sizeflag); } @@ -17644,30 +16368,10 @@ static void OP_XMM_Vex (int bytemode, int sizeflag) { if (modrm.mod != 3) - { - if (vex.register_specifier != 0) - BadOp (); - need_vex_reg = 0; - } + need_vex_reg = 0; OP_XMM (bytemode, sizeflag); } -static void -VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) -{ - switch (vex.length) - { - case 128: - mnemonicendp = stpcpy (obuf, "vzeroupper"); - break; - case 256: - mnemonicendp = stpcpy (obuf, "vzeroall"); - break; - default: - abort (); - } -} - static struct op vex_cmp_op[] = { { STRING_COMMA_LEN ("eq") }, @@ -17778,6 +16482,58 @@ VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, } } +static const struct op xop_cmp_op[] = +{ + { STRING_COMMA_LEN ("lt") }, + { STRING_COMMA_LEN ("le") }, + { STRING_COMMA_LEN ("gt") }, + { STRING_COMMA_LEN ("ge") }, + { STRING_COMMA_LEN ("eq") }, + { STRING_COMMA_LEN ("neq") }, + { STRING_COMMA_LEN ("false") }, + { STRING_COMMA_LEN ("true") } +}; + +static void +VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED, + int sizeflag ATTRIBUTE_UNUSED) +{ + unsigned int cmp_type; + + FETCH_DATA (the_info, codep + 1); + cmp_type = *codep++ & 0xff; + if (cmp_type < ARRAY_SIZE (xop_cmp_op)) + { + char suffix[3]; + char *p = mnemonicendp - 2; + + /* vpcom* can have both one- and two-lettered suffix. */ + if (p[0] == 'm') + { + p++; + suffix[0] = p[0]; + suffix[1] = '\0'; + } + else + { + suffix[0] = p[0]; + suffix[1] = p[1]; + suffix[2] = '\0'; + } + + sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix); + mnemonicendp += xop_cmp_op[cmp_type].len; + } + else + { + /* We have a reserved extension byte. Output it directly. */ + scratchbuf[0] = '$'; + print_operand_value (scratchbuf + 1, 1, cmp_type); + oappend_maybe_intel (scratchbuf); + scratchbuf[0] = '\0'; + } +} + static const struct op pclmul_op[] = { { STRING_COMMA_LEN ("lql") }, @@ -17860,10 +16616,49 @@ MOVBE_Fixup (int bytemode, int sizeflag) mnemonicendp = p; *p = '\0'; -skip: + skip: OP_M (bytemode, sizeflag); } +static void +MOVSXD_Fixup (int bytemode, int sizeflag) +{ + /* Add proper suffix to "movsxd". */ + char *p = mnemonicendp; + + switch (bytemode) + { + case movsxd_mode: + if (intel_syntax) + { + *p++ = 'x'; + *p++ = 'd'; + goto skip; + } + + USED_REX (REX_W); + if (rex & REX_W) + { + *p++ = 'l'; + *p++ = 'q'; + } + else + { + *p++ = 'x'; + *p++ = 'd'; + } + break; + default: + oappend (INTERNAL_DISASSEMBLER_ERROR); + break; + } + + skip: + mnemonicendp = p; + *p = '\0'; + OP_E (bytemode, sizeflag); +} + static void OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) { @@ -17874,7 +16669,7 @@ OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) MODRM_CHECK; codep++; - if (vex.w) + if (rex & REX_W) names = names64; else names = names32; @@ -17891,13 +16686,17 @@ static void OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) { const char **names; + unsigned int reg = vex.register_specifier; + vex.register_specifier = 0; - if (vex.w) + if (rex & REX_W) names = names64; else names = names32; - oappend (names[vex.register_specifier]); + if (address_mode != mode_64bit) + reg &= 7; + oappend (names[reg]); } static void @@ -17922,11 +16721,19 @@ OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED) { if (!vex.evex || (bytemode != evex_rounding_mode + && bytemode != evex_rounding_64_mode && bytemode != evex_sae_mode)) abort (); if (modrm.mod == 3 && vex.b) switch (bytemode) { + case evex_rounding_64_mode: + if (address_mode != mode_64bit) + { + oappend ("(bad)"); + break; + } + /* Fall through. */ case evex_rounding_mode: oappend (names_rounding[vex.ll]); break;