X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Fi386-dis.c;h=21d9d3a61a63edabc57ac6feb00f4b50cbadbde6;hb=50d036364fb2a71b3ac9a0b0cdbe58296832a1b2;hp=3e45d0e1f353dc9a97216f5a3ea1667729f2ce38;hpb=caf0678c84b5b55fbc4bcc853954745a4ad8b658;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 3e45d0e1f3..21d9d3a61a 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -1,5 +1,5 @@ /* Print i386 instructions for GDB, the GNU debugger. - Copyright (C) 1988-2018 Free Software Foundation, Inc. + Copyright (C) 1988-2020 Free Software Foundation, Inc. This file is part of the GNU opcodes library. @@ -95,20 +95,19 @@ static void OP_XMM_VexW (int, int); static void OP_Rounding (int, int); static void OP_REG_VexI4 (int, int); static void PCLMUL_Fixup (int, int); -static void VZERO_Fixup (int, int); static void VCMP_Fixup (int, int); static void VPCMP_Fixup (int, int); static void VPCOM_Fixup (int, int); static void OP_0f07 (int, int); static void OP_Monitor (int, int); static void OP_Mwait (int, int); -static void OP_Mwaitx (int, int); static void NOP_Fixup1 (int, int); static void NOP_Fixup2 (int, int); static void OP_3DNowSuffix (int, int); static void CMP_Fixup (int, int); static void BadOp (void); static void REP_Fixup (int, int); +static void SEP_Fixup (int, int); static void BND_Fixup (int, int); static void NOTRACK_Fixup (int, int); static void HLE_Fixup1 (int, int); @@ -125,6 +124,7 @@ static void OP_Vex_2src_1 (int, int); static void OP_Vex_2src_2 (int, int); static void MOVBE_Fixup (int, int); +static void MOVSXD_Fixup (int, int); static void OP_Mask (int, int); @@ -250,6 +250,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define EbS { OP_E, b_swap_mode } #define EbndS { OP_E, bnd_swap_mode } #define Ev { OP_E, v_mode } +#define Eva { OP_E, va_mode } #define Ev_bnd { OP_E, v_bnd_mode } #define EvS { OP_E, v_swap_mode } #define Ed { OP_E, d_mode } @@ -272,6 +273,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define Mo { OP_M, o_mode } #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ #define Mq { OP_M, q_mode } +#define Mv_bnd { OP_M, v_bndmk_mode } #define Mx { OP_M, x_mode } #define Mxmm { OP_M, xmm_mode } #define Gb { OP_G, b_mode } @@ -280,6 +282,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define Gd { OP_G, d_mode } #define Gdq { OP_G, dq_mode } #define Gm { OP_G, m_mode } +#define Gva { OP_G, va_mode } #define Gw { OP_G, w_mode } #define Rd { OP_R, d_mode } #define Rdq { OP_R, dq_mode } @@ -289,12 +292,13 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ #define Iv { OP_I, v_mode } #define sIv { OP_sI, v_mode } -#define Iq { OP_I, q_mode } #define Iv64 { OP_I64, v_mode } +#define Id { OP_I, d_mode } #define Iw { OP_I, w_mode } #define I1 { OP_I, const_1_mode } #define Jb { OP_J, b_mode } #define Jv { OP_J, v_mode } +#define Jdqw { OP_J, dqw_mode } #define Cm { OP_C, m_mode } #define Dm { OP_D, m_mode } #define Td { OP_T, d_mode } @@ -383,7 +387,6 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define EXd { OP_EX, d_mode } #define EXdScalar { OP_EX, d_scalar_mode } #define EXdS { OP_EX, d_swap_mode } -#define EXdScalarS { OP_EX, d_scalar_swap_mode } #define EXq { OP_EX, q_mode } #define EXqScalar { OP_EX, q_scalar_mode } #define EXqScalarS { OP_EX, q_scalar_swap_mode } @@ -398,11 +401,9 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define EXxmm_mw { OP_EX, xmm_mw_mode } #define EXxmm_md { OP_EX, xmm_md_mode } #define EXxmm_mq { OP_EX, xmm_mq_mode } -#define EXxmm_mdq { OP_EX, xmm_mdq_mode } #define EXxmmdw { OP_EX, xmmdw_mode } #define EXxmmqd { OP_EX, xmmqd_mode } #define EXymmq { OP_EX, ymmq_mode } -#define EXVexWdq { OP_EX, vex_w_dq_mode } #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode } #define EXEvexXGscat { OP_EX, evex_x_gscat_mode } #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode } @@ -411,6 +412,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define EMCq { OP_EMC, q_mode } #define MXC { OP_MXC, 0 } #define OPSUF { OP_3DNowSuffix, 0 } +#define SEP { SEP_Fixup, 0 } #define CMP { CMP_Fixup, 0 } #define XMM0 { XMM_Fixup, 0 } #define FXSAVE { FXSAVE_Fixup, 0 } @@ -423,27 +425,22 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define Vex128 { OP_VEX, vex128_mode } #define Vex256 { OP_VEX, vex256_mode } #define VexGdq { OP_VEX, dq_mode } -#define EXdVex { OP_EX_Vex, d_mode } -#define EXdVexS { OP_EX_Vex, d_swap_mode } #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode } -#define EXqVex { OP_EX_Vex, q_mode } -#define EXqVexS { OP_EX_Vex, q_swap_mode } #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode } #define EXVexW { OP_EX_VexW, x_mode } #define EXdVexW { OP_EX_VexW, d_mode } #define EXqVexW { OP_EX_VexW, q_mode } #define EXVexImmW { OP_EX_VexImmW, x_mode } -#define XMVex { OP_XMM_Vex, 0 } #define XMVexScalar { OP_XMM_Vex, scalar_mode } #define XMVexW { OP_XMM_VexW, 0 } #define XMVexI4 { OP_REG_VexI4, x_mode } #define PCLMUL { PCLMUL_Fixup, 0 } -#define VZERO { VZERO_Fixup, 0 } #define VCMP { VCMP_Fixup, 0 } #define VPCMP { VPCMP_Fixup, 0 } #define VPCOM { VPCOM_Fixup, 0 } #define EXxEVexR { OP_Rounding, evex_rounding_mode } +#define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode } #define EXxEVexS { OP_Rounding, evex_sae_mode } #define XMask { OP_Mask, mask_mode } @@ -499,6 +496,8 @@ enum v_mode, /* operand size depends on prefixes with operand swapped */ v_swap_mode, + /* operand size depends on address prefix */ + va_mode, /* word operand */ w_mode, /* double word operand */ @@ -537,9 +536,6 @@ enum xmm_md_mode, /* XMM register or quad word memory operand */ xmm_mq_mode, - /* XMM register or double/quad word memory operand, depending on - VEX.W. */ - xmm_mdq_mode, /* 16-byte XMM, word, double word or quad word operand. */ xmmdw_mode, /* 16-byte XMM, double word, quad word operand or xmm word operand. */ @@ -556,10 +552,14 @@ enum a_mode, cond_jump_mode, loop_jcxz_mode, + movsxd_mode, v_bnd_mode, + /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */ + v_bndmk_mode, /* operand size depends on REX prefixes. */ dq_mode, - /* registers like dq_mode, memory like w_mode. */ + /* registers like dq_mode, memory like w_mode, displacements like + v_mode without considering Intel64 ISA. */ dqw_mode, /* bounds operand */ bnd_mode, @@ -590,14 +590,12 @@ enum vex128_mode, /* 256bit vex mode */ vex256_mode, - /* operand size depends on the VEX.W bit. */ - vex_w_dq_mode, - /* Similar to vex_w_dq_mode, with VSIB dword indices. */ + /* Operand size depends on the VEX.W bit, with VSIB dword indices. */ vex_vsib_d_w_dq_mode, /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */ vex_vsib_d_w_d_mode, - /* Similar to vex_w_dq_mode, with VSIB qword indices. */ + /* Operand size depends on the VEX.W bit, with VSIB qword indices. */ vex_vsib_q_w_dq_mode, /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */ vex_vsib_q_w_d_mode, @@ -618,11 +616,13 @@ enum q_scalar_swap_mode, /* like vex_mode, ignore vector length. */ vex_scalar_mode, - /* like vex_w_dq_mode, ignore vector length. */ + /* Operand size depends on the VEX.W bit, ignore vector length. */ vex_scalar_w_dq_mode, /* Static rounding. */ evex_rounding_mode, + /* Static rounding, 64-bit mode only. */ + evex_rounding_64_mode, /* Supress all exceptions. */ evex_sae_mode, @@ -692,7 +692,8 @@ enum USE_VEX_C5_TABLE, USE_VEX_LEN_TABLE, USE_VEX_W_TABLE, - USE_EVEX_TABLE + USE_EVEX_TABLE, + USE_EVEX_LEN_TABLE }; #define FLOAT NULL, { { NULL, FLOATCODE } }, 0 @@ -712,6 +713,7 @@ enum #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I)) +#define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I)) enum { @@ -735,7 +737,8 @@ enum REG_0F01, REG_0F0D, REG_0F18, - REG_0F1E_MOD_3, + REG_0F1C_P_0_MOD_0, + REG_0F1E_P_1_MOD_3, REG_0F71, REG_0F72, REG_0F73, @@ -789,6 +792,7 @@ enum MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0, MOD_0F1B_PREFIX_1, + MOD_0F1C_PREFIX_0, MOD_0F1E_PREFIX_1, MOD_0F24, MOD_0F26, @@ -830,6 +834,10 @@ enum MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0, + MOD_0F38F8_PREFIX_1, + MOD_0F38F8_PREFIX_2, + MOD_0F38F8_PREFIX_3, + MOD_0F38F9_PREFIX_0, MOD_62_32BIT, MOD_C4_32BIT, MOD_C5_32BIT, @@ -886,12 +894,10 @@ enum MOD_VEX_W_1_0F91_P_2_LEN_0, MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0, - MOD_VEX_W_0_0F92_P_3_LEN_0, - MOD_VEX_W_1_0F92_P_3_LEN_0, + MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0, - MOD_VEX_W_0_0F93_P_3_LEN_0, - MOD_VEX_W_1_0F93_P_3_LEN_0, + MOD_VEX_0F93_P_3_LEN_0, MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0, MOD_VEX_W_0_0F98_P_2_LEN_0, @@ -923,10 +929,6 @@ enum MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0, - MOD_EVEX_0F10_PREFIX_1, - MOD_EVEX_0F10_PREFIX_3, - MOD_EVEX_0F11_PREFIX_1, - MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, @@ -947,19 +949,23 @@ enum RM_0F01_REG_1, RM_0F01_REG_2, RM_0F01_REG_3, - RM_0F01_REG_5, - RM_0F01_REG_7, - RM_0F1E_MOD_3_REG_7, - RM_0FAE_REG_6, - RM_0FAE_REG_7 + RM_0F01_REG_5_MOD_3, + RM_0F01_REG_7_MOD_3, + RM_0F1E_P_1_MOD_3_REG_7, + RM_0FAE_REG_6_MOD_3_P_0, + RM_0FAE_REG_7_MOD_3, }; enum { PREFIX_90 = 0, - PREFIX_MOD_0_0F01_REG_5, - PREFIX_MOD_3_0F01_REG_5_RM_0, - PREFIX_MOD_3_0F01_REG_5_RM_2, + PREFIX_0F01_REG_3_RM_1, + PREFIX_0F01_REG_5_MOD_0, + PREFIX_0F01_REG_5_MOD_3_RM_0, + PREFIX_0F01_REG_5_MOD_3_RM_1, + PREFIX_0F01_REG_5_MOD_3_RM_2, + PREFIX_0F01_REG_7_MOD_3_RM_2, + PREFIX_0F01_REG_7_MOD_3_RM_3, PREFIX_0F09, PREFIX_0F10, PREFIX_0F11, @@ -967,6 +973,7 @@ enum PREFIX_0F16, PREFIX_0F1A, PREFIX_0F1B, + PREFIX_0F1C, PREFIX_0F1E, PREFIX_0F2A, PREFIX_0F2B, @@ -1000,24 +1007,25 @@ enum PREFIX_0F7D, PREFIX_0F7E, PREFIX_0F7F, - PREFIX_0FAE_REG_0, - PREFIX_0FAE_REG_1, - PREFIX_0FAE_REG_2, - PREFIX_0FAE_REG_3, - PREFIX_MOD_0_0FAE_REG_4, - PREFIX_MOD_3_0FAE_REG_4, - PREFIX_MOD_0_0FAE_REG_5, - PREFIX_MOD_3_0FAE_REG_5, - PREFIX_0FAE_REG_6, - PREFIX_0FAE_REG_7, + PREFIX_0FAE_REG_0_MOD_3, + PREFIX_0FAE_REG_1_MOD_3, + PREFIX_0FAE_REG_2_MOD_3, + PREFIX_0FAE_REG_3_MOD_3, + PREFIX_0FAE_REG_4_MOD_0, + PREFIX_0FAE_REG_4_MOD_3, + PREFIX_0FAE_REG_5_MOD_0, + PREFIX_0FAE_REG_5_MOD_3, + PREFIX_0FAE_REG_6_MOD_0, + PREFIX_0FAE_REG_6_MOD_3, + PREFIX_0FAE_REG_7_MOD_0, PREFIX_0FB8, PREFIX_0FBC, PREFIX_0FBD, PREFIX_0FC2, - PREFIX_MOD_0_0FC3, - PREFIX_MOD_0_0FC7_REG_6, - PREFIX_MOD_3_0FC7_REG_6, - PREFIX_MOD_3_0FC7_REG_7, + PREFIX_0FC3_MOD_0, + PREFIX_0FC7_REG_6_MOD_0, + PREFIX_0FC7_REG_6_MOD_3, + PREFIX_0FC7_REG_7_MOD_3, PREFIX_0FD0, PREFIX_0FD6, PREFIX_0FE6, @@ -1074,6 +1082,8 @@ enum PREFIX_0F38F1, PREFIX_0F38F5, PREFIX_0F38F6, + PREFIX_0F38F8, + PREFIX_0F38F9, PREFIX_0F3A08, PREFIX_0F3A09, PREFIX_0F3A0A, @@ -1592,6 +1602,7 @@ enum PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, + PREFIX_EVEX_0F3868, PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872, @@ -1731,7 +1742,7 @@ enum { X86_64_06 = 0, X86_64_07, - X86_64_0D, + X86_64_0E, X86_64_16, X86_64_17, X86_64_1E, @@ -1748,6 +1759,8 @@ enum X86_64_6F, X86_64_82, X86_64_9A, + X86_64_C2, + X86_64_C3, X86_64_C4, X86_64_C5, X86_64_CE, @@ -1791,11 +1804,7 @@ enum enum { - VEX_LEN_0F10_P_1 = 0, - VEX_LEN_0F10_P_3, - VEX_LEN_0F11_P_1, - VEX_LEN_0F11_P_3, - VEX_LEN_0F12_P_0_M_0, + VEX_LEN_0F12_P_0_M_0 = 0, VEX_LEN_0F12_P_0_M_1, VEX_LEN_0F12_P_2, VEX_LEN_0F13_M_0, @@ -1803,16 +1812,6 @@ enum VEX_LEN_0F16_P_0_M_1, VEX_LEN_0F16_P_2, VEX_LEN_0F17_M_0, - VEX_LEN_0F2A_P_1, - VEX_LEN_0F2A_P_3, - VEX_LEN_0F2C_P_1, - VEX_LEN_0F2C_P_3, - VEX_LEN_0F2D_P_1, - VEX_LEN_0F2D_P_3, - VEX_LEN_0F2E_P_0, - VEX_LEN_0F2E_P_2, - VEX_LEN_0F2F_P_0, - VEX_LEN_0F2F_P_2, VEX_LEN_0F41_P_0, VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, @@ -1829,25 +1828,8 @@ enum VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2, - VEX_LEN_0F51_P_1, - VEX_LEN_0F51_P_3, - VEX_LEN_0F52_P_1, - VEX_LEN_0F53_P_1, - VEX_LEN_0F58_P_1, - VEX_LEN_0F58_P_3, - VEX_LEN_0F59_P_1, - VEX_LEN_0F59_P_3, - VEX_LEN_0F5A_P_1, - VEX_LEN_0F5A_P_3, - VEX_LEN_0F5C_P_1, - VEX_LEN_0F5C_P_3, - VEX_LEN_0F5D_P_1, - VEX_LEN_0F5D_P_3, - VEX_LEN_0F5E_P_1, - VEX_LEN_0F5E_P_3, - VEX_LEN_0F5F_P_1, - VEX_LEN_0F5F_P_3, VEX_LEN_0F6E_P_2, + VEX_LEN_0F77_P_0, VEX_LEN_0F7E_P_1, VEX_LEN_0F7E_P_2, VEX_LEN_0F90_P_0, @@ -1866,8 +1848,6 @@ enum VEX_LEN_0F99_P_2, VEX_LEN_0FAE_R_2_M_0, VEX_LEN_0FAE_R_3_M_0, - VEX_LEN_0FC2_P_1, - VEX_LEN_0FC2_P_3, VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2, @@ -1894,8 +1874,6 @@ enum VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2, VEX_LEN_0F3A06_P_2, - VEX_LEN_0F3A0A_P_2, - VEX_LEN_0F3A0B_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2, VEX_LEN_0F3A16_P_2, @@ -1941,35 +1919,57 @@ enum enum { - VEX_W_0F10_P_0 = 0, - VEX_W_0F10_P_1, - VEX_W_0F10_P_2, - VEX_W_0F10_P_3, - VEX_W_0F11_P_0, - VEX_W_0F11_P_1, - VEX_W_0F11_P_2, - VEX_W_0F11_P_3, - VEX_W_0F12_P_0_M_0, - VEX_W_0F12_P_0_M_1, - VEX_W_0F12_P_1, - VEX_W_0F12_P_2, - VEX_W_0F12_P_3, - VEX_W_0F13_M_0, - VEX_W_0F14, - VEX_W_0F15, - VEX_W_0F16_P_0_M_0, - VEX_W_0F16_P_0_M_1, - VEX_W_0F16_P_1, - VEX_W_0F16_P_2, - VEX_W_0F17_M_0, - VEX_W_0F28, - VEX_W_0F29, - VEX_W_0F2B_M_0, - VEX_W_0F2E_P_0, - VEX_W_0F2E_P_2, - VEX_W_0F2F_P_0, - VEX_W_0F2F_P_2, - VEX_W_0F41_P_0_LEN_1, + EVEX_LEN_0F6E_P_2 = 0, + EVEX_LEN_0F7E_P_1, + EVEX_LEN_0F7E_P_2, + EVEX_LEN_0FD6_P_2, + EVEX_LEN_0F3819_P_2_W_0, + EVEX_LEN_0F3819_P_2_W_1, + EVEX_LEN_0F381A_P_2_W_0, + EVEX_LEN_0F381A_P_2_W_1, + EVEX_LEN_0F381B_P_2_W_0, + EVEX_LEN_0F381B_P_2_W_1, + EVEX_LEN_0F385A_P_2_W_0, + EVEX_LEN_0F385A_P_2_W_1, + EVEX_LEN_0F385B_P_2_W_0, + EVEX_LEN_0F385B_P_2_W_1, + EVEX_LEN_0F38C6_REG_1_PREFIX_2, + EVEX_LEN_0F38C6_REG_2_PREFIX_2, + EVEX_LEN_0F38C6_REG_5_PREFIX_2, + EVEX_LEN_0F38C6_REG_6_PREFIX_2, + EVEX_LEN_0F38C7_R_1_P_2_W_0, + EVEX_LEN_0F38C7_R_1_P_2_W_1, + EVEX_LEN_0F38C7_R_2_P_2_W_0, + EVEX_LEN_0F38C7_R_2_P_2_W_1, + EVEX_LEN_0F38C7_R_5_P_2_W_0, + EVEX_LEN_0F38C7_R_5_P_2_W_1, + EVEX_LEN_0F38C7_R_6_P_2_W_0, + EVEX_LEN_0F38C7_R_6_P_2_W_1, + EVEX_LEN_0F3A18_P_2_W_0, + EVEX_LEN_0F3A18_P_2_W_1, + EVEX_LEN_0F3A19_P_2_W_0, + EVEX_LEN_0F3A19_P_2_W_1, + EVEX_LEN_0F3A1A_P_2_W_0, + EVEX_LEN_0F3A1A_P_2_W_1, + EVEX_LEN_0F3A1B_P_2_W_0, + EVEX_LEN_0F3A1B_P_2_W_1, + EVEX_LEN_0F3A23_P_2_W_0, + EVEX_LEN_0F3A23_P_2_W_1, + EVEX_LEN_0F3A38_P_2_W_0, + EVEX_LEN_0F3A38_P_2_W_1, + EVEX_LEN_0F3A39_P_2_W_0, + EVEX_LEN_0F3A39_P_2_W_1, + EVEX_LEN_0F3A3A_P_2_W_0, + EVEX_LEN_0F3A3A_P_2_W_1, + EVEX_LEN_0F3A3B_P_2_W_0, + EVEX_LEN_0F3A3B_P_2_W_1, + EVEX_LEN_0F3A43_P_2_W_0, + EVEX_LEN_0F3A43_P_2_W_1 +}; + +enum +{ + VEX_W_0F41_P_0_LEN_1 = 0, VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1, VEX_W_0F42_P_2_LEN_1, @@ -1985,213 +1985,31 @@ enum VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1, - VEX_W_0F50_M_0, - VEX_W_0F51_P_0, - VEX_W_0F51_P_1, - VEX_W_0F51_P_2, - VEX_W_0F51_P_3, - VEX_W_0F52_P_0, - VEX_W_0F52_P_1, - VEX_W_0F53_P_0, - VEX_W_0F53_P_1, - VEX_W_0F58_P_0, - VEX_W_0F58_P_1, - VEX_W_0F58_P_2, - VEX_W_0F58_P_3, - VEX_W_0F59_P_0, - VEX_W_0F59_P_1, - VEX_W_0F59_P_2, - VEX_W_0F59_P_3, - VEX_W_0F5A_P_0, - VEX_W_0F5A_P_1, - VEX_W_0F5A_P_3, - VEX_W_0F5B_P_0, - VEX_W_0F5B_P_1, - VEX_W_0F5B_P_2, - VEX_W_0F5C_P_0, - VEX_W_0F5C_P_1, - VEX_W_0F5C_P_2, - VEX_W_0F5C_P_3, - VEX_W_0F5D_P_0, - VEX_W_0F5D_P_1, - VEX_W_0F5D_P_2, - VEX_W_0F5D_P_3, - VEX_W_0F5E_P_0, - VEX_W_0F5E_P_1, - VEX_W_0F5E_P_2, - VEX_W_0F5E_P_3, - VEX_W_0F5F_P_0, - VEX_W_0F5F_P_1, - VEX_W_0F5F_P_2, - VEX_W_0F5F_P_3, - VEX_W_0F60_P_2, - VEX_W_0F61_P_2, - VEX_W_0F62_P_2, - VEX_W_0F63_P_2, - VEX_W_0F64_P_2, - VEX_W_0F65_P_2, - VEX_W_0F66_P_2, - VEX_W_0F67_P_2, - VEX_W_0F68_P_2, - VEX_W_0F69_P_2, - VEX_W_0F6A_P_2, - VEX_W_0F6B_P_2, - VEX_W_0F6C_P_2, - VEX_W_0F6D_P_2, - VEX_W_0F6F_P_1, - VEX_W_0F6F_P_2, - VEX_W_0F70_P_1, - VEX_W_0F70_P_2, - VEX_W_0F70_P_3, - VEX_W_0F71_R_2_P_2, - VEX_W_0F71_R_4_P_2, - VEX_W_0F71_R_6_P_2, - VEX_W_0F72_R_2_P_2, - VEX_W_0F72_R_4_P_2, - VEX_W_0F72_R_6_P_2, - VEX_W_0F73_R_2_P_2, - VEX_W_0F73_R_3_P_2, - VEX_W_0F73_R_6_P_2, - VEX_W_0F73_R_7_P_2, - VEX_W_0F74_P_2, - VEX_W_0F75_P_2, - VEX_W_0F76_P_2, - VEX_W_0F77_P_0, - VEX_W_0F7C_P_2, - VEX_W_0F7C_P_3, - VEX_W_0F7D_P_2, - VEX_W_0F7D_P_3, - VEX_W_0F7E_P_1, - VEX_W_0F7F_P_1, - VEX_W_0F7F_P_2, VEX_W_0F90_P_0_LEN_0, VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F92_P_2_LEN_0, - VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F93_P_2_LEN_0, - VEX_W_0F93_P_3_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0, - VEX_W_0FAE_R_2_M_0, - VEX_W_0FAE_R_3_M_0, - VEX_W_0FC2_P_0, - VEX_W_0FC2_P_1, - VEX_W_0FC2_P_2, - VEX_W_0FC2_P_3, - VEX_W_0FC4_P_2, - VEX_W_0FC5_P_2, - VEX_W_0FD0_P_2, - VEX_W_0FD0_P_3, - VEX_W_0FD1_P_2, - VEX_W_0FD2_P_2, - VEX_W_0FD3_P_2, - VEX_W_0FD4_P_2, - VEX_W_0FD5_P_2, - VEX_W_0FD6_P_2, - VEX_W_0FD7_P_2_M_1, - VEX_W_0FD8_P_2, - VEX_W_0FD9_P_2, - VEX_W_0FDA_P_2, - VEX_W_0FDB_P_2, - VEX_W_0FDC_P_2, - VEX_W_0FDD_P_2, - VEX_W_0FDE_P_2, - VEX_W_0FDF_P_2, - VEX_W_0FE0_P_2, - VEX_W_0FE1_P_2, - VEX_W_0FE2_P_2, - VEX_W_0FE3_P_2, - VEX_W_0FE4_P_2, - VEX_W_0FE5_P_2, - VEX_W_0FE6_P_1, - VEX_W_0FE6_P_2, - VEX_W_0FE6_P_3, - VEX_W_0FE7_P_2_M_0, - VEX_W_0FE8_P_2, - VEX_W_0FE9_P_2, - VEX_W_0FEA_P_2, - VEX_W_0FEB_P_2, - VEX_W_0FEC_P_2, - VEX_W_0FED_P_2, - VEX_W_0FEE_P_2, - VEX_W_0FEF_P_2, - VEX_W_0FF0_P_3_M_0, - VEX_W_0FF1_P_2, - VEX_W_0FF2_P_2, - VEX_W_0FF3_P_2, - VEX_W_0FF4_P_2, - VEX_W_0FF5_P_2, - VEX_W_0FF6_P_2, - VEX_W_0FF7_P_2, - VEX_W_0FF8_P_2, - VEX_W_0FF9_P_2, - VEX_W_0FFA_P_2, - VEX_W_0FFB_P_2, - VEX_W_0FFC_P_2, - VEX_W_0FFD_P_2, - VEX_W_0FFE_P_2, - VEX_W_0F3800_P_2, - VEX_W_0F3801_P_2, - VEX_W_0F3802_P_2, - VEX_W_0F3803_P_2, - VEX_W_0F3804_P_2, - VEX_W_0F3805_P_2, - VEX_W_0F3806_P_2, - VEX_W_0F3807_P_2, - VEX_W_0F3808_P_2, - VEX_W_0F3809_P_2, - VEX_W_0F380A_P_2, - VEX_W_0F380B_P_2, VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2, VEX_W_0F380F_P_2, VEX_W_0F3816_P_2, - VEX_W_0F3817_P_2, VEX_W_0F3818_P_2, VEX_W_0F3819_P_2, VEX_W_0F381A_P_2_M_0, - VEX_W_0F381C_P_2, - VEX_W_0F381D_P_2, - VEX_W_0F381E_P_2, - VEX_W_0F3820_P_2, - VEX_W_0F3821_P_2, - VEX_W_0F3822_P_2, - VEX_W_0F3823_P_2, - VEX_W_0F3824_P_2, - VEX_W_0F3825_P_2, - VEX_W_0F3828_P_2, - VEX_W_0F3829_P_2, - VEX_W_0F382A_P_2_M_0, - VEX_W_0F382B_P_2, VEX_W_0F382C_P_2_M_0, VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0, VEX_W_0F382F_P_2_M_0, - VEX_W_0F3830_P_2, - VEX_W_0F3831_P_2, - VEX_W_0F3832_P_2, - VEX_W_0F3833_P_2, - VEX_W_0F3834_P_2, - VEX_W_0F3835_P_2, VEX_W_0F3836_P_2, - VEX_W_0F3837_P_2, - VEX_W_0F3838_P_2, - VEX_W_0F3839_P_2, - VEX_W_0F383A_P_2, - VEX_W_0F383B_P_2, - VEX_W_0F383C_P_2, - VEX_W_0F383D_P_2, - VEX_W_0F383E_P_2, - VEX_W_0F383F_P_2, - VEX_W_0F3840_P_2, - VEX_W_0F3841_P_2, VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2, @@ -2199,60 +2017,37 @@ enum VEX_W_0F3878_P_2, VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, - VEX_W_0F38DB_P_2, VEX_W_0F3A00_P_2, VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2, VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2, - VEX_W_0F3A08_P_2, - VEX_W_0F3A09_P_2, - VEX_W_0F3A0A_P_2, - VEX_W_0F3A0B_P_2, - VEX_W_0F3A0C_P_2, - VEX_W_0F3A0D_P_2, - VEX_W_0F3A0E_P_2, - VEX_W_0F3A0F_P_2, - VEX_W_0F3A14_P_2, - VEX_W_0F3A15_P_2, VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, - VEX_W_0F3A20_P_2, - VEX_W_0F3A21_P_2, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2, VEX_W_0F3A39_P_2, - VEX_W_0F3A40_P_2, - VEX_W_0F3A41_P_2, - VEX_W_0F3A42_P_2, VEX_W_0F3A46_P_2, VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2, - VEX_W_0F3A62_P_2, - VEX_W_0F3A63_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, - VEX_W_0F3ADF_P_2, EVEX_W_0F10_P_0, - EVEX_W_0F10_P_1_M_0, - EVEX_W_0F10_P_1_M_1, + EVEX_W_0F10_P_1, EVEX_W_0F10_P_2, - EVEX_W_0F10_P_3_M_0, - EVEX_W_0F10_P_3_M_1, + EVEX_W_0F10_P_3, EVEX_W_0F11_P_0, - EVEX_W_0F11_P_1_M_0, - EVEX_W_0F11_P_1_M_1, + EVEX_W_0F11_P_1, EVEX_W_0F11_P_2, - EVEX_W_0F11_P_3_M_0, - EVEX_W_0F11_P_3_M_1, + EVEX_W_0F11_P_3, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, @@ -2274,7 +2069,6 @@ enum EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, - EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, @@ -2331,7 +2125,6 @@ enum EVEX_W_0F6B_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, - EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F6F_P_3, @@ -2348,11 +2141,9 @@ enum EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_2, EVEX_W_0F7A_P_3, - EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_2, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, - EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0F7F_P_3, @@ -2422,6 +2213,7 @@ enum EVEX_W_0F3839_P_1, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, + EVEX_W_0F3852_P_1, EVEX_W_0F3854_P_2, EVEX_W_0F3855_P_2, EVEX_W_0F3858_P_2, @@ -2431,9 +2223,12 @@ enum EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2, EVEX_W_0F3866_P_2, + EVEX_W_0F3868_P_3, EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, + EVEX_W_0F3872_P_1, EVEX_W_0F3872_P_2, + EVEX_W_0F3872_P_3, EVEX_W_0F3873_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, @@ -2460,14 +2255,12 @@ enum EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, - EVEX_W_0F3A16_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, - EVEX_W_0F3A22_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, @@ -2540,8 +2333,8 @@ struct dis386 { 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise '!' => change condition from true to false or from false to true. '%' => add 1 upper case letter to the macro. - '^' => print 'w' or 'l' depending on operand size prefix or - suffix_always is true (lcall/ljmp). + '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size + prefix or suffix_always is true (lcall/ljmp). '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending on operand size prefix. '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction @@ -2587,7 +2380,7 @@ static const struct dis386 dis386[] = { { "orS", { Gv, EvS }, 0 }, { "orB", { AL, Ib }, 0 }, { "orS", { eAX, Iv }, 0 }, - { X86_64_TABLE (X86_64_0D) }, + { X86_64_TABLE (X86_64_0E) }, { Bad_Opcode }, /* 0x0f extended opcode escape */ /* 10 */ { "adcB", { Ebh1, Gb }, 0 }, @@ -2790,8 +2583,8 @@ static const struct dis386 dis386[] = { /* c0 */ { REG_TABLE (REG_C0) }, { REG_TABLE (REG_C1) }, - { "retT", { Iw, BND }, 0 }, - { "retT", { BND }, 0 }, + { X86_64_TABLE (X86_64_C2) }, + { X86_64_TABLE (X86_64_C3) }, { X86_64_TABLE (X86_64_C4) }, { X86_64_TABLE (X86_64_C5) }, { REG_TABLE (REG_C6) }, @@ -2894,7 +2687,7 @@ static const struct dis386 dis386_twobyte[] = { { "nopQ", { Ev }, 0 }, { PREFIX_TABLE (PREFIX_0F1A) }, { PREFIX_TABLE (PREFIX_0F1B) }, - { "nopQ", { Ev }, 0 }, + { PREFIX_TABLE (PREFIX_0F1C) }, { "nopQ", { Ev }, 0 }, { PREFIX_TABLE (PREFIX_0F1E) }, { "nopQ", { Ev }, 0 }, @@ -2921,8 +2714,8 @@ static const struct dis386 dis386_twobyte[] = { { "rdtsc", { XX }, 0 }, { "rdmsr", { XX }, 0 }, { "rdpmc", { XX }, 0 }, - { "sysenter", { XX }, 0 }, - { "sysexit", { XX }, 0 }, + { "sysenter", { SEP }, 0 }, + { "sysexit", { SEP }, 0 }, { Bad_Opcode }, { "getsec", { XX }, 0 }, /* 38 */ @@ -3646,7 +3439,18 @@ static const struct dis386 reg_table[][8] = { { MOD_TABLE (MOD_0F18_REG_6) }, { MOD_TABLE (MOD_0F18_REG_7) }, }, - /* REG_0F1E_MOD_3 */ + /* REG_0F1C_P_0_MOD_0 */ + { + { "cldemote", { Mb }, 0 }, + { "nopQ", { Ev }, 0 }, + { "nopQ", { Ev }, 0 }, + { "nopQ", { Ev }, 0 }, + { "nopQ", { Ev }, 0 }, + { "nopQ", { Ev }, 0 }, + { "nopQ", { Ev }, 0 }, + { "nopQ", { Ev }, 0 }, + }, + /* REG_0F1E_P_1_MOD_3 */ { { "nopQ", { Ev }, 0 }, { "rdsspK", { Rdq }, PREFIX_OPCODE }, @@ -3655,7 +3459,7 @@ static const struct dis386 reg_table[][8] = { { "nopQ", { Ev }, 0 }, { "nopQ", { Ev }, 0 }, { "nopQ", { Ev }, 0 }, - { RM_TABLE (RM_0F1E_MOD_3_REG_7) }, + { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) }, }, /* REG_0F71 */ { @@ -3788,33 +3592,32 @@ static const struct dis386 reg_table[][8] = { }, /* REG_XOP_LWP */ { - { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 }, - { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 }, + { "lwpins", { { OP_LWP_E, 0 }, Ed, Id }, 0 }, + { "lwpval", { { OP_LWP_E, 0 }, Ed, Id }, 0 }, }, /* REG_XOP_TBM_01 */ { { Bad_Opcode }, - { "blcfill", { { OP_LWP_E, 0 }, Ev }, 0 }, - { "blsfill", { { OP_LWP_E, 0 }, Ev }, 0 }, - { "blcs", { { OP_LWP_E, 0 }, Ev }, 0 }, - { "tzmsk", { { OP_LWP_E, 0 }, Ev }, 0 }, - { "blcic", { { OP_LWP_E, 0 }, Ev }, 0 }, - { "blsic", { { OP_LWP_E, 0 }, Ev }, 0 }, - { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 }, + { "blcfill", { { OP_LWP_E, 0 }, Edq }, 0 }, + { "blsfill", { { OP_LWP_E, 0 }, Edq }, 0 }, + { "blcs", { { OP_LWP_E, 0 }, Edq }, 0 }, + { "tzmsk", { { OP_LWP_E, 0 }, Edq }, 0 }, + { "blcic", { { OP_LWP_E, 0 }, Edq }, 0 }, + { "blsic", { { OP_LWP_E, 0 }, Edq }, 0 }, + { "t1mskc", { { OP_LWP_E, 0 }, Edq }, 0 }, }, /* REG_XOP_TBM_02 */ { { Bad_Opcode }, - { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 }, + { "blcmsk", { { OP_LWP_E, 0 }, Edq }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "blci", { { OP_LWP_E, 0 }, Ev }, 0 }, + { "blci", { { OP_LWP_E, 0 }, Edq }, 0 }, }, -#define NEED_REG_TABLE -#include "i386-dis-evex.h" -#undef NEED_REG_TABLE + +#include "i386-dis-evex-reg.h" }; static const struct dis386 prefix_table[][4] = { @@ -3826,24 +3629,53 @@ static const struct dis386 prefix_table[][4] = { { NULL, { { NULL, 0 } }, PREFIX_IGNORED } }, - /* PREFIX_MOD_0_0F01_REG_5 */ + /* PREFIX_0F01_REG_3_MOD_1 */ { + { "vmmcall", { Skip_MODRM }, 0 }, + { "vmgexit", { Skip_MODRM }, 0 }, { Bad_Opcode }, - { "rstorssp", { Mq }, PREFIX_OPCODE }, + { "vmgexit", { Skip_MODRM }, 0 }, }, - /* PREFIX_MOD_3_0F01_REG_5_RM_0 */ + /* PREFIX_0F01_REG_5_MOD_0 */ { { Bad_Opcode }, + { "rstorssp", { Mq }, PREFIX_OPCODE }, + }, + + /* PREFIX_0F01_REG_5_MOD_3_RM_0 */ + { + { "serialize", { Skip_MODRM }, PREFIX_OPCODE }, { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE }, + { Bad_Opcode }, + { "xsuspldtrk", { Skip_MODRM }, PREFIX_OPCODE }, + }, + + /* PREFIX_0F01_REG_5_MOD_3_RM_1 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { Bad_Opcode }, + { "xresldtrk", { Skip_MODRM }, PREFIX_OPCODE }, }, - /* PREFIX_MOD_3_0F01_REG_5_RM_2 */ + /* PREFIX_0F01_REG_5_MOD_3_RM_2 */ { { Bad_Opcode }, { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE }, }, + /* PREFIX_0F01_REG_7_MOD_3_RM_2 */ + { + { "monitorx", { { OP_Monitor, 0 } }, 0 }, + { "mcommit", { Skip_MODRM }, 0 }, + }, + + /* PREFIX_0F01_REG_7_MOD_3_RM_3 */ + { + { "mwaitx", { { OP_Mwait, eBX_reg } }, 0 }, + }, + /* PREFIX_0F09 */ { { "wbinvd", { XX }, 0 }, @@ -3897,6 +3729,14 @@ static const struct dis386 prefix_table[][4] = { { "bndcn", { Gbnd, Ev_bnd }, 0 }, }, + /* PREFIX_0F1C */ + { + { MOD_TABLE (MOD_0F1C_PREFIX_0) }, + { "nopQ", { Ev }, PREFIX_OPCODE }, + { "nopQ", { Ev }, PREFIX_OPCODE }, + { "nopQ", { Ev }, PREFIX_OPCODE }, + }, + /* PREFIX_0F1E */ { { "nopQ", { Ev }, PREFIX_OPCODE }, @@ -3908,9 +3748,9 @@ static const struct dis386 prefix_table[][4] = { /* PREFIX_0F2A */ { { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE }, - { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE }, + { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE }, { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE }, - { "cvtsi2sd%LQ", { XM, Ev }, 0 }, + { "cvtsi2sd%LQ", { XM, Edq }, 0 }, }, /* PREFIX_0F2B */ @@ -3924,17 +3764,17 @@ static const struct dis386 prefix_table[][4] = { /* PREFIX_0F2C */ { { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE }, - { "cvttss2si", { Gv, EXd }, PREFIX_OPCODE }, + { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE }, { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE }, - { "cvttsd2si", { Gv, EXq }, PREFIX_OPCODE }, + { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE }, }, /* PREFIX_0F2D */ { { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE }, - { "cvtss2si", { Gv, EXd }, PREFIX_OPCODE }, + { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE }, { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE }, - { "cvtsd2si", { Gv, EXq }, PREFIX_OPCODE }, + { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE }, }, /* PREFIX_0F2E */ @@ -4144,61 +3984,69 @@ static const struct dis386 prefix_table[][4] = { { "movdqa", { EXxS, XM }, PREFIX_OPCODE }, }, - /* PREFIX_0FAE_REG_0 */ + /* PREFIX_0FAE_REG_0_MOD_3 */ { { Bad_Opcode }, { "rdfsbase", { Ev }, 0 }, }, - /* PREFIX_0FAE_REG_1 */ + /* PREFIX_0FAE_REG_1_MOD_3 */ { { Bad_Opcode }, { "rdgsbase", { Ev }, 0 }, }, - /* PREFIX_0FAE_REG_2 */ + /* PREFIX_0FAE_REG_2_MOD_3 */ { { Bad_Opcode }, { "wrfsbase", { Ev }, 0 }, }, - /* PREFIX_0FAE_REG_3 */ + /* PREFIX_0FAE_REG_3_MOD_3 */ { { Bad_Opcode }, { "wrgsbase", { Ev }, 0 }, }, - /* PREFIX_MOD_0_0FAE_REG_4 */ + /* PREFIX_0FAE_REG_4_MOD_0 */ { { "xsave", { FXSAVE }, 0 }, { "ptwrite%LQ", { Edq }, 0 }, }, - /* PREFIX_MOD_3_0FAE_REG_4 */ + /* PREFIX_0FAE_REG_4_MOD_3 */ { { Bad_Opcode }, { "ptwrite%LQ", { Edq }, 0 }, }, - /* PREFIX_MOD_0_0FAE_REG_5 */ + /* PREFIX_0FAE_REG_5_MOD_0 */ { { "xrstor", { FXSAVE }, PREFIX_OPCODE }, }, - /* PREFIX_MOD_3_0FAE_REG_5 */ + /* PREFIX_0FAE_REG_5_MOD_3 */ { { "lfence", { Skip_MODRM }, 0 }, { "incsspK", { Rdq }, PREFIX_OPCODE }, }, - /* PREFIX_0FAE_REG_6 */ + /* PREFIX_0FAE_REG_6_MOD_0 */ { { "xsaveopt", { FXSAVE }, PREFIX_OPCODE }, { "clrssbsy", { Mq }, PREFIX_OPCODE }, { "clwb", { Mb }, PREFIX_OPCODE }, }, - /* PREFIX_0FAE_REG_7 */ + /* PREFIX_0FAE_REG_6_MOD_3 */ + { + { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) }, + { "umonitor", { Eva }, PREFIX_OPCODE }, + { "tpause", { Edq }, PREFIX_OPCODE }, + { "umwait", { Edq }, PREFIX_OPCODE }, + }, + + /* PREFIX_0FAE_REG_7_MOD_0 */ { { "clflush", { Mb }, 0 }, { Bad_Opcode }, @@ -4233,26 +4081,26 @@ static const struct dis386 prefix_table[][4] = { { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE }, }, - /* PREFIX_MOD_0_0FC3 */ + /* PREFIX_0FC3_MOD_0 */ { - { "movntiS", { Ev, Gv }, PREFIX_OPCODE }, + { "movntiS", { Edq, Gdq }, PREFIX_OPCODE }, }, - /* PREFIX_MOD_0_0FC7_REG_6 */ + /* PREFIX_0FC7_REG_6_MOD_0 */ { { "vmptrld",{ Mq }, 0 }, { "vmxon", { Mq }, 0 }, { "vmclear",{ Mq }, 0 }, }, - /* PREFIX_MOD_3_0FC7_REG_6 */ + /* PREFIX_0FC7_REG_6_MOD_3 */ { { "rdrand", { Ev }, 0 }, { Bad_Opcode }, { "rdrand", { Ev }, 0 } }, - /* PREFIX_MOD_3_0FC7_REG_7 */ + /* PREFIX_0FC7_REG_7_MOD_3 */ { { "rdseed", { Ev }, 0 }, { "rdpid", { Em }, 0 }, @@ -4646,6 +4494,19 @@ static const struct dis386 prefix_table[][4] = { { Bad_Opcode }, }, + /* PREFIX_0F38F8 */ + { + { Bad_Opcode }, + { MOD_TABLE (MOD_0F38F8_PREFIX_1) }, + { MOD_TABLE (MOD_0F38F8_PREFIX_2) }, + { MOD_TABLE (MOD_0F38F8_PREFIX_3) }, + }, + + /* PREFIX_0F38F9 */ + { + { MOD_TABLE (MOD_0F38F9_PREFIX_0) }, + }, + /* PREFIX_0F3A08 */ { { Bad_Opcode }, @@ -4828,71 +4689,71 @@ static const struct dis386 prefix_table[][4] = { /* PREFIX_VEX_0F10 */ { - { VEX_W_TABLE (VEX_W_0F10_P_0) }, - { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) }, - { VEX_W_TABLE (VEX_W_0F10_P_2) }, - { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) }, + { "vmovups", { XM, EXx }, 0 }, + { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 }, + { "vmovupd", { XM, EXx }, 0 }, + { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 }, }, /* PREFIX_VEX_0F11 */ { - { VEX_W_TABLE (VEX_W_0F11_P_0) }, - { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) }, - { VEX_W_TABLE (VEX_W_0F11_P_2) }, - { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) }, + { "vmovups", { EXxS, XM }, 0 }, + { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 }, + { "vmovupd", { EXxS, XM }, 0 }, + { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 }, }, /* PREFIX_VEX_0F12 */ { { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) }, - { VEX_W_TABLE (VEX_W_0F12_P_1) }, + { "vmovsldup", { XM, EXx }, 0 }, { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) }, - { VEX_W_TABLE (VEX_W_0F12_P_3) }, + { "vmovddup", { XM, EXymmq }, 0 }, }, /* PREFIX_VEX_0F16 */ { { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) }, - { VEX_W_TABLE (VEX_W_0F16_P_1) }, + { "vmovshdup", { XM, EXx }, 0 }, { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) }, }, /* PREFIX_VEX_0F2A */ { { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) }, + { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Edq }, 0 }, { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) }, + { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Edq }, 0 }, }, /* PREFIX_VEX_0F2C */ { { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) }, + { "vcvttss2si", { Gdq, EXdScalar }, 0 }, { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) }, + { "vcvttsd2si", { Gdq, EXqScalar }, 0 }, }, /* PREFIX_VEX_0F2D */ { { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) }, + { "vcvtss2si", { Gdq, EXdScalar }, 0 }, { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) }, + { "vcvtsd2si", { Gdq, EXqScalar }, 0 }, }, /* PREFIX_VEX_0F2E */ { - { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) }, + { "vucomiss", { XMScalar, EXdScalar }, 0 }, { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) }, + { "vucomisd", { XMScalar, EXqScalar }, 0 }, }, /* PREFIX_VEX_0F2F */ { - { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) }, + { "vcomiss", { XMScalar, EXdScalar }, 0 }, { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) }, + { "vcomisd", { XMScalar, EXqScalar }, 0 }, }, /* PREFIX_VEX_0F41 */ @@ -4953,183 +4814,183 @@ static const struct dis386 prefix_table[][4] = { /* PREFIX_VEX_0F51 */ { - { VEX_W_TABLE (VEX_W_0F51_P_0) }, - { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) }, - { VEX_W_TABLE (VEX_W_0F51_P_2) }, - { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) }, + { "vsqrtps", { XM, EXx }, 0 }, + { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, + { "vsqrtpd", { XM, EXx }, 0 }, + { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 }, }, /* PREFIX_VEX_0F52 */ { - { VEX_W_TABLE (VEX_W_0F52_P_0) }, - { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) }, + { "vrsqrtps", { XM, EXx }, 0 }, + { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, }, /* PREFIX_VEX_0F53 */ { - { VEX_W_TABLE (VEX_W_0F53_P_0) }, - { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) }, + { "vrcpps", { XM, EXx }, 0 }, + { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 }, }, /* PREFIX_VEX_0F58 */ { - { VEX_W_TABLE (VEX_W_0F58_P_0) }, - { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) }, - { VEX_W_TABLE (VEX_W_0F58_P_2) }, - { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) }, + { "vaddps", { XM, Vex, EXx }, 0 }, + { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 }, + { "vaddpd", { XM, Vex, EXx }, 0 }, + { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 }, }, /* PREFIX_VEX_0F59 */ { - { VEX_W_TABLE (VEX_W_0F59_P_0) }, - { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) }, - { VEX_W_TABLE (VEX_W_0F59_P_2) }, - { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) }, + { "vmulps", { XM, Vex, EXx }, 0 }, + { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 }, + { "vmulpd", { XM, Vex, EXx }, 0 }, + { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 }, }, /* PREFIX_VEX_0F5A */ { - { VEX_W_TABLE (VEX_W_0F5A_P_0) }, - { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) }, - { "vcvtpd2ps%XY", { XMM, EXx }, 0 }, - { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) }, + { "vcvtps2pd", { XM, EXxmmq }, 0 }, + { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 }, + { "vcvtpd2ps%XY",{ XMM, EXx }, 0 }, + { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 }, }, /* PREFIX_VEX_0F5B */ { - { VEX_W_TABLE (VEX_W_0F5B_P_0) }, - { VEX_W_TABLE (VEX_W_0F5B_P_1) }, - { VEX_W_TABLE (VEX_W_0F5B_P_2) }, + { "vcvtdq2ps", { XM, EXx }, 0 }, + { "vcvttps2dq", { XM, EXx }, 0 }, + { "vcvtps2dq", { XM, EXx }, 0 }, }, /* PREFIX_VEX_0F5C */ { - { VEX_W_TABLE (VEX_W_0F5C_P_0) }, - { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) }, - { VEX_W_TABLE (VEX_W_0F5C_P_2) }, - { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) }, + { "vsubps", { XM, Vex, EXx }, 0 }, + { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 }, + { "vsubpd", { XM, Vex, EXx }, 0 }, + { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 }, }, /* PREFIX_VEX_0F5D */ { - { VEX_W_TABLE (VEX_W_0F5D_P_0) }, - { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) }, - { VEX_W_TABLE (VEX_W_0F5D_P_2) }, - { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) }, + { "vminps", { XM, Vex, EXx }, 0 }, + { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 }, + { "vminpd", { XM, Vex, EXx }, 0 }, + { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 }, }, /* PREFIX_VEX_0F5E */ { - { VEX_W_TABLE (VEX_W_0F5E_P_0) }, - { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) }, - { VEX_W_TABLE (VEX_W_0F5E_P_2) }, - { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) }, + { "vdivps", { XM, Vex, EXx }, 0 }, + { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 }, + { "vdivpd", { XM, Vex, EXx }, 0 }, + { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 }, }, /* PREFIX_VEX_0F5F */ { - { VEX_W_TABLE (VEX_W_0F5F_P_0) }, - { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) }, - { VEX_W_TABLE (VEX_W_0F5F_P_2) }, - { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) }, + { "vmaxps", { XM, Vex, EXx }, 0 }, + { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 }, + { "vmaxpd", { XM, Vex, EXx }, 0 }, + { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 }, }, /* PREFIX_VEX_0F60 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F60_P_2) }, + { "vpunpcklbw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F61 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F61_P_2) }, + { "vpunpcklwd", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F62 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F62_P_2) }, + { "vpunpckldq", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F63 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F63_P_2) }, + { "vpacksswb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F64 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F64_P_2) }, + { "vpcmpgtb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F65 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F65_P_2) }, + { "vpcmpgtw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F66 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F66_P_2) }, + { "vpcmpgtd", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F67 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F67_P_2) }, + { "vpackuswb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F68 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F68_P_2) }, + { "vpunpckhbw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F69 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F69_P_2) }, + { "vpunpckhwd", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F6A */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F6A_P_2) }, + { "vpunpckhdq", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F6B */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F6B_P_2) }, + { "vpackssdw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F6C */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F6C_P_2) }, + { "vpunpcklqdq", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F6D */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F6D_P_2) }, + { "vpunpckhqdq", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F6E */ @@ -5142,128 +5003,128 @@ static const struct dis386 prefix_table[][4] = { /* PREFIX_VEX_0F6F */ { { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F6F_P_1) }, - { VEX_W_TABLE (VEX_W_0F6F_P_2) }, + { "vmovdqu", { XM, EXx }, 0 }, + { "vmovdqa", { XM, EXx }, 0 }, }, /* PREFIX_VEX_0F70 */ { { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F70_P_1) }, - { VEX_W_TABLE (VEX_W_0F70_P_2) }, - { VEX_W_TABLE (VEX_W_0F70_P_3) }, + { "vpshufhw", { XM, EXx, Ib }, 0 }, + { "vpshufd", { XM, EXx, Ib }, 0 }, + { "vpshuflw", { XM, EXx, Ib }, 0 }, }, /* PREFIX_VEX_0F71_REG_2 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) }, + { "vpsrlw", { Vex, XS, Ib }, 0 }, }, /* PREFIX_VEX_0F71_REG_4 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) }, + { "vpsraw", { Vex, XS, Ib }, 0 }, }, /* PREFIX_VEX_0F71_REG_6 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) }, + { "vpsllw", { Vex, XS, Ib }, 0 }, }, /* PREFIX_VEX_0F72_REG_2 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) }, + { "vpsrld", { Vex, XS, Ib }, 0 }, }, /* PREFIX_VEX_0F72_REG_4 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) }, + { "vpsrad", { Vex, XS, Ib }, 0 }, }, /* PREFIX_VEX_0F72_REG_6 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) }, + { "vpslld", { Vex, XS, Ib }, 0 }, }, /* PREFIX_VEX_0F73_REG_2 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) }, + { "vpsrlq", { Vex, XS, Ib }, 0 }, }, /* PREFIX_VEX_0F73_REG_3 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) }, + { "vpsrldq", { Vex, XS, Ib }, 0 }, }, /* PREFIX_VEX_0F73_REG_6 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) }, + { "vpsllq", { Vex, XS, Ib }, 0 }, }, /* PREFIX_VEX_0F73_REG_7 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) }, + { "vpslldq", { Vex, XS, Ib }, 0 }, }, /* PREFIX_VEX_0F74 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F74_P_2) }, + { "vpcmpeqb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F75 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F75_P_2) }, + { "vpcmpeqw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F76 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F76_P_2) }, + { "vpcmpeqd", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F77 */ { - { VEX_W_TABLE (VEX_W_0F77_P_0) }, + { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) }, }, /* PREFIX_VEX_0F7C */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F7C_P_2) }, - { VEX_W_TABLE (VEX_W_0F7C_P_3) }, + { "vhaddpd", { XM, Vex, EXx }, 0 }, + { "vhaddps", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F7D */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F7D_P_2) }, - { VEX_W_TABLE (VEX_W_0F7D_P_3) }, + { "vhsubpd", { XM, Vex, EXx }, 0 }, + { "vhsubps", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F7E */ @@ -5276,8 +5137,8 @@ static const struct dis386 prefix_table[][4] = { /* PREFIX_VEX_0F7F */ { { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F7F_P_1) }, - { VEX_W_TABLE (VEX_W_0F7F_P_2) }, + { "vmovdqu", { EXxS, XM }, 0 }, + { "vmovdqa", { EXxS, XM }, 0 }, }, /* PREFIX_VEX_0F90 */ @@ -5326,10 +5187,10 @@ static const struct dis386 prefix_table[][4] = { /* PREFIX_VEX_0FC2 */ { - { VEX_W_TABLE (VEX_W_0FC2_P_0) }, - { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) }, - { VEX_W_TABLE (VEX_W_0FC2_P_2) }, - { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) }, + { "vcmpps", { XM, Vex, EXx, VCMP }, 0 }, + { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 }, + { "vcmppd", { XM, Vex, EXx, VCMP }, 0 }, + { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 }, }, /* PREFIX_VEX_0FC4 */ @@ -5350,43 +5211,43 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FD0_P_2) }, - { VEX_W_TABLE (VEX_W_0FD0_P_3) }, + { "vaddsubpd", { XM, Vex, EXx }, 0 }, + { "vaddsubps", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FD1 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FD1_P_2) }, + { "vpsrlw", { XM, Vex, EXxmm }, 0 }, }, /* PREFIX_VEX_0FD2 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FD2_P_2) }, + { "vpsrld", { XM, Vex, EXxmm }, 0 }, }, /* PREFIX_VEX_0FD3 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FD3_P_2) }, + { "vpsrlq", { XM, Vex, EXxmm }, 0 }, }, /* PREFIX_VEX_0FD4 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FD4_P_2) }, + { "vpaddq", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FD5 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FD5_P_2) }, + { "vpmullw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FD6 */ @@ -5407,106 +5268,106 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FD8_P_2) }, + { "vpsubusb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FD9 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FD9_P_2) }, + { "vpsubusw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FDA */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FDA_P_2) }, + { "vpminub", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FDB */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FDB_P_2) }, + { "vpand", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FDC */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FDC_P_2) }, + { "vpaddusb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FDD */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FDD_P_2) }, + { "vpaddusw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FDE */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FDE_P_2) }, + { "vpmaxub", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FDF */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FDF_P_2) }, + { "vpandn", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FE0 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FE0_P_2) }, + { "vpavgb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FE1 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FE1_P_2) }, + { "vpsraw", { XM, Vex, EXxmm }, 0 }, }, /* PREFIX_VEX_0FE2 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FE2_P_2) }, + { "vpsrad", { XM, Vex, EXxmm }, 0 }, }, /* PREFIX_VEX_0FE3 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FE3_P_2) }, + { "vpavgw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FE4 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FE4_P_2) }, + { "vpmulhuw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FE5 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FE5_P_2) }, + { "vpmulhw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FE6 */ { { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FE6_P_1) }, - { VEX_W_TABLE (VEX_W_0FE6_P_2) }, - { VEX_W_TABLE (VEX_W_0FE6_P_3) }, + { "vcvtdq2pd", { XM, EXxmmq }, 0 }, + { "vcvttpd2dq%XY", { XMM, EXx }, 0 }, + { "vcvtpd2dq%XY", { XMM, EXx }, 0 }, }, /* PREFIX_VEX_0FE7 */ @@ -5520,56 +5381,56 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FE8_P_2) }, + { "vpsubsb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FE9 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FE9_P_2) }, + { "vpsubsw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FEA */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FEA_P_2) }, + { "vpminsw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FEB */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FEB_P_2) }, + { "vpor", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FEC */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FEC_P_2) }, + { "vpaddsb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FED */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FED_P_2) }, + { "vpaddsw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FEE */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FEE_P_2) }, + { "vpmaxsw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FEF */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FEF_P_2) }, + { "vpxor", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FF0 */ @@ -5584,42 +5445,42 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FF1_P_2) }, + { "vpsllw", { XM, Vex, EXxmm }, 0 }, }, /* PREFIX_VEX_0FF2 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FF2_P_2) }, + { "vpslld", { XM, Vex, EXxmm }, 0 }, }, /* PREFIX_VEX_0FF3 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FF3_P_2) }, + { "vpsllq", { XM, Vex, EXxmm }, 0 }, }, /* PREFIX_VEX_0FF4 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FF4_P_2) }, + { "vpmuludq", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FF5 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FF5_P_2) }, + { "vpmaddwd", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FF6 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FF6_P_2) }, + { "vpsadbw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FF7 */ @@ -5633,133 +5494,133 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FF8_P_2) }, + { "vpsubb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FF9 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FF9_P_2) }, + { "vpsubw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FFA */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FFA_P_2) }, + { "vpsubd", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FFB */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FFB_P_2) }, + { "vpsubq", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FFC */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FFC_P_2) }, + { "vpaddb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FFD */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FFD_P_2) }, + { "vpaddw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0FFE */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FFE_P_2) }, + { "vpaddd", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3800 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3800_P_2) }, + { "vpshufb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3801 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3801_P_2) }, + { "vphaddw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3802 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3802_P_2) }, + { "vphaddd", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3803 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3803_P_2) }, + { "vphaddsw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3804 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3804_P_2) }, + { "vpmaddubsw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3805 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3805_P_2) }, + { "vphsubw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3806 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3806_P_2) }, + { "vphsubd", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3807 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3807_P_2) }, + { "vphsubsw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3808 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3808_P_2) }, + { "vpsignb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3809 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3809_P_2) }, + { "vpsignw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F380A */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F380A_P_2) }, + { "vpsignd", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F380B */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F380B_P_2) }, + { "vpmulhrsw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F380C */ @@ -5808,7 +5669,7 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3817_P_2) }, + { "vptest", { XM, EXx }, 0 }, }, /* PREFIX_VEX_0F3818 */ @@ -5836,77 +5697,77 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F381C_P_2) }, + { "vpabsb", { XM, EXx }, 0 }, }, /* PREFIX_VEX_0F381D */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F381D_P_2) }, + { "vpabsw", { XM, EXx }, 0 }, }, /* PREFIX_VEX_0F381E */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F381E_P_2) }, + { "vpabsd", { XM, EXx }, 0 }, }, /* PREFIX_VEX_0F3820 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3820_P_2) }, + { "vpmovsxbw", { XM, EXxmmq }, 0 }, }, /* PREFIX_VEX_0F3821 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3821_P_2) }, + { "vpmovsxbd", { XM, EXxmmqd }, 0 }, }, /* PREFIX_VEX_0F3822 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3822_P_2) }, + { "vpmovsxbq", { XM, EXxmmdw }, 0 }, }, /* PREFIX_VEX_0F3823 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3823_P_2) }, + { "vpmovsxwd", { XM, EXxmmq }, 0 }, }, /* PREFIX_VEX_0F3824 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3824_P_2) }, + { "vpmovsxwq", { XM, EXxmmqd }, 0 }, }, /* PREFIX_VEX_0F3825 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3825_P_2) }, + { "vpmovsxdq", { XM, EXxmmq }, 0 }, }, /* PREFIX_VEX_0F3828 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3828_P_2) }, + { "vpmuldq", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3829 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3829_P_2) }, + { "vpcmpeqq", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F382A */ @@ -5920,7 +5781,7 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F382B_P_2) }, + { "vpackusdw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F382C */ @@ -5955,42 +5816,42 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3830_P_2) }, + { "vpmovzxbw", { XM, EXxmmq }, 0 }, }, /* PREFIX_VEX_0F3831 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3831_P_2) }, + { "vpmovzxbd", { XM, EXxmmqd }, 0 }, }, /* PREFIX_VEX_0F3832 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3832_P_2) }, + { "vpmovzxbq", { XM, EXxmmdw }, 0 }, }, /* PREFIX_VEX_0F3833 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3833_P_2) }, + { "vpmovzxwd", { XM, EXxmmq }, 0 }, }, /* PREFIX_VEX_0F3834 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3834_P_2) }, + { "vpmovzxwq", { XM, EXxmmqd }, 0 }, }, /* PREFIX_VEX_0F3835 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3835_P_2) }, + { "vpmovzxdq", { XM, EXxmmq }, 0 }, }, /* PREFIX_VEX_0F3836 */ @@ -6004,70 +5865,70 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3837_P_2) }, + { "vpcmpgtq", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3838 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3838_P_2) }, + { "vpminsb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3839 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3839_P_2) }, + { "vpminsd", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F383A */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F383A_P_2) }, + { "vpminuw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F383B */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F383B_P_2) }, + { "vpminud", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F383C */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F383C_P_2) }, + { "vpmaxsb", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F383D */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F383D_P_2) }, + { "vpmaxsd", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F383E */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F383E_P_2) }, + { "vpmaxuw", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F383F */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F383F_P_2) }, + { "vpmaxud", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3840 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3840_P_2) }, + { "vpmulld", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F3841 */ @@ -6518,56 +6379,56 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3A08_P_2) }, + { "vroundps", { XM, EXx, Ib }, 0 }, }, /* PREFIX_VEX_0F3A09 */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3A09_P_2) }, + { "vroundpd", { XM, EXx, Ib }, 0 }, }, /* PREFIX_VEX_0F3A0A */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) }, + { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 }, }, /* PREFIX_VEX_0F3A0B */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) }, + { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 }, }, /* PREFIX_VEX_0F3A0C */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3A0C_P_2) }, + { "vblendps", { XM, Vex, EXx, Ib }, 0 }, }, /* PREFIX_VEX_0F3A0D */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3A0D_P_2) }, + { "vblendpd", { XM, Vex, EXx, Ib }, 0 }, }, /* PREFIX_VEX_0F3A0E */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3A0E_P_2) }, + { "vpblendw", { XM, Vex, EXx, Ib }, 0 }, }, /* PREFIX_VEX_0F3A0F */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3A0F_P_2) }, + { "vpalignr", { XM, Vex, EXx, Ib }, 0 }, }, /* PREFIX_VEX_0F3A14 */ @@ -6686,7 +6547,7 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3A40_P_2) }, + { "vdpps", { XM, Vex, EXx, Ib }, 0 }, }, /* PREFIX_VEX_0F3A41 */ @@ -6700,7 +6561,7 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F3A42_P_2) }, + { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 }, }, /* PREFIX_VEX_0F3A44 */ @@ -6951,9 +6812,7 @@ static const struct dis386 prefix_table[][4] = { { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) }, }, -#define NEED_PREFIX_TABLE -#include "i386-dis-evex.h" -#undef NEED_PREFIX_TABLE +#include "i386-dis-evex-prefix.h" }; static const struct dis386 x86_64_table[][2] = { @@ -6967,7 +6826,7 @@ static const struct dis386 x86_64_table[][2] = { { "popP", { es }, 0 }, }, - /* X86_64_0D */ + /* X86_64_0E */ { { "pushP", { cs }, 0 }, }, @@ -7031,7 +6890,7 @@ static const struct dis386 x86_64_table[][2] = { /* X86_64_63 */ { { "arpl", { Ew, Gw }, 0 }, - { "movs{lq|xd}", { Gv, Ed }, 0 }, + { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 }, }, /* X86_64_6D */ @@ -7057,6 +6916,18 @@ static const struct dis386 x86_64_table[][2] = { { "Jcall{T|}", { Ap }, 0 }, }, + /* X86_64_C2 */ + { + { "retP", { Iw, BND }, 0 }, + { "ret@", { Iw, BND }, 0 }, + }, + + /* X86_64_C3 */ + { + { "retP", { BND }, 0 }, + { "ret@", { BND }, 0 }, + }, + /* X86_64_C4 */ { { MOD_TABLE (MOD_C4_32BIT) }, @@ -7410,8 +7281,8 @@ static const struct dis386 three_byte_table[][256] = { { PREFIX_TABLE (PREFIX_0F38F6) }, { Bad_Opcode }, /* f8 */ - { Bad_Opcode }, - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_0F38F8) }, + { PREFIX_TABLE (PREFIX_0F38F9) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -8316,7 +8187,7 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* 10 */ - { "bextr", { Gv, Ev, Iq }, 0 }, + { "bextrS", { Gdq, Edq, Id }, 0 }, { Bad_Opcode }, { REG_TABLE (REG_XOP_LWP) }, { Bad_Opcode }, @@ -8614,8 +8485,8 @@ static const struct dis386 vex_table[][256] = { { PREFIX_TABLE (PREFIX_VEX_0F11) }, { PREFIX_TABLE (PREFIX_VEX_0F12) }, { MOD_TABLE (MOD_VEX_0F13) }, - { VEX_W_TABLE (VEX_W_0F14) }, - { VEX_W_TABLE (VEX_W_0F15) }, + { "vunpcklpX", { XM, Vex, EXx }, 0 }, + { "vunpckhpX", { XM, Vex, EXx }, 0 }, { PREFIX_TABLE (PREFIX_VEX_0F16) }, { MOD_TABLE (MOD_VEX_0F17) }, /* 18 */ @@ -8637,8 +8508,8 @@ static const struct dis386 vex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* 28 */ - { VEX_W_TABLE (VEX_W_0F28) }, - { VEX_W_TABLE (VEX_W_0F29) }, + { "vmovapX", { XM, EXx }, 0 }, + { "vmovapX", { EXxS, XM }, 0 }, { PREFIX_TABLE (PREFIX_VEX_0F2A) }, { MOD_TABLE (MOD_VEX_0F2B) }, { PREFIX_TABLE (PREFIX_VEX_0F2C) }, @@ -9464,132 +9335,47 @@ static const struct dis386 vex_table[][256] = { }, }; -#define NEED_OPCODE_TABLE #include "i386-dis-evex.h" -#undef NEED_OPCODE_TABLE -static const struct dis386 vex_len_table[][2] = { - /* VEX_LEN_0F10_P_1 */ - { - { VEX_W_TABLE (VEX_W_0F10_P_1) }, - { VEX_W_TABLE (VEX_W_0F10_P_1) }, - }, - - /* VEX_LEN_0F10_P_3 */ - { - { VEX_W_TABLE (VEX_W_0F10_P_3) }, - { VEX_W_TABLE (VEX_W_0F10_P_3) }, - }, - - /* VEX_LEN_0F11_P_1 */ - { - { VEX_W_TABLE (VEX_W_0F11_P_1) }, - { VEX_W_TABLE (VEX_W_0F11_P_1) }, - }, - - /* VEX_LEN_0F11_P_3 */ - { - { VEX_W_TABLE (VEX_W_0F11_P_3) }, - { VEX_W_TABLE (VEX_W_0F11_P_3) }, - }, +static const struct dis386 vex_len_table[][2] = { /* VEX_LEN_0F12_P_0_M_0 */ { - { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) }, + { "vmovlps", { XM, Vex128, EXq }, 0 }, }, /* VEX_LEN_0F12_P_0_M_1 */ { - { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) }, + { "vmovhlps", { XM, Vex128, EXq }, 0 }, }, /* VEX_LEN_0F12_P_2 */ { - { VEX_W_TABLE (VEX_W_0F12_P_2) }, + { "vmovlpd", { XM, Vex128, EXq }, 0 }, }, /* VEX_LEN_0F13_M_0 */ { - { VEX_W_TABLE (VEX_W_0F13_M_0) }, + { "vmovlpX", { EXq, XM }, 0 }, }, /* VEX_LEN_0F16_P_0_M_0 */ { - { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) }, + { "vmovhps", { XM, Vex128, EXq }, 0 }, }, /* VEX_LEN_0F16_P_0_M_1 */ { - { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) }, + { "vmovlhps", { XM, Vex128, EXq }, 0 }, }, /* VEX_LEN_0F16_P_2 */ { - { VEX_W_TABLE (VEX_W_0F16_P_2) }, + { "vmovhpd", { XM, Vex128, EXq }, 0 }, }, /* VEX_LEN_0F17_M_0 */ { - { VEX_W_TABLE (VEX_W_0F17_M_0) }, - }, - - /* VEX_LEN_0F2A_P_1 */ - { - { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 }, - { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 }, - }, - - /* VEX_LEN_0F2A_P_3 */ - { - { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 }, - { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 }, - }, - - /* VEX_LEN_0F2C_P_1 */ - { - { "vcvttss2si", { Gv, EXdScalar }, 0 }, - { "vcvttss2si", { Gv, EXdScalar }, 0 }, - }, - - /* VEX_LEN_0F2C_P_3 */ - { - { "vcvttsd2si", { Gv, EXqScalar }, 0 }, - { "vcvttsd2si", { Gv, EXqScalar }, 0 }, - }, - - /* VEX_LEN_0F2D_P_1 */ - { - { "vcvtss2si", { Gv, EXdScalar }, 0 }, - { "vcvtss2si", { Gv, EXdScalar }, 0 }, - }, - - /* VEX_LEN_0F2D_P_3 */ - { - { "vcvtsd2si", { Gv, EXqScalar }, 0 }, - { "vcvtsd2si", { Gv, EXqScalar }, 0 }, - }, - - /* VEX_LEN_0F2E_P_0 */ - { - { VEX_W_TABLE (VEX_W_0F2E_P_0) }, - { VEX_W_TABLE (VEX_W_0F2E_P_0) }, - }, - - /* VEX_LEN_0F2E_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F2E_P_2) }, - { VEX_W_TABLE (VEX_W_0F2E_P_2) }, - }, - - /* VEX_LEN_0F2F_P_0 */ - { - { VEX_W_TABLE (VEX_W_0F2F_P_0) }, - { VEX_W_TABLE (VEX_W_0F2F_P_0) }, - }, - - /* VEX_LEN_0F2F_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F2F_P_2) }, - { VEX_W_TABLE (VEX_W_0F2F_P_2) }, + { "vmovhpX", { EXq, XM }, 0 }, }, /* VEX_LEN_0F41_P_0 */ @@ -9671,130 +9457,25 @@ static const struct dis386 vex_len_table[][2] = { { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) }, }, - /* VEX_LEN_0F51_P_1 */ - { - { VEX_W_TABLE (VEX_W_0F51_P_1) }, - { VEX_W_TABLE (VEX_W_0F51_P_1) }, - }, - - /* VEX_LEN_0F51_P_3 */ - { - { VEX_W_TABLE (VEX_W_0F51_P_3) }, - { VEX_W_TABLE (VEX_W_0F51_P_3) }, - }, - - /* VEX_LEN_0F52_P_1 */ - { - { VEX_W_TABLE (VEX_W_0F52_P_1) }, - { VEX_W_TABLE (VEX_W_0F52_P_1) }, - }, - - /* VEX_LEN_0F53_P_1 */ - { - { VEX_W_TABLE (VEX_W_0F53_P_1) }, - { VEX_W_TABLE (VEX_W_0F53_P_1) }, - }, - - /* VEX_LEN_0F58_P_1 */ - { - { VEX_W_TABLE (VEX_W_0F58_P_1) }, - { VEX_W_TABLE (VEX_W_0F58_P_1) }, - }, - - /* VEX_LEN_0F58_P_3 */ - { - { VEX_W_TABLE (VEX_W_0F58_P_3) }, - { VEX_W_TABLE (VEX_W_0F58_P_3) }, - }, - - /* VEX_LEN_0F59_P_1 */ - { - { VEX_W_TABLE (VEX_W_0F59_P_1) }, - { VEX_W_TABLE (VEX_W_0F59_P_1) }, - }, - - /* VEX_LEN_0F59_P_3 */ - { - { VEX_W_TABLE (VEX_W_0F59_P_3) }, - { VEX_W_TABLE (VEX_W_0F59_P_3) }, - }, - - /* VEX_LEN_0F5A_P_1 */ - { - { VEX_W_TABLE (VEX_W_0F5A_P_1) }, - { VEX_W_TABLE (VEX_W_0F5A_P_1) }, - }, - - /* VEX_LEN_0F5A_P_3 */ - { - { VEX_W_TABLE (VEX_W_0F5A_P_3) }, - { VEX_W_TABLE (VEX_W_0F5A_P_3) }, - }, - - /* VEX_LEN_0F5C_P_1 */ - { - { VEX_W_TABLE (VEX_W_0F5C_P_1) }, - { VEX_W_TABLE (VEX_W_0F5C_P_1) }, - }, - - /* VEX_LEN_0F5C_P_3 */ - { - { VEX_W_TABLE (VEX_W_0F5C_P_3) }, - { VEX_W_TABLE (VEX_W_0F5C_P_3) }, - }, - - /* VEX_LEN_0F5D_P_1 */ - { - { VEX_W_TABLE (VEX_W_0F5D_P_1) }, - { VEX_W_TABLE (VEX_W_0F5D_P_1) }, - }, - - /* VEX_LEN_0F5D_P_3 */ - { - { VEX_W_TABLE (VEX_W_0F5D_P_3) }, - { VEX_W_TABLE (VEX_W_0F5D_P_3) }, - }, - - /* VEX_LEN_0F5E_P_1 */ - { - { VEX_W_TABLE (VEX_W_0F5E_P_1) }, - { VEX_W_TABLE (VEX_W_0F5E_P_1) }, - }, - - /* VEX_LEN_0F5E_P_3 */ - { - { VEX_W_TABLE (VEX_W_0F5E_P_3) }, - { VEX_W_TABLE (VEX_W_0F5E_P_3) }, - }, - - /* VEX_LEN_0F5F_P_1 */ - { - { VEX_W_TABLE (VEX_W_0F5F_P_1) }, - { VEX_W_TABLE (VEX_W_0F5F_P_1) }, - }, - - /* VEX_LEN_0F5F_P_3 */ + /* VEX_LEN_0F6E_P_2 */ { - { VEX_W_TABLE (VEX_W_0F5F_P_3) }, - { VEX_W_TABLE (VEX_W_0F5F_P_3) }, + { "vmovK", { XMScalar, Edq }, 0 }, }, - /* VEX_LEN_0F6E_P_2 */ + /* VEX_LEN_0F77_P_1 */ { - { "vmovK", { XMScalar, Edq }, 0 }, - { "vmovK", { XMScalar, Edq }, 0 }, + { "vzeroupper", { XX }, 0 }, + { "vzeroall", { XX }, 0 }, }, /* VEX_LEN_0F7E_P_1 */ { - { VEX_W_TABLE (VEX_W_0F7E_P_1) }, - { VEX_W_TABLE (VEX_W_0F7E_P_1) }, + { "vmovq", { XMScalar, EXqScalar }, 0 }, }, /* VEX_LEN_0F7E_P_2 */ { { "vmovK", { Edq, XMScalar }, 0 }, - { "vmovK", { Edq, XMScalar }, 0 }, }, /* VEX_LEN_0F90_P_0 */ @@ -9829,7 +9510,7 @@ static const struct dis386 vex_len_table[][2] = { /* VEX_LEN_0F92_P_3 */ { - { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) }, + { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) }, }, /* VEX_LEN_0F93_P_0 */ @@ -9844,7 +9525,7 @@ static const struct dis386 vex_len_table[][2] = { /* VEX_LEN_0F93_P_3 */ { - { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) }, + { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) }, }, /* VEX_LEN_0F98_P_0 */ @@ -9869,45 +9550,32 @@ static const struct dis386 vex_len_table[][2] = { /* VEX_LEN_0FAE_R_2_M_0 */ { - { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) }, + { "vldmxcsr", { Md }, 0 }, }, /* VEX_LEN_0FAE_R_3_M_0 */ { - { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) }, - }, - - /* VEX_LEN_0FC2_P_1 */ - { - { VEX_W_TABLE (VEX_W_0FC2_P_1) }, - { VEX_W_TABLE (VEX_W_0FC2_P_1) }, - }, - - /* VEX_LEN_0FC2_P_3 */ - { - { VEX_W_TABLE (VEX_W_0FC2_P_3) }, - { VEX_W_TABLE (VEX_W_0FC2_P_3) }, + { "vstmxcsr", { Md }, 0 }, }, /* VEX_LEN_0FC4_P_2 */ { - { VEX_W_TABLE (VEX_W_0FC4_P_2) }, + { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 }, }, /* VEX_LEN_0FC5_P_2 */ { - { VEX_W_TABLE (VEX_W_0FC5_P_2) }, + { "vpextrw", { Gdq, XS, Ib }, 0 }, }, /* VEX_LEN_0FD6_P_2 */ { - { VEX_W_TABLE (VEX_W_0FD6_P_2) }, - { VEX_W_TABLE (VEX_W_0FD6_P_2) }, + { "vmovq", { EXqScalarS, XMScalar }, 0 }, }, /* VEX_LEN_0FF7_P_2 */ { - { VEX_W_TABLE (VEX_W_0FF7_P_2) }, + { "vmaskmovdqu", { XM, XS }, 0 }, }, /* VEX_LEN_0F3816_P_2 */ @@ -9936,7 +9604,7 @@ static const struct dis386 vex_len_table[][2] = { /* VEX_LEN_0F3841_P_2 */ { - { VEX_W_TABLE (VEX_W_0F3841_P_2) }, + { "vphminposuw", { XM, EXx }, 0 }, }, /* VEX_LEN_0F385A_P_2_M_0 */ @@ -9947,7 +9615,7 @@ static const struct dis386 vex_len_table[][2] = { /* VEX_LEN_0F38DB_P_2 */ { - { VEX_W_TABLE (VEX_W_0F38DB_P_2) }, + { "vaesimc", { XM, EXx }, 0 }, }, /* VEX_LEN_0F38F2_P_0 */ @@ -10028,26 +9696,14 @@ static const struct dis386 vex_len_table[][2] = { { VEX_W_TABLE (VEX_W_0F3A06_P_2) }, }, - /* VEX_LEN_0F3A0A_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, - { VEX_W_TABLE (VEX_W_0F3A0A_P_2) }, - }, - - /* VEX_LEN_0F3A0B_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, - { VEX_W_TABLE (VEX_W_0F3A0B_P_2) }, - }, - /* VEX_LEN_0F3A14_P_2 */ { - { VEX_W_TABLE (VEX_W_0F3A14_P_2) }, + { "vpextrb", { Edqb, XM, Ib }, 0 }, }, /* VEX_LEN_0F3A15_P_2 */ { - { VEX_W_TABLE (VEX_W_0F3A15_P_2) }, + { "vpextrw", { Edqw, XM, Ib }, 0 }, }, /* VEX_LEN_0F3A16_P_2 */ @@ -10074,12 +9730,12 @@ static const struct dis386 vex_len_table[][2] = { /* VEX_LEN_0F3A20_P_2 */ { - { VEX_W_TABLE (VEX_W_0F3A20_P_2) }, + { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 }, }, /* VEX_LEN_0F3A21_P_2 */ { - { VEX_W_TABLE (VEX_W_0F3A21_P_2) }, + { "vinsertps", { XM, Vex128, EXd, Ib }, 0 }, }, /* VEX_LEN_0F3A22_P_2 */ @@ -10121,7 +9777,7 @@ static const struct dis386 vex_len_table[][2] = { /* VEX_LEN_0F3A41_P_2 */ { - { VEX_W_TABLE (VEX_W_0F3A41_P_2) }, + { "vdppd", { XM, Vex128, EXx, Ib }, 0 }, }, /* VEX_LEN_0F3A46_P_2 */ @@ -10142,12 +9798,12 @@ static const struct dis386 vex_len_table[][2] = { /* VEX_LEN_0F3A62_P_2 */ { - { VEX_W_TABLE (VEX_W_0F3A62_P_2) }, + { "vpcmpistrm", { XM, EXx, Ib }, 0 }, }, /* VEX_LEN_0F3A63_P_2 */ { - { VEX_W_TABLE (VEX_W_0F3A63_P_2) }, + { "vpcmpistri", { XM, EXx, Ib }, 0 }, }, /* VEX_LEN_0F3A6A_P_2 */ @@ -10192,7 +9848,7 @@ static const struct dis386 vex_len_table[][2] = { /* VEX_LEN_0F3ADF_P_2 */ { - { VEX_W_TABLE (VEX_W_0F3ADF_P_2) }, + { "vaeskeygenassist", { XM, EXx, Ib }, 0 }, }, /* VEX_LEN_0F3AF0_P_3 */ @@ -10253,119 +9909,9 @@ static const struct dis386 vex_len_table[][2] = { }, }; +#include "i386-dis-evex-len.h" + static const struct dis386 vex_w_table[][2] = { - { - /* VEX_W_0F10_P_0 */ - { "vmovups", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F10_P_1 */ - { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 }, - }, - { - /* VEX_W_0F10_P_2 */ - { "vmovupd", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F10_P_3 */ - { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 }, - }, - { - /* VEX_W_0F11_P_0 */ - { "vmovups", { EXxS, XM }, 0 }, - }, - { - /* VEX_W_0F11_P_1 */ - { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 }, - }, - { - /* VEX_W_0F11_P_2 */ - { "vmovupd", { EXxS, XM }, 0 }, - }, - { - /* VEX_W_0F11_P_3 */ - { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 }, - }, - { - /* VEX_W_0F12_P_0_M_0 */ - { "vmovlps", { XM, Vex128, EXq }, 0 }, - }, - { - /* VEX_W_0F12_P_0_M_1 */ - { "vmovhlps", { XM, Vex128, EXq }, 0 }, - }, - { - /* VEX_W_0F12_P_1 */ - { "vmovsldup", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F12_P_2 */ - { "vmovlpd", { XM, Vex128, EXq }, 0 }, - }, - { - /* VEX_W_0F12_P_3 */ - { "vmovddup", { XM, EXymmq }, 0 }, - }, - { - /* VEX_W_0F13_M_0 */ - { "vmovlpX", { EXq, XM }, 0 }, - }, - { - /* VEX_W_0F14 */ - { "vunpcklpX", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F15 */ - { "vunpckhpX", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F16_P_0_M_0 */ - { "vmovhps", { XM, Vex128, EXq }, 0 }, - }, - { - /* VEX_W_0F16_P_0_M_1 */ - { "vmovlhps", { XM, Vex128, EXq }, 0 }, - }, - { - /* VEX_W_0F16_P_1 */ - { "vmovshdup", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F16_P_2 */ - { "vmovhpd", { XM, Vex128, EXq }, 0 }, - }, - { - /* VEX_W_0F17_M_0 */ - { "vmovhpX", { EXq, XM }, 0 }, - }, - { - /* VEX_W_0F28 */ - { "vmovapX", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F29 */ - { "vmovapX", { EXxS, XM }, 0 }, - }, - { - /* VEX_W_0F2B_M_0 */ - { "vmovntpX", { Mx, XM }, 0 }, - }, - { - /* VEX_W_0F2E_P_0 */ - { "vucomiss", { XMScalar, EXdScalar }, 0 }, - }, - { - /* VEX_W_0F2E_P_2 */ - { "vucomisd", { XMScalar, EXqScalar }, 0 }, - }, - { - /* VEX_W_0F2F_P_0 */ - { "vcomiss", { XMScalar, EXdScalar }, 0 }, - }, - { - /* VEX_W_0F2F_P_2 */ - { "vcomisd", { XMScalar, EXqScalar }, 0 }, - }, { /* VEX_W_0F41_P_0_LEN_1 */ { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) }, @@ -10446,666 +9992,60 @@ static const struct dis386 vex_w_table[][2] = { { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) }, }, { - /* VEX_W_0F50_M_0 */ - { "vmovmskpX", { Gdq, XS }, 0 }, + /* VEX_W_0F90_P_0_LEN_0 */ + { "kmovw", { MaskG, MaskE }, 0 }, + { "kmovq", { MaskG, MaskE }, 0 }, }, { - /* VEX_W_0F51_P_0 */ - { "vsqrtps", { XM, EXx }, 0 }, + /* VEX_W_0F90_P_2_LEN_0 */ + { "kmovb", { MaskG, MaskBDE }, 0 }, + { "kmovd", { MaskG, MaskBDE }, 0 }, }, { - /* VEX_W_0F51_P_1 */ - { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, + /* VEX_W_0F91_P_0_LEN_0 */ + { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) }, + { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) }, }, { - /* VEX_W_0F51_P_2 */ - { "vsqrtpd", { XM, EXx }, 0 }, + /* VEX_W_0F91_P_2_LEN_0 */ + { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) }, + { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) }, }, { - /* VEX_W_0F51_P_3 */ - { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 }, + /* VEX_W_0F92_P_0_LEN_0 */ + { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) }, }, { - /* VEX_W_0F52_P_0 */ - { "vrsqrtps", { XM, EXx }, 0 }, + /* VEX_W_0F92_P_2_LEN_0 */ + { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) }, }, { - /* VEX_W_0F52_P_1 */ - { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, + /* VEX_W_0F93_P_0_LEN_0 */ + { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) }, }, { - /* VEX_W_0F53_P_0 */ - { "vrcpps", { XM, EXx }, 0 }, + /* VEX_W_0F93_P_2_LEN_0 */ + { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) }, }, { - /* VEX_W_0F53_P_1 */ - { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 }, + /* VEX_W_0F98_P_0_LEN_0 */ + { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) }, + { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) }, }, { - /* VEX_W_0F58_P_0 */ - { "vaddps", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F58_P_1 */ - { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 }, - }, - { - /* VEX_W_0F58_P_2 */ - { "vaddpd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F58_P_3 */ - { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 }, - }, - { - /* VEX_W_0F59_P_0 */ - { "vmulps", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F59_P_1 */ - { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 }, - }, - { - /* VEX_W_0F59_P_2 */ - { "vmulpd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F59_P_3 */ - { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 }, - }, - { - /* VEX_W_0F5A_P_0 */ - { "vcvtps2pd", { XM, EXxmmq }, 0 }, - }, - { - /* VEX_W_0F5A_P_1 */ - { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 }, - }, - { - /* VEX_W_0F5A_P_3 */ - { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 }, - }, - { - /* VEX_W_0F5B_P_0 */ - { "vcvtdq2ps", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F5B_P_1 */ - { "vcvttps2dq", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F5B_P_2 */ - { "vcvtps2dq", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F5C_P_0 */ - { "vsubps", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F5C_P_1 */ - { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 }, - }, - { - /* VEX_W_0F5C_P_2 */ - { "vsubpd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F5C_P_3 */ - { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 }, - }, - { - /* VEX_W_0F5D_P_0 */ - { "vminps", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F5D_P_1 */ - { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 }, - }, - { - /* VEX_W_0F5D_P_2 */ - { "vminpd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F5D_P_3 */ - { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 }, - }, - { - /* VEX_W_0F5E_P_0 */ - { "vdivps", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F5E_P_1 */ - { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 }, - }, - { - /* VEX_W_0F5E_P_2 */ - { "vdivpd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F5E_P_3 */ - { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 }, - }, - { - /* VEX_W_0F5F_P_0 */ - { "vmaxps", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F5F_P_1 */ - { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 }, - }, - { - /* VEX_W_0F5F_P_2 */ - { "vmaxpd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F5F_P_3 */ - { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 }, - }, - { - /* VEX_W_0F60_P_2 */ - { "vpunpcklbw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F61_P_2 */ - { "vpunpcklwd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F62_P_2 */ - { "vpunpckldq", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F63_P_2 */ - { "vpacksswb", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F64_P_2 */ - { "vpcmpgtb", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F65_P_2 */ - { "vpcmpgtw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F66_P_2 */ - { "vpcmpgtd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F67_P_2 */ - { "vpackuswb", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F68_P_2 */ - { "vpunpckhbw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F69_P_2 */ - { "vpunpckhwd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F6A_P_2 */ - { "vpunpckhdq", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F6B_P_2 */ - { "vpackssdw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F6C_P_2 */ - { "vpunpcklqdq", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F6D_P_2 */ - { "vpunpckhqdq", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F6F_P_1 */ - { "vmovdqu", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F6F_P_2 */ - { "vmovdqa", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F70_P_1 */ - { "vpshufhw", { XM, EXx, Ib }, 0 }, - }, - { - /* VEX_W_0F70_P_2 */ - { "vpshufd", { XM, EXx, Ib }, 0 }, - }, - { - /* VEX_W_0F70_P_3 */ - { "vpshuflw", { XM, EXx, Ib }, 0 }, - }, - { - /* VEX_W_0F71_R_2_P_2 */ - { "vpsrlw", { Vex, XS, Ib }, 0 }, - }, - { - /* VEX_W_0F71_R_4_P_2 */ - { "vpsraw", { Vex, XS, Ib }, 0 }, - }, - { - /* VEX_W_0F71_R_6_P_2 */ - { "vpsllw", { Vex, XS, Ib }, 0 }, - }, - { - /* VEX_W_0F72_R_2_P_2 */ - { "vpsrld", { Vex, XS, Ib }, 0 }, - }, - { - /* VEX_W_0F72_R_4_P_2 */ - { "vpsrad", { Vex, XS, Ib }, 0 }, - }, - { - /* VEX_W_0F72_R_6_P_2 */ - { "vpslld", { Vex, XS, Ib }, 0 }, - }, - { - /* VEX_W_0F73_R_2_P_2 */ - { "vpsrlq", { Vex, XS, Ib }, 0 }, - }, - { - /* VEX_W_0F73_R_3_P_2 */ - { "vpsrldq", { Vex, XS, Ib }, 0 }, - }, - { - /* VEX_W_0F73_R_6_P_2 */ - { "vpsllq", { Vex, XS, Ib }, 0 }, - }, - { - /* VEX_W_0F73_R_7_P_2 */ - { "vpslldq", { Vex, XS, Ib }, 0 }, - }, - { - /* VEX_W_0F74_P_2 */ - { "vpcmpeqb", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F75_P_2 */ - { "vpcmpeqw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F76_P_2 */ - { "vpcmpeqd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F77_P_0 */ - { "", { VZERO }, 0 }, - }, - { - /* VEX_W_0F7C_P_2 */ - { "vhaddpd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F7C_P_3 */ - { "vhaddps", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F7D_P_2 */ - { "vhsubpd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F7D_P_3 */ - { "vhsubps", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F7E_P_1 */ - { "vmovq", { XMScalar, EXqScalar }, 0 }, - }, - { - /* VEX_W_0F7F_P_1 */ - { "vmovdqu", { EXxS, XM }, 0 }, - }, - { - /* VEX_W_0F7F_P_2 */ - { "vmovdqa", { EXxS, XM }, 0 }, - }, - { - /* VEX_W_0F90_P_0_LEN_0 */ - { "kmovw", { MaskG, MaskE }, 0 }, - { "kmovq", { MaskG, MaskE }, 0 }, - }, - { - /* VEX_W_0F90_P_2_LEN_0 */ - { "kmovb", { MaskG, MaskBDE }, 0 }, - { "kmovd", { MaskG, MaskBDE }, 0 }, - }, - { - /* VEX_W_0F91_P_0_LEN_0 */ - { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) }, - { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) }, - }, - { - /* VEX_W_0F91_P_2_LEN_0 */ - { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) }, - { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) }, - }, - { - /* VEX_W_0F92_P_0_LEN_0 */ - { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) }, - }, - { - /* VEX_W_0F92_P_2_LEN_0 */ - { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) }, - }, - { - /* VEX_W_0F92_P_3_LEN_0 */ - { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) }, - { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) }, - }, - { - /* VEX_W_0F93_P_0_LEN_0 */ - { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) }, - }, - { - /* VEX_W_0F93_P_2_LEN_0 */ - { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) }, - }, - { - /* VEX_W_0F93_P_3_LEN_0 */ - { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) }, - { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) }, - }, - { - /* VEX_W_0F98_P_0_LEN_0 */ - { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) }, - { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) }, - }, - { - /* VEX_W_0F98_P_2_LEN_0 */ - { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) }, - { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) }, - }, - { - /* VEX_W_0F99_P_0_LEN_0 */ - { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) }, - { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) }, - }, - { - /* VEX_W_0F99_P_2_LEN_0 */ - { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) }, - { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) }, - }, - { - /* VEX_W_0FAE_R_2_M_0 */ - { "vldmxcsr", { Md }, 0 }, - }, - { - /* VEX_W_0FAE_R_3_M_0 */ - { "vstmxcsr", { Md }, 0 }, - }, - { - /* VEX_W_0FC2_P_0 */ - { "vcmpps", { XM, Vex, EXx, VCMP }, 0 }, - }, - { - /* VEX_W_0FC2_P_1 */ - { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 }, - }, - { - /* VEX_W_0FC2_P_2 */ - { "vcmppd", { XM, Vex, EXx, VCMP }, 0 }, - }, - { - /* VEX_W_0FC2_P_3 */ - { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 }, - }, - { - /* VEX_W_0FC4_P_2 */ - { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 }, - }, - { - /* VEX_W_0FC5_P_2 */ - { "vpextrw", { Gdq, XS, Ib }, 0 }, - }, - { - /* VEX_W_0FD0_P_2 */ - { "vaddsubpd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FD0_P_3 */ - { "vaddsubps", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FD1_P_2 */ - { "vpsrlw", { XM, Vex, EXxmm }, 0 }, - }, - { - /* VEX_W_0FD2_P_2 */ - { "vpsrld", { XM, Vex, EXxmm }, 0 }, - }, - { - /* VEX_W_0FD3_P_2 */ - { "vpsrlq", { XM, Vex, EXxmm }, 0 }, - }, - { - /* VEX_W_0FD4_P_2 */ - { "vpaddq", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FD5_P_2 */ - { "vpmullw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FD6_P_2 */ - { "vmovq", { EXqScalarS, XMScalar }, 0 }, - }, - { - /* VEX_W_0FD7_P_2_M_1 */ - { "vpmovmskb", { Gdq, XS }, 0 }, - }, - { - /* VEX_W_0FD8_P_2 */ - { "vpsubusb", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FD9_P_2 */ - { "vpsubusw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FDA_P_2 */ - { "vpminub", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FDB_P_2 */ - { "vpand", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FDC_P_2 */ - { "vpaddusb", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FDD_P_2 */ - { "vpaddusw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FDE_P_2 */ - { "vpmaxub", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FDF_P_2 */ - { "vpandn", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FE0_P_2 */ - { "vpavgb", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FE1_P_2 */ - { "vpsraw", { XM, Vex, EXxmm }, 0 }, - }, - { - /* VEX_W_0FE2_P_2 */ - { "vpsrad", { XM, Vex, EXxmm }, 0 }, - }, - { - /* VEX_W_0FE3_P_2 */ - { "vpavgw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FE4_P_2 */ - { "vpmulhuw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FE5_P_2 */ - { "vpmulhw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FE6_P_1 */ - { "vcvtdq2pd", { XM, EXxmmq }, 0 }, - }, - { - /* VEX_W_0FE6_P_2 */ - { "vcvttpd2dq%XY", { XMM, EXx }, 0 }, - }, - { - /* VEX_W_0FE6_P_3 */ - { "vcvtpd2dq%XY", { XMM, EXx }, 0 }, - }, - { - /* VEX_W_0FE7_P_2_M_0 */ - { "vmovntdq", { Mx, XM }, 0 }, - }, - { - /* VEX_W_0FE8_P_2 */ - { "vpsubsb", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FE9_P_2 */ - { "vpsubsw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FEA_P_2 */ - { "vpminsw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FEB_P_2 */ - { "vpor", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FEC_P_2 */ - { "vpaddsb", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FED_P_2 */ - { "vpaddsw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FEE_P_2 */ - { "vpmaxsw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FEF_P_2 */ - { "vpxor", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FF0_P_3_M_0 */ - { "vlddqu", { XM, M }, 0 }, - }, - { - /* VEX_W_0FF1_P_2 */ - { "vpsllw", { XM, Vex, EXxmm }, 0 }, - }, - { - /* VEX_W_0FF2_P_2 */ - { "vpslld", { XM, Vex, EXxmm }, 0 }, - }, - { - /* VEX_W_0FF3_P_2 */ - { "vpsllq", { XM, Vex, EXxmm }, 0 }, - }, - { - /* VEX_W_0FF4_P_2 */ - { "vpmuludq", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FF5_P_2 */ - { "vpmaddwd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FF6_P_2 */ - { "vpsadbw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FF7_P_2 */ - { "vmaskmovdqu", { XM, XS }, 0 }, - }, - { - /* VEX_W_0FF8_P_2 */ - { "vpsubb", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FF9_P_2 */ - { "vpsubw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FFA_P_2 */ - { "vpsubd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FFB_P_2 */ - { "vpsubq", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FFC_P_2 */ - { "vpaddb", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FFD_P_2 */ - { "vpaddw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0FFE_P_2 */ - { "vpaddd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F3800_P_2 */ - { "vpshufb", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F3801_P_2 */ - { "vphaddw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F3802_P_2 */ - { "vphaddd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F3803_P_2 */ - { "vphaddsw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F3804_P_2 */ - { "vpmaddubsw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F3805_P_2 */ - { "vphsubw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F3806_P_2 */ - { "vphsubd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F3807_P_2 */ - { "vphsubsw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F3808_P_2 */ - { "vpsignb", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F3809_P_2 */ - { "vpsignw", { XM, Vex, EXx }, 0 }, + /* VEX_W_0F98_P_2_LEN_0 */ + { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) }, + { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) }, }, { - /* VEX_W_0F380A_P_2 */ - { "vpsignd", { XM, Vex, EXx }, 0 }, + /* VEX_W_0F99_P_0_LEN_0 */ + { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) }, + { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) }, }, { - /* VEX_W_0F380B_P_2 */ - { "vpmulhrsw", { XM, Vex, EXx }, 0 }, + /* VEX_W_0F99_P_2_LEN_0 */ + { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) }, + { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) }, }, { /* VEX_W_0F380C_P_2 */ @@ -11127,10 +10067,6 @@ static const struct dis386 vex_w_table[][2] = { /* VEX_W_0F3816_P_2 */ { "vpermps", { XM, Vex, EXx }, 0 }, }, - { - /* VEX_W_0F3817_P_2 */ - { "vptest", { XM, EXx }, 0 }, - }, { /* VEX_W_0F3818_P_2 */ { "vbroadcastss", { XM, EXxmm_md }, 0 }, @@ -11143,58 +10079,6 @@ static const struct dis386 vex_w_table[][2] = { /* VEX_W_0F381A_P_2_M_0 */ { "vbroadcastf128", { XM, Mxmm }, 0 }, }, - { - /* VEX_W_0F381C_P_2 */ - { "vpabsb", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F381D_P_2 */ - { "vpabsw", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F381E_P_2 */ - { "vpabsd", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F3820_P_2 */ - { "vpmovsxbw", { XM, EXxmmq }, 0 }, - }, - { - /* VEX_W_0F3821_P_2 */ - { "vpmovsxbd", { XM, EXxmmqd }, 0 }, - }, - { - /* VEX_W_0F3822_P_2 */ - { "vpmovsxbq", { XM, EXxmmdw }, 0 }, - }, - { - /* VEX_W_0F3823_P_2 */ - { "vpmovsxwd", { XM, EXxmmq }, 0 }, - }, - { - /* VEX_W_0F3824_P_2 */ - { "vpmovsxwq", { XM, EXxmmqd }, 0 }, - }, - { - /* VEX_W_0F3825_P_2 */ - { "vpmovsxdq", { XM, EXxmmq }, 0 }, - }, - { - /* VEX_W_0F3828_P_2 */ - { "vpmuldq", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F3829_P_2 */ - { "vpcmpeqq", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F382A_P_2_M_0 */ - { "vmovntdqa", { XM, Mx }, 0 }, - }, - { - /* VEX_W_0F382B_P_2 */ - { "vpackusdw", { XM, Vex, EXx }, 0 }, - }, { /* VEX_W_0F382C_P_2_M_0 */ { "vmaskmovps", { XM, Vex, Mx }, 0 }, @@ -11211,78 +10095,10 @@ static const struct dis386 vex_w_table[][2] = { /* VEX_W_0F382F_P_2_M_0 */ { "vmaskmovpd", { Mx, Vex, XM }, 0 }, }, - { - /* VEX_W_0F3830_P_2 */ - { "vpmovzxbw", { XM, EXxmmq }, 0 }, - }, - { - /* VEX_W_0F3831_P_2 */ - { "vpmovzxbd", { XM, EXxmmqd }, 0 }, - }, - { - /* VEX_W_0F3832_P_2 */ - { "vpmovzxbq", { XM, EXxmmdw }, 0 }, - }, - { - /* VEX_W_0F3833_P_2 */ - { "vpmovzxwd", { XM, EXxmmq }, 0 }, - }, - { - /* VEX_W_0F3834_P_2 */ - { "vpmovzxwq", { XM, EXxmmqd }, 0 }, - }, - { - /* VEX_W_0F3835_P_2 */ - { "vpmovzxdq", { XM, EXxmmq }, 0 }, - }, { /* VEX_W_0F3836_P_2 */ { "vpermd", { XM, Vex, EXx }, 0 }, }, - { - /* VEX_W_0F3837_P_2 */ - { "vpcmpgtq", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F3838_P_2 */ - { "vpminsb", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F3839_P_2 */ - { "vpminsd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F383A_P_2 */ - { "vpminuw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F383B_P_2 */ - { "vpminud", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F383C_P_2 */ - { "vpmaxsb", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F383D_P_2 */ - { "vpmaxsd", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F383E_P_2 */ - { "vpmaxuw", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F383F_P_2 */ - { "vpmaxud", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F3840_P_2 */ - { "vpmulld", { XM, Vex, EXx }, 0 }, - }, - { - /* VEX_W_0F3841_P_2 */ - { "vphminposuw", { XM, EXx }, 0 }, - }, { /* VEX_W_0F3846_P_2 */ { "vpsravd", { XM, Vex, EXx }, 0 }, @@ -11311,10 +10127,6 @@ static const struct dis386 vex_w_table[][2] = { /* VEX_W_0F38CF_P_2 */ { "vgf2p8mulb", { XM, Vex, EXx }, 0 }, }, - { - /* VEX_W_0F38DB_P_2 */ - { "vaesimc", { XM, EXx }, 0 }, - }, { /* VEX_W_0F3A00_P_2 */ { Bad_Opcode }, @@ -11341,46 +10153,6 @@ static const struct dis386 vex_w_table[][2] = { /* VEX_W_0F3A06_P_2 */ { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 }, }, - { - /* VEX_W_0F3A08_P_2 */ - { "vroundps", { XM, EXx, Ib }, 0 }, - }, - { - /* VEX_W_0F3A09_P_2 */ - { "vroundpd", { XM, EXx, Ib }, 0 }, - }, - { - /* VEX_W_0F3A0A_P_2 */ - { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 }, - }, - { - /* VEX_W_0F3A0B_P_2 */ - { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 }, - }, - { - /* VEX_W_0F3A0C_P_2 */ - { "vblendps", { XM, Vex, EXx, Ib }, 0 }, - }, - { - /* VEX_W_0F3A0D_P_2 */ - { "vblendpd", { XM, Vex, EXx, Ib }, 0 }, - }, - { - /* VEX_W_0F3A0E_P_2 */ - { "vpblendw", { XM, Vex, EXx, Ib }, 0 }, - }, - { - /* VEX_W_0F3A0F_P_2 */ - { "vpalignr", { XM, Vex, EXx, Ib }, 0 }, - }, - { - /* VEX_W_0F3A14_P_2 */ - { "vpextrb", { Edqb, XM, Ib }, 0 }, - }, - { - /* VEX_W_0F3A15_P_2 */ - { "vpextrw", { Edqw, XM, Ib }, 0 }, - }, { /* VEX_W_0F3A18_P_2 */ { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 }, @@ -11389,14 +10161,6 @@ static const struct dis386 vex_w_table[][2] = { /* VEX_W_0F3A19_P_2 */ { "vextractf128", { EXxmm, XM, Ib }, 0 }, }, - { - /* VEX_W_0F3A20_P_2 */ - { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 }, - }, - { - /* VEX_W_0F3A21_P_2 */ - { "vinsertps", { XM, Vex128, EXd, Ib }, 0 }, - }, { /* VEX_W_0F3A30_P_2_LEN_0 */ { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) }, @@ -11425,18 +10189,6 @@ static const struct dis386 vex_w_table[][2] = { /* VEX_W_0F3A39_P_2 */ { "vextracti128", { EXxmm, XM, Ib }, 0 }, }, - { - /* VEX_W_0F3A40_P_2 */ - { "vdpps", { XM, Vex, EXx, Ib }, 0 }, - }, - { - /* VEX_W_0F3A41_P_2 */ - { "vdppd", { XM, Vex128, EXx, Ib }, 0 }, - }, - { - /* VEX_W_0F3A42_P_2 */ - { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 }, - }, { /* VEX_W_0F3A46_P_2 */ { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 }, @@ -11463,14 +10215,6 @@ static const struct dis386 vex_w_table[][2] = { /* VEX_W_0F3A4C_P_2 */ { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 }, }, - { - /* VEX_W_0F3A62_P_2 */ - { "vpcmpistrm", { XM, EXx, Ib }, 0 }, - }, - { - /* VEX_W_0F3A63_P_2 */ - { "vpcmpistri", { XM, EXx, Ib }, 0 }, - }, { /* VEX_W_0F3ACE_P_2 */ { Bad_Opcode }, @@ -11481,13 +10225,8 @@ static const struct dis386 vex_w_table[][2] = { { Bad_Opcode }, { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, 0 }, }, - { - /* VEX_W_0F3ADF_P_2 */ - { "vaeskeygenassist", { XM, EXx, Ib }, 0 }, - }, -#define NEED_VEX_W_TABLE -#include "i386-dis-evex.h" -#undef NEED_VEX_W_TABLE + +#include "i386-dis-evex-w.h" }; static const struct dis386 mod_table[][2] = { @@ -11535,13 +10274,13 @@ static const struct dis386 mod_table[][2] = { }, { /* MOD_0F01_REG_5 */ - { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) }, - { RM_TABLE (RM_0F01_REG_5) }, + { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) }, + { RM_TABLE (RM_0F01_REG_5_MOD_3) }, }, { /* MOD_0F01_REG_7 */ { "invlpg", { Mb }, 0 }, - { RM_TABLE (RM_0F01_REG_7) }, + { RM_TABLE (RM_0F01_REG_7_MOD_3) }, }, { /* MOD_0F12_PREFIX_0 */ @@ -11595,23 +10334,28 @@ static const struct dis386 mod_table[][2] = { }, { /* MOD_0F1A_PREFIX_0 */ - { "bndldx", { Gbnd, Ev_bnd }, 0 }, + { "bndldx", { Gbnd, Mv_bnd }, 0 }, { "nopQ", { Ev }, 0 }, }, { /* MOD_0F1B_PREFIX_0 */ - { "bndstx", { Ev_bnd, Gbnd }, 0 }, + { "bndstx", { Mv_bnd, Gbnd }, 0 }, { "nopQ", { Ev }, 0 }, }, { /* MOD_0F1B_PREFIX_1 */ - { "bndmk", { Gbnd, Ev_bnd }, 0 }, + { "bndmk", { Gbnd, Mv_bnd }, 0 }, + { "nopQ", { Ev }, 0 }, + }, + { + /* MOD_0F1C_PREFIX_0 */ + { REG_TABLE (REG_0F1C_P_0_MOD_0) }, { "nopQ", { Ev }, 0 }, }, { /* MOD_0F1E_PREFIX_1 */ { "nopQ", { Ev }, 0 }, - { REG_TABLE (REG_0F1E_MOD_3) }, + { REG_TABLE (REG_0F1E_P_1_MOD_3) }, }, { /* MOD_0F24 */ @@ -11697,42 +10441,42 @@ static const struct dis386 mod_table[][2] = { { /* MOD_0FAE_REG_0 */ { "fxsave", { FXSAVE }, 0 }, - { PREFIX_TABLE (PREFIX_0FAE_REG_0) }, + { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) }, }, { /* MOD_0FAE_REG_1 */ { "fxrstor", { FXSAVE }, 0 }, - { PREFIX_TABLE (PREFIX_0FAE_REG_1) }, + { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) }, }, { /* MOD_0FAE_REG_2 */ { "ldmxcsr", { Md }, 0 }, - { PREFIX_TABLE (PREFIX_0FAE_REG_2) }, + { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) }, }, { /* MOD_0FAE_REG_3 */ { "stmxcsr", { Md }, 0 }, - { PREFIX_TABLE (PREFIX_0FAE_REG_3) }, + { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) }, }, { /* MOD_0FAE_REG_4 */ - { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) }, - { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) }, + { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) }, + { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) }, }, { /* MOD_0FAE_REG_5 */ - { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) }, - { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) }, + { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) }, + { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) }, }, { /* MOD_0FAE_REG_6 */ - { PREFIX_TABLE (PREFIX_0FAE_REG_6) }, - { RM_TABLE (RM_0FAE_REG_6) }, + { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) }, + { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) }, }, { /* MOD_0FAE_REG_7 */ - { PREFIX_TABLE (PREFIX_0FAE_REG_7) }, - { RM_TABLE (RM_0FAE_REG_7) }, + { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) }, + { RM_TABLE (RM_0FAE_REG_7_MOD_3) }, }, { /* MOD_0FB2 */ @@ -11748,7 +10492,7 @@ static const struct dis386 mod_table[][2] = { }, { /* MOD_0FC3 */ - { PREFIX_TABLE (PREFIX_MOD_0_0FC3) }, + { PREFIX_TABLE (PREFIX_0FC3_MOD_0) }, }, { /* MOD_0FC7_REG_3 */ @@ -11764,13 +10508,13 @@ static const struct dis386 mod_table[][2] = { }, { /* MOD_0FC7_REG_6 */ - { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) }, - { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) } + { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) }, + { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) } }, { /* MOD_0FC7_REG_7 */ { "vmptrst", { Mq }, 0 }, - { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) } + { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) } }, { /* MOD_0FD7 */ @@ -11797,6 +10541,22 @@ static const struct dis386 mod_table[][2] = { /* MOD_0F38F6_PREFIX_0 */ { "wrssK", { M, Gdq }, PREFIX_OPCODE }, }, + { + /* MOD_0F38F8_PREFIX_1 */ + { "enqcmds", { Gva, M }, PREFIX_OPCODE }, + }, + { + /* MOD_0F38F8_PREFIX_2 */ + { "movdir64b", { Gva, M }, PREFIX_OPCODE }, + }, + { + /* MOD_0F38F8_PREFIX_3 */ + { "enqcmd", { Gva, M }, PREFIX_OPCODE }, + }, + { + /* MOD_0F38F9_PREFIX_0 */ + { "movdiri", { Ev, Gv }, PREFIX_OPCODE }, + }, { /* MOD_62_32BIT */ { "bound{S|}", { Gv, Ma }, 0 }, @@ -11832,7 +10592,7 @@ static const struct dis386 mod_table[][2] = { }, { /* MOD_VEX_0F2B */ - { VEX_W_TABLE (VEX_W_0F2B_M_0) }, + { "vmovntpX", { Mx, XM }, 0 }, }, { /* MOD_VEX_W_0_0F41_P_0_LEN_1 */ @@ -11992,7 +10752,7 @@ static const struct dis386 mod_table[][2] = { { /* MOD_VEX_0F50 */ { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0F50_M_0) }, + { "vmovmskpX", { Gdq, XS }, 0 }, }, { /* MOD_VEX_0F71_REG_2 */ @@ -12075,14 +10835,9 @@ static const struct dis386 mod_table[][2] = { { "kmovb", { MaskG, Rdq }, 0 }, }, { - /* MOD_VEX_W_0_0F92_P_3_LEN_0 */ - { Bad_Opcode }, - { "kmovd", { MaskG, Rdq }, 0 }, - }, - { - /* MOD_VEX_W_1_0F92_P_3_LEN_0 */ + /* MOD_VEX_0F92_P_3_LEN_0 */ { Bad_Opcode }, - { "kmovq", { MaskG, Rdq }, 0 }, + { "kmovK", { MaskG, Rdq }, 0 }, }, { /* MOD_VEX_W_0_0F93_P_0_LEN_0 */ @@ -12095,14 +10850,9 @@ static const struct dis386 mod_table[][2] = { { "kmovb", { Gdq, MaskR }, 0 }, }, { - /* MOD_VEX_W_0_0F93_P_3_LEN_0 */ - { Bad_Opcode }, - { "kmovd", { Gdq, MaskR }, 0 }, - }, - { - /* MOD_VEX_W_1_0F93_P_3_LEN_0 */ + /* MOD_VEX_0F93_P_3_LEN_0 */ { Bad_Opcode }, - { "kmovq", { Gdq, MaskR }, 0 }, + { "kmovK", { Gdq, MaskR }, 0 }, }, { /* MOD_VEX_W_0_0F98_P_0_LEN_0 */ @@ -12155,15 +10905,15 @@ static const struct dis386 mod_table[][2] = { { /* MOD_VEX_0FD7_PREFIX_2 */ { Bad_Opcode }, - { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) }, + { "vpmovmskb", { Gdq, XS }, 0 }, }, { /* MOD_VEX_0FE7_PREFIX_2 */ - { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) }, + { "vmovntdq", { Mx, XM }, 0 }, }, { /* MOD_VEX_0FF0_PREFIX_3 */ - { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) }, + { "vlddqu", { XM, M }, 0 }, }, { /* MOD_VEX_0F381A_PREFIX_2 */ @@ -12171,7 +10921,7 @@ static const struct dis386 mod_table[][2] = { }, { /* MOD_VEX_0F382A_PREFIX_2 */ - { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) }, + { "vmovntdqa", { XM, Mx }, 0 }, }, { /* MOD_VEX_0F382C_PREFIX_2 */ @@ -12241,9 +10991,8 @@ static const struct dis386 mod_table[][2] = { { Bad_Opcode }, { "kshiftlq", { MaskG, MaskR, Ib }, 0 }, }, -#define NEED_MOD_TABLE -#include "i386-dis-evex.h" -#undef NEED_MOD_TABLE + +#include "i386-dis-evex-mod.h" }; static const struct dis386 rm_table[][8] = { @@ -12253,11 +11002,11 @@ static const struct dis386 rm_table[][8] = { }, { /* RM_C7_REG_7 */ - { "xbeginT", { Skip_MODRM, Jv }, 0 }, + { "xbeginT", { Skip_MODRM, Jdqw }, 0 }, }, { /* RM_0F01_REG_0 */ - { Bad_Opcode }, + { "enclv", { Skip_MODRM }, 0 }, { "vmcall", { Skip_MODRM }, 0 }, { "vmlaunch", { Skip_MODRM }, 0 }, { "vmresume", { Skip_MODRM }, 0 }, @@ -12289,7 +11038,7 @@ static const struct dis386 rm_table[][8] = { { /* RM_0F01_REG_3 */ { "vmrun", { Skip_MODRM }, 0 }, - { "vmmcall", { Skip_MODRM }, 0 }, + { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) }, { "vmload", { Skip_MODRM }, 0 }, { "vmsave", { Skip_MODRM }, 0 }, { "stgi", { Skip_MODRM }, 0 }, @@ -12298,10 +11047,10 @@ static const struct dis386 rm_table[][8] = { { "invlpga", { Skip_MODRM }, 0 }, }, { - /* RM_0F01_REG_5 */ - { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) }, - { Bad_Opcode }, - { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) }, + /* RM_0F01_REG_5_MOD_3 */ + { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) }, + { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) }, + { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -12309,15 +11058,16 @@ static const struct dis386 rm_table[][8] = { { "wrpkru", { Skip_MODRM }, 0 }, }, { - /* RM_0F01_REG_7 */ + /* RM_0F01_REG_7_MOD_3 */ { "swapgs", { Skip_MODRM }, 0 }, { "rdtscp", { Skip_MODRM }, 0 }, - { "monitorx", { { OP_Monitor, 0 } }, 0 }, - { "mwaitx", { { OP_Mwaitx, 0 } }, 0 }, + { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) }, + { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) }, { "clzero", { Skip_MODRM }, 0 }, + { "rdpru", { Skip_MODRM }, 0 }, }, { - /* RM_0F1E_MOD_3_REG_7 */ + /* RM_0F1E_P_1_MOD_3_REG_7 */ { "nopQ", { Ev }, 0 }, { "nopQ", { Ev }, 0 }, { "endbr64", { Skip_MODRM }, PREFIX_OPCODE }, @@ -12328,11 +11078,11 @@ static const struct dis386 rm_table[][8] = { { "nopQ", { Ev }, 0 }, }, { - /* RM_0FAE_REG_6 */ + /* RM_0FAE_REG_6_MOD_3 */ { "mfence", { Skip_MODRM }, 0 }, }, { - /* RM_0FAE_REG_7 */ + /* RM_0FAE_REG_7_MOD_3 */ { "sfence", { Skip_MODRM }, 0 }, }, @@ -12348,6 +11098,9 @@ static const struct dis386 rm_table[][8] = { #define BND_PREFIX (0xf2 | 0x400) #define NOTRACK_PREFIX (0x3e | 0x100) +/* Remember if the current op is a jump instruction. */ +static bfd_boolean op_is_jump = FALSE; + static int ckprefix (void) { @@ -12597,7 +11350,7 @@ static char scale_char; enum x86_64_isa { - amd64 = 0, + amd64 = 1, intel64 }; @@ -12788,6 +11541,29 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) dp = &vex_len_table[dp->op[1].bytemode][vindex]; break; + case USE_EVEX_LEN_TABLE: + if (!vex.evex) + abort (); + + switch (vex.length) + { + case 128: + vindex = 0; + break; + case 256: + vindex = 1; + break; + case 512: + vindex = 2; + break; + default: + abort (); + break; + } + + dp = &evex_len_table[dp->op[1].bytemode][vindex]; + break; + case USE_XOP_8F_TABLE: FETCH_DATA (info, codep + 3); /* All bits in the REX prefix are ignored. */ @@ -13399,6 +12175,58 @@ print_insn (bfd_vma pc, disassemble_info *info) } } + /* Clear instruction information. */ + if (the_info) + { + the_info->insn_info_valid = 0; + the_info->branch_delay_insns = 0; + the_info->data_size = 0; + the_info->insn_type = dis_noninsn; + the_info->target = 0; + the_info->target2 = 0; + } + + /* Reset jump operation indicator. */ + op_is_jump = FALSE; + + { + int jump_detection = 0; + + /* Extract flags. */ + for (i = 0; i < MAX_OPERANDS; ++i) + { + if ((dp->op[i].rtn == OP_J) + || (dp->op[i].rtn == OP_indirE)) + jump_detection |= 1; + else if ((dp->op[i].rtn == BND_Fixup) + || (!dp->op[i].rtn && !dp->op[i].bytemode)) + jump_detection |= 2; + else if ((dp->op[i].bytemode == cond_jump_mode) + || (dp->op[i].bytemode == loop_jcxz_mode)) + jump_detection |= 4; + } + + /* Determine if this is a jump or branch. */ + if ((jump_detection & 0x3) == 0x3) + { + op_is_jump = TRUE; + if (jump_detection & 0x4) + the_info->insn_type = dis_condbranch; + else + the_info->insn_type = + (dp->name && !strncmp(dp->name, "call", 4)) + ? dis_jsr : dis_branch; + } + } + + /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which + are all 0s in inverted form. */ + if (need_vex && vex.register_specifier != 0) + { + (*info->fprintf_func) (info->stream, "(bad)"); + return end_codep - priv.the_buffer; + } + /* Check if the REX prefix is used. */ if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0) all_prefixes[last_rex_prefix] = 0; @@ -13504,7 +12332,19 @@ print_insn (bfd_vma pc, disassemble_info *info) if (needcomma) (*info->fprintf_func) (info->stream, ","); if (op_index[i] != -1 && !op_riprel[i]) - (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info); + { + bfd_vma target = (bfd_vma) op_address[op_index[i]]; + + if (the_info && op_is_jump) + { + the_info->insn_info_valid = 1; + the_info->branch_delay_insns = 0; + the_info->data_size = 0; + the_info->target = target; + the_info->target2 = 0; + } + (*info->print_address_func) (target, info); + } else (*info->fprintf_func) (info->stream, "%s", op_txt[i]); needcomma = 1; @@ -13971,7 +12811,7 @@ putop (const char *in_template, int sizeflag) case 'B': if (l == 0 && len == 1) { -case_B: + case_B: if (intel_syntax) break; if (sizeflag & SUFFIX_ALWAYS) @@ -14136,7 +12976,7 @@ case_B: SAVE_LAST (*p); break; } -case_L: + case_L: if (intel_syntax) break; if (sizeflag & SUFFIX_ALWAYS) @@ -14185,7 +13025,7 @@ case_L: case 'P': if (l == 0 && len == 1) { -case_P: + case_P: if (intel_syntax) { if ((rex & REX_W) == 0 @@ -14255,7 +13095,7 @@ case_P: case 'Q': if (l == 0 && len == 1) { -case_Q: + case_Q: if (intel_syntax && !alt) break; USED_REX (REX_W); @@ -14346,7 +13186,7 @@ case_Q: case 'S': if (l == 0 && len == 1) { -case_S: + case_S: if (intel_syntax) break; if (sizeflag & SUFFIX_ALWAYS) @@ -14476,6 +13316,12 @@ case_S: case '^': if (intel_syntax) break; + if (isa64 == intel64 && (rex & REX_W)) + { + USED_REX (REX_W); + *obufp++ = 'q'; + break; + } if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) { if (sizeflag & DFLAG) @@ -14725,6 +13571,13 @@ intel_operand_size (int bytemode, int sizeflag) oappend ("DWORD PTR "); used_prefixes |= (prefixes & PREFIX_DATA); break; + case movsxd_mode: + if (!(sizeflag & DFLAG) && isa64 == intel64) + oappend ("WORD PTR "); + else + oappend ("DWORD PTR "); + used_prefixes |= (prefixes & PREFIX_DATA); + break; case d_mode: case d_scalar_mode: case d_scalar_swap_mode: @@ -14940,8 +13793,6 @@ intel_operand_size (int bytemode, int sizeflag) case o_mode: oappend ("OWORD PTR "); break; - case xmm_mdq_mode: - case vex_w_dq_mode: case vex_scalar_w_dq_mode: if (!need_vex) abort (); @@ -15019,6 +13870,7 @@ intel_operand_size (int bytemode, int sizeflag) oappend ("WORD PTR "); break; case v_bnd_mode: + case v_bndmk_mode: default: break; } @@ -15109,6 +13961,28 @@ OP_E_register (int bytemode, int sizeflag) used_prefixes |= (prefixes & PREFIX_DATA); } break; + case movsxd_mode: + if (!(sizeflag & DFLAG) && isa64 == intel64) + names = names16; + else + names = names32; + used_prefixes |= (prefixes & PREFIX_DATA); + break; + case va_mode: + names = (address_mode == mode_64bit + ? names64 : names32); + if (!(prefixes & PREFIX_ADDR)) + names = (address_mode == mode_16bit + ? names16 : names); + else + { + /* Remove "addr16/addr32". */ + all_prefixes[last_addr_prefix] = 0; + names = (address_mode != mode_32bit + ? names32 : names16); + used_prefixes |= PREFIX_ADDR; + } + break; case mask_bd_mode: case mask_mode: if (reg > 0x7) @@ -15156,12 +14030,19 @@ OP_E_memory (int bytemode, int sizeflag) case db_mode: shift = 0; break; + case dq_mode: + if (address_mode != mode_64bit) + { + shift = 2; + break; + } + /* fall through */ + case vex_scalar_w_dq_mode: case vex_vsib_d_w_dq_mode: case vex_vsib_d_w_d_mode: case vex_vsib_q_w_dq_mode: case vex_vsib_q_w_d_mode: case evex_x_gscat_mode: - case xmm_mdq_mode: shift = vex.w ? 3 : 2; break; case x_mode: @@ -15214,11 +14095,11 @@ OP_E_memory (int bytemode, int sizeflag) case d_scalar_swap_mode: shift = 2; break; - case w_scalar_mode: + case w_scalar_mode: case xmm_mw_mode: shift = 1; break; - case b_scalar_mode: + case b_scalar_mode: case xmm_mb_mode: shift = 0; break; @@ -15258,11 +14139,13 @@ OP_E_memory (int bytemode, int sizeflag) int havebase; int haveindex; int needindex; + int needaddr32; int base, rbase; int vindex = 0; int scale = 0; int addr32flag = !((sizeflag & AFLAG) || bytemode == v_bnd_mode + || bytemode == v_bndmk_mode || bytemode == bnd_mode || bytemode == bnd_swap_mode); const char **indexes64 = names64; @@ -15339,6 +14222,11 @@ OP_E_memory (int bytemode, int sizeflag) if (address_mode == mode_64bit && !havesib) riprel = 1; disp = get32s (); + if (riprel && bytemode == v_bndmk_mode) + { + oappend ("(bad)"); + return; + } } break; case 1: @@ -15354,12 +14242,27 @@ OP_E_memory (int bytemode, int sizeflag) break; } - /* In 32bit mode, we need index register to tell [offset] from - [eiz*1 + offset]. */ - needindex = (havesib - && !havebase - && !haveindex - && address_mode == mode_32bit); + needindex = 0; + needaddr32 = 0; + if (havesib + && !havebase + && !haveindex + && address_mode != mode_16bit) + { + if (address_mode == mode_64bit) + { + /* Display eiz instead of addr32. */ + needindex = addr32flag; + needaddr32 = 1; + } + else + { + /* In 32-bit mode, we need index register to tell [offset] + from [eiz*1 + offset]. */ + needindex = 1; + } + } + havedisp = (havebase || needindex || (havesib && (haveindex || scale != 0))); @@ -15379,10 +14282,12 @@ OP_E_memory (int bytemode, int sizeflag) } } - if ((havebase || haveindex || riprel) - && (bytemode != v_bnd_mode) - && (bytemode != bnd_mode) - && (bytemode != bnd_swap_mode)) + if ((havebase || haveindex || needindex || needaddr32 || riprel) + && (address_mode != mode_64bit + || ((bytemode != v_bnd_mode) + && (bytemode != v_bndmk_mode) + && (bytemode != bnd_mode) + && (bytemode != bnd_swap_mode)))) used_prefixes |= PREFIX_ADDR; if (havedisp || (intel_syntax && riprel)) @@ -15463,6 +14368,14 @@ OP_E_memory (int bytemode, int sizeflag) } } } + else if (bytemode == v_bnd_mode + || bytemode == v_bndmk_mode + || bytemode == bnd_mode + || bytemode == bnd_swap_mode) + { + oappend ("(bad)"); + return; + } else { /* 16 bit address mode */ @@ -15598,6 +14511,7 @@ static void OP_G (int bytemode, int sizeflag) { int add = 0; + const char **names; USED_REX (REX_R); if (rex & REX_R) add += 8; @@ -15634,18 +14548,38 @@ OP_G (int bytemode, int sizeflag) case dqb_mode: case dqd_mode: case dqw_mode: + case movsxd_mode: USED_REX (REX_W); if (rex & REX_W) oappend (names64[modrm.reg + add]); else { - if ((sizeflag & DFLAG) || bytemode != v_mode) + if ((sizeflag & DFLAG) + || (bytemode != v_mode && bytemode != movsxd_mode)) oappend (names32[modrm.reg + add]); else oappend (names16[modrm.reg + add]); used_prefixes |= (prefixes & PREFIX_DATA); } break; + case va_mode: + names = (address_mode == mode_64bit + ? names64 : names32); + if (!(prefixes & PREFIX_ADDR)) + { + if (address_mode == mode_16bit) + names = names16; + } + else + { + /* Remove "addr16/addr32". */ + all_prefixes[last_addr_prefix] = 0; + names = (address_mode != mode_32bit + ? names32 : names16); + used_prefixes |= PREFIX_ADDR; + } + oappend (names[modrm.reg + add]); + break; case m_mode: if (address_mode == mode_64bit) oappend (names64[modrm.reg + add]); @@ -15885,13 +14819,6 @@ OP_I (int bytemode, int sizeflag) op = *codep++; mask = 0xff; break; - case q_mode: - if (address_mode == mode_64bit) - { - op = get32s (); - break; - } - /* Fall through. */ case v_mode: USED_REX (REX_W); if (rex & REX_W) @@ -15911,6 +14838,10 @@ OP_I (int bytemode, int sizeflag) used_prefixes |= (prefixes & PREFIX_DATA); } break; + case d_mode: + mask = 0xffffffff; + op = get32 (); + break; case w_mode: mask = 0xfffff; op = get16 (); @@ -15934,53 +14865,16 @@ OP_I (int bytemode, int sizeflag) static void OP_I64 (int bytemode, int sizeflag) { - bfd_signed_vma op; - bfd_signed_vma mask = -1; - - if (address_mode != mode_64bit) + if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W)) { OP_I (bytemode, sizeflag); return; } - switch (bytemode) - { - case b_mode: - FETCH_DATA (the_info, codep + 1); - op = *codep++; - mask = 0xff; - break; - case v_mode: - USED_REX (REX_W); - if (rex & REX_W) - op = get64 (); - else - { - if (sizeflag & DFLAG) - { - op = get32 (); - mask = 0xffffffff; - } - else - { - op = get16 (); - mask = 0xfffff; - } - used_prefixes |= (prefixes & PREFIX_DATA); - } - break; - case w_mode: - mask = 0xfffff; - op = get16 (); - break; - default: - oappend (INTERNAL_DISASSEMBLER_ERROR); - return; - } + USED_REX (REX_W); - op &= mask; scratchbuf[0] = '$'; - print_operand_value (scratchbuf + 1, 1, op); + print_operand_value (scratchbuf + 1, 1, get64 ()); oappend_maybe_intel (scratchbuf); scratchbuf[0] = '\0'; } @@ -16054,11 +14948,13 @@ OP_J (int bytemode, int sizeflag) disp -= 0x100; break; case v_mode: - if (isa64 == amd64) + if (isa64 != intel64) + case dqw_mode: USED_REX (REX_W); if ((sizeflag & DFLAG) || (address_mode == mode_64bit - && (isa64 != amd64 || (rex & REX_W)))) + && ((isa64 == intel64 && bytemode != dqw_mode) + || (rex & REX_W)))) disp = get32s (); else { @@ -16075,7 +14971,7 @@ OP_J (int bytemode, int sizeflag) & ~((bfd_vma) 0xffff)); } if (address_mode != mode_64bit - || (isa64 == amd64 && !(rex & REX_W))) + || (isa64 != intel64 && !(rex & REX_W))) used_prefixes |= (prefixes & PREFIX_DATA); break; default: @@ -16501,7 +15397,6 @@ OP_EX (int bytemode, int sizeflag) && bytemode != xmm_mw_mode && bytemode != xmm_md_mode && bytemode != xmm_mq_mode - && bytemode != xmm_mdq_mode && bytemode != xmmq_mode && bytemode != evex_half_bcst_xmmq_mode && bytemode != ymm_mode @@ -16744,35 +15639,15 @@ CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) } static void -OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED, - int sizeflag ATTRIBUTE_UNUSED) -{ - /* mwaitx %eax,%ecx,%ebx */ - if (!intel_syntax) - { - const char **names = (address_mode == mode_64bit - ? names64 : names32); - strcpy (op_out[0], names[0]); - strcpy (op_out[1], names[1]); - strcpy (op_out[2], names[3]); - two_source_ops = 1; - } - /* Skip mod/rm byte. */ - MODRM_CHECK; - codep++; -} - -static void -OP_Mwait (int bytemode ATTRIBUTE_UNUSED, - int sizeflag ATTRIBUTE_UNUSED) +OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED) { - /* mwait %eax,%ecx */ + /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */ if (!intel_syntax) { - const char **names = (address_mode == mode_64bit - ? names64 : names32); - strcpy (op_out[0], names[0]); - strcpy (op_out[1], names[1]); + strcpy (op_out[0], names32[0]); + strcpy (op_out[1], names32[1]); + if (bytemode == eBX_reg) + strcpy (op_out[2], names32[3]); two_source_ops = 1; } /* Skip mod/rm byte. */ @@ -16784,27 +15659,25 @@ static void OP_Monitor (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) { - /* monitor %eax,%ecx,%edx" */ + /* monitor %{e,r,}ax,%ecx,%edx" */ if (!intel_syntax) { - const char **op1_names; const char **names = (address_mode == mode_64bit ? names64 : names32); - if (!(prefixes & PREFIX_ADDR)) - op1_names = (address_mode == mode_16bit - ? names16 : names); - else + if (prefixes & PREFIX_ADDR) { /* Remove "addr16/addr32". */ all_prefixes[last_addr_prefix] = 0; - op1_names = (address_mode != mode_32bit - ? names32 : names16); + names = (address_mode != mode_32bit + ? names32 : names16); used_prefixes |= PREFIX_ADDR; } - strcpy (op_out[0], op1_names[0]); - strcpy (op_out[1], names[1]); - strcpy (op_out[2], names[2]); + else if (address_mode == mode_16bit) + names = names16; + strcpy (op_out[0], names[0]); + strcpy (op_out[1], names32[1]); + strcpy (op_out[2], names32[2]); two_source_ops = 1; } /* Skip mod/rm byte. */ @@ -16847,6 +15720,18 @@ REP_Fixup (int bytemode, int sizeflag) } } +static void +SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) +{ + if ( isa64 != amd64 ) + return; + + obufp = obuf; + BadOp (); + mnemonicendp = obufp; + ++codep; +} + /* For BND-prefixed instructions 0xF2 prefix should be displayed as "bnd". */ @@ -17008,7 +15893,7 @@ CRC32_Fixup (int bytemode, int sizeflag) mnemonicendp = p; *p = '\0'; -skip: + skip: if (modrm.mod == 3) { int add; @@ -17095,6 +15980,7 @@ OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) return; reg = vex.register_specifier; + vex.register_specifier = 0; if (address_mode != mode_64bit) reg &= 7; else if (vex.evex && !vex.v) @@ -17378,6 +16264,7 @@ OP_Vex_2src_1 (int bytemode, int sizeflag) if (vex.w) { unsigned int reg = vex.register_specifier; + vex.register_specifier = 0; if (address_mode != mode_64bit) reg &= 7; @@ -17395,6 +16282,7 @@ OP_Vex_2src_2 (int bytemode, int sizeflag) else { unsigned int reg = vex.register_specifier; + vex.register_specifier = 0; if (address_mode != mode_64bit) reg &= 7; @@ -17472,11 +16360,7 @@ static void OP_EX_Vex (int bytemode, int sizeflag) { if (modrm.mod != 3) - { - if (vex.register_specifier != 0) - BadOp (); - need_vex_reg = 0; - } + need_vex_reg = 0; OP_EX (bytemode, sizeflag); } @@ -17484,30 +16368,10 @@ static void OP_XMM_Vex (int bytemode, int sizeflag) { if (modrm.mod != 3) - { - if (vex.register_specifier != 0) - BadOp (); - need_vex_reg = 0; - } + need_vex_reg = 0; OP_XMM (bytemode, sizeflag); } -static void -VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) -{ - switch (vex.length) - { - case 128: - mnemonicendp = stpcpy (obuf, "vzeroupper"); - break; - case 256: - mnemonicendp = stpcpy (obuf, "vzeroall"); - break; - default: - abort (); - } -} - static struct op vex_cmp_op[] = { { STRING_COMMA_LEN ("eq") }, @@ -17752,10 +16616,49 @@ MOVBE_Fixup (int bytemode, int sizeflag) mnemonicendp = p; *p = '\0'; -skip: + skip: OP_M (bytemode, sizeflag); } +static void +MOVSXD_Fixup (int bytemode, int sizeflag) +{ + /* Add proper suffix to "movsxd". */ + char *p = mnemonicendp; + + switch (bytemode) + { + case movsxd_mode: + if (intel_syntax) + { + *p++ = 'x'; + *p++ = 'd'; + goto skip; + } + + USED_REX (REX_W); + if (rex & REX_W) + { + *p++ = 'l'; + *p++ = 'q'; + } + else + { + *p++ = 'x'; + *p++ = 'd'; + } + break; + default: + oappend (INTERNAL_DISASSEMBLER_ERROR); + break; + } + + skip: + mnemonicendp = p; + *p = '\0'; + OP_E (bytemode, sizeflag); +} + static void OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) { @@ -17784,6 +16687,7 @@ OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) { const char **names; unsigned int reg = vex.register_specifier; + vex.register_specifier = 0; if (rex & REX_W) names = names64; @@ -17817,11 +16721,19 @@ OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED) { if (!vex.evex || (bytemode != evex_rounding_mode + && bytemode != evex_rounding_64_mode && bytemode != evex_sae_mode)) abort (); if (modrm.mod == 3 && vex.b) switch (bytemode) { + case evex_rounding_64_mode: + if (address_mode != mode_64bit) + { + oappend ("(bad)"); + break; + } + /* Fall through. */ case evex_rounding_mode: oappend (names_rounding[vex.ll]); break;