X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Fi386-dis.c;h=930569e0f73a2544d317e4542a0fe5d9dd54e4cd;hb=e90426589d7c783b7e458162baaac1431fc33bd5;hp=5c5f926d30d35538e18c51941a2aa9028e115dae;hpb=1a0670f37442b7ae904932b347353046126b990c;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 5c5f926d30..930569e0f7 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -1,5 +1,5 @@ /* Print i386 instructions for GDB, the GNU debugger. - Copyright (C) 1988-2016 Free Software Foundation, Inc. + Copyright (C) 1988-2018 Free Software Foundation, Inc. This file is part of the GNU opcodes library. @@ -33,7 +33,7 @@ the Intel manual for details. */ #include "sysdep.h" -#include "dis-asm.h" +#include "disassemble.h" #include "opintl.h" #include "opcode/i386.h" #include "libiberty.h" @@ -95,10 +95,10 @@ static void OP_XMM_VexW (int, int); static void OP_Rounding (int, int); static void OP_REG_VexI4 (int, int); static void PCLMUL_Fixup (int, int); -static void VEXI4_Fixup (int, int); static void VZERO_Fixup (int, int); static void VCMP_Fixup (int, int); static void VPCMP_Fixup (int, int); +static void VPCOM_Fixup (int, int); static void OP_0f07 (int, int); static void OP_Monitor (int, int); static void OP_Mwait (int, int); @@ -110,6 +110,7 @@ static void CMP_Fixup (int, int); static void BadOp (void); static void REP_Fixup (int, int); static void BND_Fixup (int, int); +static void NOTRACK_Fixup (int, int); static void HLE_Fixup1 (int, int); static void HLE_Fixup2 (int, int); static void HLE_Fixup3 (int, int); @@ -117,6 +118,7 @@ static void CMPXCHG8B_Fixup (int, int); static void XMM_Fixup (int, int); static void CRC32_Fixup (int, int); static void FXSAVE_Fixup (int, int); +static void PCMPESTR_Fixup (int, int); static void OP_LWPCB_E (int, int); static void OP_LWP_E (int, int); static void OP_Vex_2src_1 (int, int); @@ -246,13 +248,14 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define Eb { OP_E, b_mode } #define Ebnd { OP_E, bnd_mode } #define EbS { OP_E, b_swap_mode } +#define EbndS { OP_E, bnd_swap_mode } #define Ev { OP_E, v_mode } +#define Eva { OP_E, va_mode } #define Ev_bnd { OP_E, v_bnd_mode } #define EvS { OP_E, v_swap_mode } #define Ed { OP_E, d_mode } #define Edq { OP_E, dq_mode } #define Edqw { OP_E, dqw_mode } -#define EdqwS { OP_E, dqw_swap_mode } #define Edqb { OP_E, dqb_mode } #define Edb { OP_E, db_mode } #define Edw { OP_E, dw_mode } @@ -270,6 +273,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define Mo { OP_M, o_mode } #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ #define Mq { OP_M, q_mode } +#define Mv_bnd { OP_M, v_bndmk_mode } #define Mx { OP_M, x_mode } #define Mxmm { OP_M, xmm_mode } #define Gb { OP_G, b_mode } @@ -278,6 +282,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define Gd { OP_G, d_mode } #define Gdq { OP_G, dq_mode } #define Gm { OP_G, m_mode } +#define Gva { OP_G, va_mode } #define Gw { OP_G, w_mode } #define Rd { OP_R, d_mode } #define Rdq { OP_R, dq_mode } @@ -375,7 +380,9 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define EMS { OP_EM, v_swap_mode } #define EMd { OP_EM, d_mode } #define EMx { OP_EM, x_mode } +#define EXbScalar { OP_EX, b_scalar_mode } #define EXw { OP_EX, w_mode } +#define EXwScalar { OP_EX, w_scalar_mode } #define EXd { OP_EX, d_mode } #define EXdScalar { OP_EX, d_scalar_mode } #define EXdS { OP_EX, d_swap_mode } @@ -419,7 +426,6 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define Vex128 { OP_VEX, vex128_mode } #define Vex256 { OP_VEX, vex256_mode } #define VexGdq { OP_VEX, dq_mode } -#define VexI4 { VEXI4_Fixup, 0} #define EXdVex { OP_EX_Vex, d_mode } #define EXdVexS { OP_EX_Vex, d_swap_mode } #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode } @@ -438,6 +444,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define VZERO { VZERO_Fixup, 0 } #define VCMP { VCMP_Fixup, 0 } #define VPCMP { VPCMP_Fixup, 0 } +#define VPCOM { VPCOM_Fixup, 0 } #define EXxEVexR { OP_Rounding, evex_rounding_mode } #define EXxEVexS { OP_Rounding, evex_sae_mode } @@ -473,6 +480,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define Evh3 { HLE_Fixup3, v_mode } #define BND { BND_Fixup, 0 } +#define NOTRACK { NOTRACK_Fixup, 0 } #define cond_jump_flag { NULL, cond_jump_mode } #define loop_jcxz_flag { NULL, loop_jcxz_mode } @@ -494,6 +502,8 @@ enum v_mode, /* operand size depends on prefixes with operand swapped */ v_swap_mode, + /* operand size depends on address prefix */ + va_mode, /* word operand */ w_mode, /* double word operand */ @@ -552,12 +562,16 @@ enum cond_jump_mode, loop_jcxz_mode, v_bnd_mode, + /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */ + v_bndmk_mode, /* operand size depends on REX prefixes. */ dq_mode, /* registers like dq_mode, memory like w_mode. */ dqw_mode, - dqw_swap_mode, + /* bounds operand */ bnd_mode, + /* bounds operand with operand swapped */ + bnd_swap_mode, /* 4- or 6-byte pointer operand */ f_mode, const_1_mode, @@ -597,6 +611,10 @@ enum /* scalar, ignore vector length. */ scalar_mode, + /* like b_mode, ignore vector length. */ + b_scalar_mode, + /* like w_mode, ignore vector length. */ + w_scalar_mode, /* like d_mode, ignore vector length. */ d_scalar_mode, /* like d_swap_mode, ignore vector length. */ @@ -706,7 +724,7 @@ enum { REG_80 = 0, REG_81, - REG_82, + REG_83, REG_8F, REG_C0, REG_C1, @@ -724,6 +742,8 @@ enum REG_0F01, REG_0F0D, REG_0F18, + REG_0F1C_MOD_0, + REG_0F1E_MOD_3, REG_0F71, REG_0F72, REG_0F73, @@ -777,6 +797,8 @@ enum MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0, MOD_0F1B_PREFIX_1, + MOD_0F1C_PREFIX_0, + MOD_0F1E_PREFIX_1, MOD_0F24, MOD_0F26, MOD_0F2B_PREFIX_0, @@ -815,6 +837,10 @@ enum MOD_0FE7_PREFIX_2, MOD_0FF0_PREFIX_3, MOD_0F382A_PREFIX_2, + MOD_0F38F5_PREFIX_2, + MOD_0F38F6_PREFIX_0, + MOD_0F38F8_PREFIX_2, + MOD_0F38F9_PREFIX_0, MOD_62_32BIT, MOD_C4_32BIT, MOD_C5_32BIT, @@ -934,7 +960,7 @@ enum RM_0F01_REG_3, RM_0F01_REG_5, RM_0F01_REG_7, - RM_0FAE_REG_5, + RM_0F1E_MOD_3_REG_7, RM_0FAE_REG_6, RM_0FAE_REG_7 }; @@ -942,12 +968,18 @@ enum enum { PREFIX_90 = 0, + PREFIX_MOD_0_0F01_REG_5, + PREFIX_MOD_3_0F01_REG_5_RM_0, + PREFIX_MOD_3_0F01_REG_5_RM_2, + PREFIX_0F09, PREFIX_0F10, PREFIX_0F11, PREFIX_0F12, PREFIX_0F16, PREFIX_0F1A, PREFIX_0F1B, + PREFIX_0F1C, + PREFIX_0F1E, PREFIX_0F2A, PREFIX_0F2B, PREFIX_0F2C, @@ -986,9 +1018,11 @@ enum PREFIX_0FAE_REG_3, PREFIX_MOD_0_0FAE_REG_4, PREFIX_MOD_3_0FAE_REG_4, - PREFIX_0FAE_REG_6, + PREFIX_MOD_0_0FAE_REG_5, + PREFIX_MOD_3_0FAE_REG_5, + PREFIX_MOD_0_0FAE_REG_6, + PREFIX_MOD_1_0FAE_REG_6, PREFIX_0FAE_REG_7, - PREFIX_RM_0_0FAE_REG_7, PREFIX_0FB8, PREFIX_0FBC, PREFIX_0FBD, @@ -1043,6 +1077,7 @@ enum PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD, + PREFIX_0F38CF, PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, @@ -1050,7 +1085,10 @@ enum PREFIX_0F38DF, PREFIX_0F38F0, PREFIX_0F38F1, + PREFIX_0F38F5, PREFIX_0F38F6, + PREFIX_0F38F8, + PREFIX_0F38F9, PREFIX_0F3A08, PREFIX_0F3A09, PREFIX_0F3A0A, @@ -1074,6 +1112,8 @@ enum PREFIX_0F3A62, PREFIX_0F3A63, PREFIX_0F3ACC, + PREFIX_0F3ACE, + PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F10, PREFIX_VEX_0F11, @@ -1295,6 +1335,7 @@ enum PREFIX_VEX_0F38BD, PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, + PREFIX_VEX_0F38CF, PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD, @@ -1371,6 +1412,8 @@ enum PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F, + PREFIX_VEX_0F3ACE, + PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF, PREFIX_VEX_0F3AF0, @@ -1549,13 +1592,25 @@ enum PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, + PREFIX_EVEX_0F3850, + PREFIX_EVEX_0F3851, + PREFIX_EVEX_0F3852, + PREFIX_EVEX_0F3853, + PREFIX_EVEX_0F3854, + PREFIX_EVEX_0F3855, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, + PREFIX_EVEX_0F3862, + PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, + PREFIX_EVEX_0F3870, + PREFIX_EVEX_0F3871, + PREFIX_EVEX_0F3872, + PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, @@ -1573,6 +1628,7 @@ enum PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, + PREFIX_EVEX_0F388F, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, @@ -1627,6 +1683,11 @@ enum PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, + PREFIX_EVEX_0F38CF, + PREFIX_EVEX_0F38DC, + PREFIX_EVEX_0F38DD, + PREFIX_EVEX_0F38DE, + PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, @@ -1664,6 +1725,7 @@ enum PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, + PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3A50, PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, @@ -1671,7 +1733,13 @@ enum PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66, - PREFIX_EVEX_0F3A67 + PREFIX_EVEX_0F3A67, + PREFIX_EVEX_0F3A70, + PREFIX_EVEX_0F3A71, + PREFIX_EVEX_0F3A72, + PREFIX_EVEX_0F3A73, + PREFIX_EVEX_0F3ACE, + PREFIX_EVEX_0F3ACF }; enum @@ -1693,6 +1761,7 @@ enum X86_64_63, X86_64_6D, X86_64_6F, + X86_64_82, X86_64_9A, X86_64_C4, X86_64_C5, @@ -1711,8 +1780,7 @@ enum enum { THREE_BYTE_0F38 = 0, - THREE_BYTE_0F3A, - THREE_BYTE_0F7A + THREE_BYTE_0F3A }; enum @@ -1826,10 +1894,6 @@ enum VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0, VEX_LEN_0F38DB_P_2, - VEX_LEN_0F38DC_P_2, - VEX_LEN_0F38DD_P_2, - VEX_LEN_0F38DE_P_2, - VEX_LEN_0F38DF_P_2, VEX_LEN_0F38F2_P_0, VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0, @@ -1863,7 +1927,6 @@ enum VEX_LEN_0F3A38_P_2, VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, - VEX_LEN_0F3A44_P_2, VEX_LEN_0F3A46_P_2, VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, @@ -2150,11 +2213,8 @@ enum VEX_W_0F385A_P_2_M_0, VEX_W_0F3878_P_2, VEX_W_0F3879_P_2, + VEX_W_0F38CF_P_2, VEX_W_0F38DB_P_2, - VEX_W_0F38DC_P_2, - VEX_W_0F38DD_P_2, - VEX_W_0F38DE_P_2, - VEX_W_0F38DF_P_2, VEX_W_0F3A00_P_2, VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, @@ -2184,17 +2244,16 @@ enum VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2, VEX_W_0F3A42_P_2, - VEX_W_0F3A44_P_2, VEX_W_0F3A46_P_2, VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2, - VEX_W_0F3A60_P_2, - VEX_W_0F3A61_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2, + VEX_W_0F3ACE_P_2, + VEX_W_0F3ACF_P_2, VEX_W_0F3ADF_P_2, EVEX_W_0F10_P_0, @@ -2378,11 +2437,19 @@ enum EVEX_W_0F3839_P_1, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, + EVEX_W_0F3854_P_2, + EVEX_W_0F3855_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, + EVEX_W_0F3862_P_2, + EVEX_W_0F3863_P_2, EVEX_W_0F3866_P_2, + EVEX_W_0F3870_P_2, + EVEX_W_0F3871_P_2, + EVEX_W_0F3872_P_2, + EVEX_W_0F3873_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, @@ -2430,7 +2497,13 @@ enum EVEX_W_0F3A56_P_2, EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, - EVEX_W_0F3A67_P_2 + EVEX_W_0F3A67_P_2, + EVEX_W_0F3A70_P_2, + EVEX_W_0F3A71_P_2, + EVEX_W_0F3A72_P_2, + EVEX_W_0F3A73_P_2, + EVEX_W_0F3ACE_P_2, + EVEX_W_0F3ACF_P_2 }; typedef void (*op_rtn) (int bytemode, int sizeflag); @@ -2478,8 +2551,7 @@ struct dis386 { prefix and behave as 'S' otherwise 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) 'X' => print 's', 'd' depending on data16 prefix (for XMM) - 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and - suffix_always is true. + 'Y' unused. 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise '!' => change condition from true to false or from false to true. '%' => add 1 upper case letter to the macro. @@ -2661,8 +2733,8 @@ static const struct dis386 dis386[] = { /* 80 */ { REG_TABLE (REG_80) }, { REG_TABLE (REG_81) }, - { Bad_Opcode }, - { REG_TABLE (REG_82) }, + { X86_64_TABLE (X86_64_82) }, + { REG_TABLE (REG_83) }, { "testB", { Eb, Gb }, 0 }, { "testS", { Ev, Gv }, 0 }, { "xchgB", { Ebh2, Gb }, 0 }, @@ -2816,7 +2888,7 @@ static const struct dis386 dis386_twobyte[] = { { "sysret%LP", { XX }, 0 }, /* 08 */ { "invd", { XX }, 0 }, - { "wbinvd", { XX }, 0 }, + { PREFIX_TABLE (PREFIX_0F09) }, { Bad_Opcode }, { "ud2", { XX }, 0 }, { Bad_Opcode }, @@ -2837,9 +2909,9 @@ static const struct dis386 dis386_twobyte[] = { { "nopQ", { Ev }, 0 }, { PREFIX_TABLE (PREFIX_0F1A) }, { PREFIX_TABLE (PREFIX_0F1B) }, + { PREFIX_TABLE (PREFIX_0F1C) }, { "nopQ", { Ev }, 0 }, - { "nopQ", { Ev }, 0 }, - { "nopQ", { Ev }, 0 }, + { PREFIX_TABLE (PREFIX_0F1E) }, { "nopQ", { Ev }, 0 }, /* 20 */ { "movZ", { Rm, Cm }, 0 }, @@ -2943,7 +3015,7 @@ static const struct dis386 dis386_twobyte[] = { /* 78 */ { PREFIX_TABLE (PREFIX_0F78) }, { PREFIX_TABLE (PREFIX_0F79) }, - { THREE_BYTE_TABLE (THREE_BYTE_0F7A) }, + { Bad_Opcode }, { Bad_Opcode }, { PREFIX_TABLE (PREFIX_0F7C) }, { PREFIX_TABLE (PREFIX_0F7D) }, @@ -3014,7 +3086,7 @@ static const struct dis386 dis386_twobyte[] = { { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */ /* b8 */ { PREFIX_TABLE (PREFIX_0FB8) }, - { "ud1", { XX }, 0 }, + { "ud1S", { Gv, Ev }, 0 }, { REG_TABLE (REG_0FBA) }, { "btcS", { Evh1, Gv }, 0 }, { PREFIX_TABLE (PREFIX_0FBC) }, @@ -3092,7 +3164,7 @@ static const struct dis386 dis386_twobyte[] = { { "paddb", { MX, EM }, PREFIX_OPCODE }, { "paddw", { MX, EM }, PREFIX_OPCODE }, { "paddd", { MX, EM }, PREFIX_OPCODE }, - { Bad_Opcode }, + { "ud0S", { Gv, Ev }, 0 }, }; static const unsigned char onebyte_has_modrm[256] = { @@ -3132,11 +3204,11 @@ static const unsigned char twobyte_has_modrm[256] = { /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ - /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */ + /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */ /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ - /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */ + /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */ /* ------------------------------- */ /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ }; @@ -3399,7 +3471,7 @@ static const struct dis386 reg_table[][8] = { { "xorQ", { Evh1, Iv }, 0 }, { "cmpQ", { Ev, Iv }, 0 }, }, - /* REG_82 */ + /* REG_83 */ { { "addQ", { Evh1, sIb }, 0 }, { "orQ", { Evh1, sIb }, 0 }, @@ -3427,7 +3499,7 @@ static const struct dis386 reg_table[][8] = { { "rcrA", { Eb, Ib }, 0 }, { "shlA", { Eb, Ib }, 0 }, { "shrA", { Eb, Ib }, 0 }, - { Bad_Opcode }, + { "shlA", { Eb, Ib }, 0 }, { "sarA", { Eb, Ib }, 0 }, }, /* REG_C1 */ @@ -3438,7 +3510,7 @@ static const struct dis386 reg_table[][8] = { { "rcrQ", { Ev, Ib }, 0 }, { "shlQ", { Ev, Ib }, 0 }, { "shrQ", { Ev, Ib }, 0 }, - { Bad_Opcode }, + { "shlQ", { Ev, Ib }, 0 }, { "sarQ", { Ev, Ib }, 0 }, }, /* REG_C6 */ @@ -3471,7 +3543,7 @@ static const struct dis386 reg_table[][8] = { { "rcrA", { Eb, I1 }, 0 }, { "shlA", { Eb, I1 }, 0 }, { "shrA", { Eb, I1 }, 0 }, - { Bad_Opcode }, + { "shlA", { Eb, I1 }, 0 }, { "sarA", { Eb, I1 }, 0 }, }, /* REG_D1 */ @@ -3482,7 +3554,7 @@ static const struct dis386 reg_table[][8] = { { "rcrQ", { Ev, I1 }, 0 }, { "shlQ", { Ev, I1 }, 0 }, { "shrQ", { Ev, I1 }, 0 }, - { Bad_Opcode }, + { "shlQ", { Ev, I1 }, 0 }, { "sarQ", { Ev, I1 }, 0 }, }, /* REG_D2 */ @@ -3493,7 +3565,7 @@ static const struct dis386 reg_table[][8] = { { "rcrA", { Eb, CL }, 0 }, { "shlA", { Eb, CL }, 0 }, { "shrA", { Eb, CL }, 0 }, - { Bad_Opcode }, + { "shlA", { Eb, CL }, 0 }, { "sarA", { Eb, CL }, 0 }, }, /* REG_D3 */ @@ -3504,13 +3576,13 @@ static const struct dis386 reg_table[][8] = { { "rcrQ", { Ev, CL }, 0 }, { "shlQ", { Ev, CL }, 0 }, { "shrQ", { Ev, CL }, 0 }, - { Bad_Opcode }, + { "shlQ", { Ev, CL }, 0 }, { "sarQ", { Ev, CL }, 0 }, }, /* REG_F6 */ { { "testA", { Eb, Ib }, 0 }, - { Bad_Opcode }, + { "testA", { Eb, Ib }, 0 }, { "notA", { Ebh1 }, 0 }, { "negA", { Ebh1 }, 0 }, { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */ @@ -3521,7 +3593,7 @@ static const struct dis386 reg_table[][8] = { /* REG_F7 */ { { "testQ", { Ev, Iv }, 0 }, - { Bad_Opcode }, + { "testQ", { Ev, Iv }, 0 }, { "notQ", { Evh1 }, 0 }, { "negQ", { Evh1 }, 0 }, { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */ @@ -3538,9 +3610,9 @@ static const struct dis386 reg_table[][8] = { { { "incQ", { Evh1 }, 0 }, { "decQ", { Evh1 }, 0 }, - { "call{&|}", { indirEv, BND }, 0 }, + { "call{&|}", { NOTRACK, indirEv, BND }, 0 }, { MOD_TABLE (MOD_FF_REG_3) }, - { "jmp{&|}", { indirEv, BND }, 0 }, + { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 }, { MOD_TABLE (MOD_FF_REG_5) }, { "pushU", { stackEv }, 0 }, { Bad_Opcode }, @@ -3589,6 +3661,28 @@ static const struct dis386 reg_table[][8] = { { MOD_TABLE (MOD_0F18_REG_6) }, { MOD_TABLE (MOD_0F18_REG_7) }, }, + /* REG_0F1C_MOD_0 */ + { + { "cldemote", { Mb }, 0 }, + { "nopQ", { Ev }, 0 }, + { "nopQ", { Ev }, 0 }, + { "nopQ", { Ev }, 0 }, + { "nopQ", { Ev }, 0 }, + { "nopQ", { Ev }, 0 }, + { "nopQ", { Ev }, 0 }, + { "nopQ", { Ev }, 0 }, + }, + /* REG_0F1E_MOD_3 */ + { + { "nopQ", { Ev }, 0 }, + { "rdsspK", { Rdq }, PREFIX_OPCODE }, + { "nopQ", { Ev }, 0 }, + { "nopQ", { Ev }, 0 }, + { "nopQ", { Ev }, 0 }, + { "nopQ", { Ev }, 0 }, + { "nopQ", { Ev }, 0 }, + { RM_TABLE (RM_0F1E_MOD_3_REG_7) }, + }, /* REG_0F71 */ { { Bad_Opcode }, @@ -3758,6 +3852,30 @@ static const struct dis386 prefix_table[][4] = { { NULL, { { NULL, 0 } }, PREFIX_IGNORED } }, + /* PREFIX_MOD_0_0F01_REG_5 */ + { + { Bad_Opcode }, + { "rstorssp", { Mq }, PREFIX_OPCODE }, + }, + + /* PREFIX_MOD_3_0F01_REG_5_RM_0 */ + { + { Bad_Opcode }, + { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE }, + }, + + /* PREFIX_MOD_3_0F01_REG_5_RM_2 */ + { + { Bad_Opcode }, + { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE }, + }, + + /* PREFIX_0F09 */ + { + { "wbinvd", { XX }, 0 }, + { "wbnoinvd", { XX }, 0 }, + }, + /* PREFIX_0F10 */ { { "movups", { XM, EXx }, PREFIX_OPCODE }, @@ -3801,10 +3919,26 @@ static const struct dis386 prefix_table[][4] = { { { MOD_TABLE (MOD_0F1B_PREFIX_0) }, { MOD_TABLE (MOD_0F1B_PREFIX_1) }, - { "bndmov", { Ebnd, Gbnd }, 0 }, + { "bndmov", { EbndS, Gbnd }, 0 }, { "bndcn", { Gbnd, Ev_bnd }, 0 }, }, + /* PREFIX_0F1C */ + { + { MOD_TABLE (MOD_0F1C_PREFIX_0) }, + { "nopQ", { Ev }, PREFIX_OPCODE }, + { "nopQ", { Ev }, PREFIX_OPCODE }, + { "nopQ", { Ev }, PREFIX_OPCODE }, + }, + + /* PREFIX_0F1E */ + { + { "nopQ", { Ev }, PREFIX_OPCODE }, + { MOD_TABLE (MOD_0F1E_PREFIX_1) }, + { "nopQ", { Ev }, PREFIX_OPCODE }, + { "nopQ", { Ev }, PREFIX_OPCODE }, + }, + /* PREFIX_0F2A */ { { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE }, @@ -3824,17 +3958,17 @@ static const struct dis386 prefix_table[][4] = { /* PREFIX_0F2C */ { { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE }, - { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE }, + { "cvttss2si", { Gv, EXd }, PREFIX_OPCODE }, { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE }, - { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE }, + { "cvttsd2si", { Gv, EXq }, PREFIX_OPCODE }, }, /* PREFIX_0F2D */ { { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE }, - { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE }, + { "cvtss2si", { Gv, EXd }, PREFIX_OPCODE }, { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE }, - { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE }, + { "cvtsd2si", { Gv, EXq }, PREFIX_OPCODE }, }, /* PREFIX_0F2E */ @@ -4080,25 +4214,37 @@ static const struct dis386 prefix_table[][4] = { { "ptwrite%LQ", { Edq }, 0 }, }, - /* PREFIX_0FAE_REG_6 */ + /* PREFIX_MOD_0_0FAE_REG_5 */ { - { "xsaveopt", { FXSAVE }, 0 }, - { Bad_Opcode }, - { "clwb", { Mb }, 0 }, + { "xrstor", { FXSAVE }, PREFIX_OPCODE }, }, - /* PREFIX_0FAE_REG_7 */ + /* PREFIX_MOD_3_0FAE_REG_5 */ { - { "clflush", { Mb }, 0 }, - { Bad_Opcode }, - { "clflushopt", { Mb }, 0 }, + { "lfence", { Skip_MODRM }, 0 }, + { "incsspK", { Rdq }, PREFIX_OPCODE }, }, - /* PREFIX_RM_0_0FAE_REG_7 */ + /* PREFIX_MOD_0_0FAE_REG_6 */ { - { "sfence", { Skip_MODRM }, 0 }, + { "xsaveopt", { FXSAVE }, PREFIX_OPCODE }, + { "clrssbsy", { Mq }, PREFIX_OPCODE }, + { "clwb", { Mb }, PREFIX_OPCODE }, + }, + + /* PREFIX_MOD_1_0FAE_REG_6 */ + { + { RM_TABLE (RM_0FAE_REG_6) }, + { "umonitor", { Eva }, PREFIX_OPCODE }, + { "tpause", { Edq }, PREFIX_OPCODE }, + { "umwait", { Edq }, PREFIX_OPCODE }, + }, + + /* PREFIX_0FAE_REG_7 */ + { + { "clflush", { Mb }, 0 }, { Bad_Opcode }, - { "pcommit", { Skip_MODRM }, 0 }, + { "clflushopt", { Mb }, 0 }, }, /* PREFIX_0FB8 */ @@ -4469,6 +4615,13 @@ static const struct dis386 prefix_table[][4] = { { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE }, }, + /* PREFIX_0F38CF */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE }, + }, + /* PREFIX_0F38DB */ { { Bad_Opcode }, @@ -4520,14 +4673,33 @@ static const struct dis386 prefix_table[][4] = { { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE }, }, - /* PREFIX_0F38F6 */ + /* PREFIX_0F38F5 */ { { Bad_Opcode }, + { Bad_Opcode }, + { MOD_TABLE (MOD_0F38F5_PREFIX_2) }, + }, + + /* PREFIX_0F38F6 */ + { + { MOD_TABLE (MOD_0F38F6_PREFIX_0) }, { "adoxS", { Gdq, Edq}, PREFIX_OPCODE }, { "adcxS", { Gdq, Edq}, PREFIX_OPCODE }, { Bad_Opcode }, }, + /* PREFIX_0F38F8 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { MOD_TABLE (MOD_0F38F8_PREFIX_2) }, + }, + + /* PREFIX_0F38F9 */ + { + { MOD_TABLE (MOD_0F38F9_PREFIX_0) }, + }, + /* PREFIX_0F3A08 */ { { Bad_Opcode }, @@ -4658,14 +4830,14 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { "pcmpestrm", { XM, EXx, Ib }, PREFIX_OPCODE }, + { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE }, }, /* PREFIX_0F3A61 */ { { Bad_Opcode }, { Bad_Opcode }, - { "pcmpestri", { XM, EXx, Ib }, PREFIX_OPCODE }, + { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE }, }, /* PREFIX_0F3A62 */ @@ -4687,6 +4859,20 @@ static const struct dis386 prefix_table[][4] = { { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE }, }, + /* PREFIX_0F3ACE */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE }, + }, + + /* PREFIX_0F3ACF */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE }, + }, + /* PREFIX_0F3ADF */ { { Bad_Opcode }, @@ -6254,6 +6440,13 @@ static const struct dis386 prefix_table[][4] = { { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, }, + /* PREFIX_VEX_0F38CF */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F38CF_P_2) }, + }, + /* PREFIX_VEX_0F38DB */ { { Bad_Opcode }, @@ -6265,28 +6458,28 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F38DC_P_2) }, + { "vaesenc", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F38DD */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F38DD_P_2) }, + { "vaesenclast", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F38DE */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F38DE_P_2) }, + { "vaesdec", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F38DF */ { { Bad_Opcode }, { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F38DF_P_2) }, + { "vaesdeclast", { XM, Vex, EXx }, 0 }, }, /* PREFIX_VEX_0F38F2 */ @@ -6568,7 +6761,7 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F3A44_P_2) }, + { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, 0 }, }, /* PREFIX_VEX_0F3A46 */ @@ -6617,28 +6810,28 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, }, /* PREFIX_VEX_0F3A5D */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, }, /* PREFIX_VEX_0F3A5E */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, }, /* PREFIX_VEX_0F3A5F */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, }, /* PREFIX_VEX_0F3A60 */ @@ -6674,14 +6867,14 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, }, /* PREFIX_VEX_0F3A69 */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, }, /* PREFIX_VEX_0F3A6A */ @@ -6702,14 +6895,14 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, }, /* PREFIX_VEX_0F3A6D */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, }, /* PREFIX_VEX_0F3A6E */ @@ -6730,14 +6923,14 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, }, /* PREFIX_VEX_0F3A79 */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, }, /* PREFIX_VEX_0F3A7A */ @@ -6758,7 +6951,7 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, { Bad_Opcode }, }, @@ -6766,7 +6959,7 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, }, /* PREFIX_VEX_0F3A7E */ @@ -6783,6 +6976,20 @@ static const struct dis386 prefix_table[][4] = { { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) }, }, + /* PREFIX_VEX_0F3ACE */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F3ACE_P_2) }, + }, + + /* PREFIX_VEX_0F3ACF */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { VEX_W_TABLE (VEX_W_0F3ACF_P_2) }, + }, + /* PREFIX_VEX_0F3ADF */ { { Bad_Opcode }, @@ -6893,6 +7100,12 @@ static const struct dis386 x86_64_table[][2] = { { "outs{G|}", { indirDXr, Xz }, 0 }, }, + /* X86_64_82 */ + { + /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */ + { REG_TABLE (REG_80) }, + }, + /* X86_64_9A */ { { "Jcall{T|}", { Ap }, 0 }, @@ -7204,7 +7417,7 @@ static const struct dis386 three_byte_table[][256] = { { PREFIX_TABLE (PREFIX_0F38CC) }, { PREFIX_TABLE (PREFIX_0F38CD) }, { Bad_Opcode }, - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_0F38CF) }, /* d0 */ { Bad_Opcode }, { Bad_Opcode }, @@ -7247,12 +7460,12 @@ static const struct dis386 three_byte_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_0F38F5) }, { PREFIX_TABLE (PREFIX_0F38F6) }, { Bad_Opcode }, /* f8 */ - { Bad_Opcode }, - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_0F38F8) }, + { PREFIX_TABLE (PREFIX_0F38F9) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -7494,8 +7707,8 @@ static const struct dis386 three_byte_table[][256] = { { Bad_Opcode }, { PREFIX_TABLE (PREFIX_0F3ACC) }, { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_0F3ACE) }, + { PREFIX_TABLE (PREFIX_0F3ACF) }, /* d0 */ { Bad_Opcode }, { Bad_Opcode }, @@ -7551,298 +7764,6 @@ static const struct dis386 three_byte_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, }, - - /* THREE_BYTE_0F7A */ - { - /* 00 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* 08 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* 10 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* 18 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* 20 */ - { "ptest", { XX }, PREFIX_OPCODE }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* 28 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* 30 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* 38 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* 40 */ - { Bad_Opcode }, - { "phaddbw", { XM, EXq }, PREFIX_OPCODE }, - { "phaddbd", { XM, EXq }, PREFIX_OPCODE }, - { "phaddbq", { XM, EXq }, PREFIX_OPCODE }, - { Bad_Opcode }, - { Bad_Opcode }, - { "phaddwd", { XM, EXq }, PREFIX_OPCODE }, - { "phaddwq", { XM, EXq }, PREFIX_OPCODE }, - /* 48 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { "phadddq", { XM, EXq }, PREFIX_OPCODE }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* 50 */ - { Bad_Opcode }, - { "phaddubw", { XM, EXq }, PREFIX_OPCODE }, - { "phaddubd", { XM, EXq }, PREFIX_OPCODE }, - { "phaddubq", { XM, EXq }, PREFIX_OPCODE }, - { Bad_Opcode }, - { Bad_Opcode }, - { "phadduwd", { XM, EXq }, PREFIX_OPCODE }, - { "phadduwq", { XM, EXq }, PREFIX_OPCODE }, - /* 58 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { "phaddudq", { XM, EXq }, PREFIX_OPCODE }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* 60 */ - { Bad_Opcode }, - { "phsubbw", { XM, EXq }, PREFIX_OPCODE }, - { "phsubbd", { XM, EXq }, PREFIX_OPCODE }, - { "phsubbq", { XM, EXq }, PREFIX_OPCODE }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* 68 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* 70 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* 78 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* 80 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* 88 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* 90 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* 98 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* a0 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* a8 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* b0 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* b8 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* c0 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* c8 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* d0 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* d8 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* e0 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* e8 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* f0 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - /* f8 */ - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - }, }; static const struct dis386 xop_table[][256] = { @@ -7998,9 +7919,9 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, - { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, - { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, + { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, + { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, /* 88 */ { Bad_Opcode }, { Bad_Opcode }, @@ -8008,17 +7929,17 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, - { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, + { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, /* 90 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, - { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, - { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, + { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, + { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, /* 98 */ { Bad_Opcode }, { Bad_Opcode }, @@ -8026,16 +7947,16 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, - { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, + { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, /* a0 */ { Bad_Opcode }, { Bad_Opcode }, - { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, - { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, + { "vpperm", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, { Bad_Opcode }, { Bad_Opcode }, - { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, { Bad_Opcode }, /* a8 */ { Bad_Opcode }, @@ -8053,7 +7974,7 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, { Bad_Opcode }, /* b8 */ { Bad_Opcode }, @@ -9248,7 +9169,7 @@ static const struct dis386 vex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_VEX_0F38CF) }, /* d0 */ { Bad_Opcode }, { Bad_Opcode }, @@ -9538,8 +9459,8 @@ static const struct dis386 vex_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { PREFIX_TABLE(PREFIX_VEX_0F3ACE) }, + { PREFIX_TABLE(PREFIX_VEX_0F3ACF) }, /* d0 */ { Bad_Opcode }, { Bad_Opcode }, @@ -9679,26 +9600,26 @@ static const struct dis386 vex_len_table[][2] = { /* VEX_LEN_0F2C_P_1 */ { - { "vcvttss2siY", { Gv, EXdScalar }, 0 }, - { "vcvttss2siY", { Gv, EXdScalar }, 0 }, + { "vcvttss2si", { Gv, EXdScalar }, 0 }, + { "vcvttss2si", { Gv, EXdScalar }, 0 }, }, /* VEX_LEN_0F2C_P_3 */ { - { "vcvttsd2siY", { Gv, EXqScalar }, 0 }, - { "vcvttsd2siY", { Gv, EXqScalar }, 0 }, + { "vcvttsd2si", { Gv, EXqScalar }, 0 }, + { "vcvttsd2si", { Gv, EXqScalar }, 0 }, }, /* VEX_LEN_0F2D_P_1 */ { - { "vcvtss2siY", { Gv, EXdScalar }, 0 }, - { "vcvtss2siY", { Gv, EXdScalar }, 0 }, + { "vcvtss2si", { Gv, EXdScalar }, 0 }, + { "vcvtss2si", { Gv, EXdScalar }, 0 }, }, /* VEX_LEN_0F2D_P_3 */ { - { "vcvtsd2siY", { Gv, EXqScalar }, 0 }, - { "vcvtsd2siY", { Gv, EXqScalar }, 0 }, + { "vcvtsd2si", { Gv, EXqScalar }, 0 }, + { "vcvtsd2si", { Gv, EXqScalar }, 0 }, }, /* VEX_LEN_0F2E_P_0 */ @@ -10083,26 +10004,6 @@ static const struct dis386 vex_len_table[][2] = { { VEX_W_TABLE (VEX_W_0F38DB_P_2) }, }, - /* VEX_LEN_0F38DC_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F38DC_P_2) }, - }, - - /* VEX_LEN_0F38DD_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F38DD_P_2) }, - }, - - /* VEX_LEN_0F38DE_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F38DE_P_2) }, - }, - - /* VEX_LEN_0F38DF_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F38DF_P_2) }, - }, - /* VEX_LEN_0F38F2_P_0 */ { { "andnS", { Gdq, VexGdq, Edq }, 0 }, @@ -10277,11 +10178,6 @@ static const struct dis386 vex_len_table[][2] = { { VEX_W_TABLE (VEX_W_0F3A41_P_2) }, }, - /* VEX_LEN_0F3A44_P_2 */ - { - { VEX_W_TABLE (VEX_W_0F3A44_P_2) }, - }, - /* VEX_LEN_0F3A46_P_2 */ { { Bad_Opcode }, @@ -10290,12 +10186,12 @@ static const struct dis386 vex_len_table[][2] = { /* VEX_LEN_0F3A60_P_2 */ { - { VEX_W_TABLE (VEX_W_0F3A60_P_2) }, + { "vpcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 }, }, /* VEX_LEN_0F3A61_P_2 */ { - { VEX_W_TABLE (VEX_W_0F3A61_P_2) }, + { "vpcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 }, }, /* VEX_LEN_0F3A62_P_2 */ @@ -10310,42 +10206,42 @@ static const struct dis386 vex_len_table[][2] = { /* VEX_LEN_0F3A6A_P_2 */ { - { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, + { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, }, /* VEX_LEN_0F3A6B_P_2 */ { - { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, + { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, }, /* VEX_LEN_0F3A6E_P_2 */ { - { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, + { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, }, /* VEX_LEN_0F3A6F_P_2 */ { - { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, + { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, }, /* VEX_LEN_0F3A7A_P_2 */ { - { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, + { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, }, /* VEX_LEN_0F3A7B_P_2 */ { - { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, + { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, }, /* VEX_LEN_0F3A7E_P_2 */ { - { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, + { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, }, /* VEX_LEN_0F3A7F_P_2 */ { - { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, + { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, }, /* VEX_LEN_0F3ADF_P_2 */ @@ -10360,42 +10256,42 @@ static const struct dis386 vex_len_table[][2] = { /* VEX_LEN_0FXOP_08_CC */ { - { "vpcomb", { XM, Vex128, EXx, Ib }, 0 }, + { "vpcomb", { XM, Vex128, EXx, VPCOM }, 0 }, }, /* VEX_LEN_0FXOP_08_CD */ { - { "vpcomw", { XM, Vex128, EXx, Ib }, 0 }, + { "vpcomw", { XM, Vex128, EXx, VPCOM }, 0 }, }, /* VEX_LEN_0FXOP_08_CE */ { - { "vpcomd", { XM, Vex128, EXx, Ib }, 0 }, + { "vpcomd", { XM, Vex128, EXx, VPCOM }, 0 }, }, /* VEX_LEN_0FXOP_08_CF */ { - { "vpcomq", { XM, Vex128, EXx, Ib }, 0 }, + { "vpcomq", { XM, Vex128, EXx, VPCOM }, 0 }, }, /* VEX_LEN_0FXOP_08_EC */ { - { "vpcomub", { XM, Vex128, EXx, Ib }, 0 }, + { "vpcomub", { XM, Vex128, EXx, VPCOM }, 0 }, }, /* VEX_LEN_0FXOP_08_ED */ { - { "vpcomuw", { XM, Vex128, EXx, Ib }, 0 }, + { "vpcomuw", { XM, Vex128, EXx, VPCOM }, 0 }, }, /* VEX_LEN_0FXOP_08_EE */ { - { "vpcomud", { XM, Vex128, EXx, Ib }, 0 }, + { "vpcomud", { XM, Vex128, EXx, VPCOM }, 0 }, }, /* VEX_LEN_0FXOP_08_EF */ { - { "vpcomuq", { XM, Vex128, EXx, Ib }, 0 }, + { "vpcomuq", { XM, Vex128, EXx, VPCOM }, 0 }, }, /* VEX_LEN_0FXOP_09_80 */ @@ -11463,27 +11359,15 @@ static const struct dis386 vex_w_table[][2] = { }, { /* VEX_W_0F3879_P_2 */ - { "vpbroadcastw", { XM, EXxmm_mw }, 0 }, - }, - { - /* VEX_W_0F38DB_P_2 */ - { "vaesimc", { XM, EXx }, 0 }, - }, - { - /* VEX_W_0F38DC_P_2 */ - { "vaesenc", { XM, Vex128, EXx }, 0 }, - }, - { - /* VEX_W_0F38DD_P_2 */ - { "vaesenclast", { XM, Vex128, EXx }, 0 }, + { "vpbroadcastw", { XM, EXxmm_mw }, 0 }, }, { - /* VEX_W_0F38DE_P_2 */ - { "vaesdec", { XM, Vex128, EXx }, 0 }, + /* VEX_W_0F38CF_P_2 */ + { "vgf2p8mulb", { XM, Vex, EXx }, 0 }, }, { - /* VEX_W_0F38DF_P_2 */ - { "vaesdeclast", { XM, Vex128, EXx }, 0 }, + /* VEX_W_0F38DB_P_2 */ + { "vaesimc", { XM, EXx }, 0 }, }, { /* VEX_W_0F3A00_P_2 */ @@ -11607,10 +11491,6 @@ static const struct dis386 vex_w_table[][2] = { /* VEX_W_0F3A42_P_2 */ { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 }, }, - { - /* VEX_W_0F3A44_P_2 */ - { "vpclmulqdq", { XM, Vex128, EXx, PCLMUL }, 0 }, - }, { /* VEX_W_0F3A46_P_2 */ { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 }, @@ -11637,14 +11517,6 @@ static const struct dis386 vex_w_table[][2] = { /* VEX_W_0F3A4C_P_2 */ { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 }, }, - { - /* VEX_W_0F3A60_P_2 */ - { "vpcmpestrm", { XM, EXx, Ib }, 0 }, - }, - { - /* VEX_W_0F3A61_P_2 */ - { "vpcmpestri", { XM, EXx, Ib }, 0 }, - }, { /* VEX_W_0F3A62_P_2 */ { "vpcmpistrm", { XM, EXx, Ib }, 0 }, @@ -11653,6 +11525,16 @@ static const struct dis386 vex_w_table[][2] = { /* VEX_W_0F3A63_P_2 */ { "vpcmpistri", { XM, EXx, Ib }, 0 }, }, + { + /* VEX_W_0F3ACE_P_2 */ + { Bad_Opcode }, + { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 }, + }, + { + /* VEX_W_0F3ACF_P_2 */ + { Bad_Opcode }, + { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, 0 }, + }, { /* VEX_W_0F3ADF_P_2 */ { "vaeskeygenassist", { XM, EXx, Ib }, 0 }, @@ -11707,7 +11589,7 @@ static const struct dis386 mod_table[][2] = { }, { /* MOD_0F01_REG_5 */ - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) }, { RM_TABLE (RM_0F01_REG_5) }, }, { @@ -11767,19 +11649,29 @@ static const struct dis386 mod_table[][2] = { }, { /* MOD_0F1A_PREFIX_0 */ - { "bndldx", { Gbnd, Ev_bnd }, 0 }, + { "bndldx", { Gbnd, Mv_bnd }, 0 }, { "nopQ", { Ev }, 0 }, }, { /* MOD_0F1B_PREFIX_0 */ - { "bndstx", { Ev_bnd, Gbnd }, 0 }, + { "bndstx", { Mv_bnd, Gbnd }, 0 }, { "nopQ", { Ev }, 0 }, }, { /* MOD_0F1B_PREFIX_1 */ - { "bndmk", { Gbnd, Ev_bnd }, 0 }, + { "bndmk", { Gbnd, Mv_bnd }, 0 }, { "nopQ", { Ev }, 0 }, }, + { + /* MOD_0F1C_PREFIX_0 */ + { REG_TABLE (REG_0F1C_MOD_0) }, + { "nopQ", { Ev }, 0 }, + }, + { + /* MOD_0F1E_PREFIX_1 */ + { "nopQ", { Ev }, 0 }, + { REG_TABLE (REG_0F1E_MOD_3) }, + }, { /* MOD_0F24 */ { Bad_Opcode }, @@ -11888,13 +11780,13 @@ static const struct dis386 mod_table[][2] = { }, { /* MOD_0FAE_REG_5 */ - { "xrstor", { FXSAVE }, 0 }, - { RM_TABLE (RM_0FAE_REG_5) }, + { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) }, + { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) }, }, { /* MOD_0FAE_REG_6 */ - { PREFIX_TABLE (PREFIX_0FAE_REG_6) }, - { RM_TABLE (RM_0FAE_REG_6) }, + { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_6) }, + { PREFIX_TABLE (PREFIX_MOD_1_0FAE_REG_6) }, }, { /* MOD_0FAE_REG_7 */ @@ -11956,6 +11848,22 @@ static const struct dis386 mod_table[][2] = { /* MOD_0F382A_PREFIX_2 */ { "movntdqa", { XM, Mx }, 0 }, }, + { + /* MOD_0F38F5_PREFIX_2 */ + { "wrussK", { M, Gdq }, PREFIX_OPCODE }, + }, + { + /* MOD_0F38F6_PREFIX_0 */ + { "wrssK", { M, Gdq }, PREFIX_OPCODE }, + }, + { + /* MOD_0F38F8_PREFIX_2 */ + { "movdir64b", { Gva, M }, PREFIX_OPCODE }, + }, + { + /* MOD_0F38F9_PREFIX_0 */ + { "movdiri", { Em, Gv }, PREFIX_OPCODE }, + }, { /* MOD_62_32BIT */ { "bound{S|}", { Gv, Ma }, 0 }, @@ -12421,6 +12329,7 @@ static const struct dis386 rm_table[][8] = { { "vmlaunch", { Skip_MODRM }, 0 }, { "vmresume", { Skip_MODRM }, 0 }, { "vmxoff", { Skip_MODRM }, 0 }, + { "pconfig", { Skip_MODRM }, 0 }, }, { /* RM_0F01_REG_1 */ @@ -12457,9 +12366,9 @@ static const struct dis386 rm_table[][8] = { }, { /* RM_0F01_REG_5 */ + { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) }, { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, + { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -12475,8 +12384,15 @@ static const struct dis386 rm_table[][8] = { { "clzero", { Skip_MODRM }, 0 }, }, { - /* RM_0FAE_REG_5 */ - { "lfence", { Skip_MODRM }, 0 }, + /* RM_0F1E_MOD_3_REG_7 */ + { "nopQ", { Ev }, 0 }, + { "nopQ", { Ev }, 0 }, + { "endbr64", { Skip_MODRM }, PREFIX_OPCODE }, + { "endbr32", { Skip_MODRM }, PREFIX_OPCODE }, + { "nopQ", { Ev }, 0 }, + { "nopQ", { Ev }, 0 }, + { "nopQ", { Ev }, 0 }, + { "nopQ", { Ev }, 0 }, }, { /* RM_0FAE_REG_6 */ @@ -12484,7 +12400,8 @@ static const struct dis386 rm_table[][8] = { }, { /* RM_0FAE_REG_7 */ - { PREFIX_TABLE (PREFIX_RM_0_0FAE_REG_7) }, + { "sfence", { Skip_MODRM }, 0 }, + }, }; @@ -12496,6 +12413,7 @@ static const struct dis386 rm_table[][8] = { #define XACQUIRE_PREFIX (0xf2 | 0x200) #define XRELEASE_PREFIX (0xf3 | 0x400) #define BND_PREFIX (0xf2 | 0x400) +#define NOTRACK_PREFIX (0x3e | 0x100) static int ckprefix (void) @@ -12714,6 +12632,8 @@ prefix_name (int pref, int sizeflag) return "xrelease"; case BND_PREFIX: return "bnd"; + case NOTRACK_PREFIX: + return "notrack"; default: return NULL; } @@ -12963,18 +12883,16 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) rex |= REX_W; vex.register_specifier = (~(*codep >> 3)) & 0xf; - if (address_mode != mode_64bit - && vex.register_specifier > 0x7) + if (address_mode != mode_64bit) { - dp = &bad_opcode; - return dp; + /* In 16/32-bit mode REX_B is silently ignored. */ + rex &= ~REX_B; } vex.length = (*codep & 0x4) ? 256 : 128; switch ((*codep & 0x3)) { case 0: - vex.prefix = 0; break; case 1: vex.prefix = DATA_PREFIX_OPCODE; @@ -13022,22 +12940,23 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) } codep++; vex.w = *codep & 0x80; - if (vex.w && address_mode == mode_64bit) - rex |= REX_W; - - vex.register_specifier = (~(*codep >> 3)) & 0xf; - if (address_mode != mode_64bit - && vex.register_specifier > 0x7) + if (address_mode == mode_64bit) { - dp = &bad_opcode; - return dp; + if (vex.w) + rex |= REX_W; } - + else + { + /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit + is ignored, other REX bits are 0 and the highest bit in + VEX.vvvv is also ignored (but we mustn't clear it here). */ + rex = 0; + } + vex.register_specifier = (~(*codep >> 3)) & 0xf; vex.length = (*codep & 0x4) ? 256 : 128; switch ((*codep & 0x3)) { case 0: - vex.prefix = 0; break; case 1: vex.prefix = DATA_PREFIX_OPCODE; @@ -13055,8 +12974,8 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) vindex = *codep++; dp = &vex_table[vex_table_index][vindex]; end_codep = codep; - /* There is no MODRM byte for VEX [82|77]. */ - if (vindex != 0x77 && vindex != 0x82) + /* There is no MODRM byte for VEX0F 77. */ + if (vex_table_index != VEX_0F || vindex != 0x77) { FETCH_DATA (info, codep + 1); modrm.mod = (*codep >> 6) & 3; @@ -13072,21 +12991,13 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) rex_ignored = rex; rex = (*codep & 0x80) ? 0 : REX_R; + /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in + VEX.vvvv is 1. */ vex.register_specifier = (~(*codep >> 3)) & 0xf; - if (address_mode != mode_64bit - && vex.register_specifier > 0x7) - { - dp = &bad_opcode; - return dp; - } - - vex.w = 0; - vex.length = (*codep & 0x4) ? 256 : 128; switch ((*codep & 0x3)) { case 0: - vex.prefix = 0; break; case 1: vex.prefix = DATA_PREFIX_OPCODE; @@ -13104,8 +13015,8 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) vindex = *codep++; dp = &vex_table[dp->op[1].bytemode][vindex]; end_codep = codep; - /* There is no MODRM byte for VEX [82|77]. */ - if (vindex != 0x77 && vindex != 0x82) + /* There is no MODRM byte for VEX 77. */ + if (vindex != 0x77) { FETCH_DATA (info, codep + 1); modrm.mod = (*codep >> 6) & 3; @@ -13153,14 +13064,6 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) rex |= REX_W; vex.register_specifier = (~(*codep >> 3)) & 0xf; - if (address_mode != mode_64bit) - { - /* In 16/32-bit mode silently ignore following bits. */ - rex &= ~REX_B; - vex.r = 1; - vex.v = 1; - vex.register_specifier &= 0x7; - } /* The U bit. */ if (!(*codep & 0x4)) @@ -13169,7 +13072,6 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) switch ((*codep & 0x3)) { case 0: - vex.prefix = 0; break; case 1: vex.prefix = DATA_PREFIX_OPCODE; @@ -13193,6 +13095,14 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) vex.mask_register_specifier = *codep & 0x7; vex.zeroing = *codep & 0x80; + if (address_mode != mode_64bit) + { + /* In 16/32-bit mode silently ignore following bits. */ + rex &= ~REX_B; + vex.r = 1; + vex.v = 1; + } + need_vex = 1; need_vex_reg = 1; codep++; @@ -13519,7 +13429,7 @@ print_insn (bfd_vma pc, disassemble_info *info) need_vex = 0; need_vex_reg = 0; vex_w_done = 0; - vex.evex = 0; + memset (&vex, 0, sizeof (vex)); if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) { @@ -13734,19 +13644,19 @@ static const char *float_mem[] = { "fNsaveIC", "fNstsw", /* de */ - "fiadd", - "fimul", - "ficom", - "ficomp", - "fisub", - "fisubr", - "fidiv", - "fidivr", + "fiadd{s|}", + "fimul{s|}", + "ficom{s|}", + "ficomp{s|}", + "fisub{s|}", + "fisubr{s|}", + "fidiv{s|}", + "fidivr{s|}", /* df */ - "fild", - "fisttp", - "fist", - "fistp", + "fild{s|}", + "fisttp{s|}", + "fist{s|}", + "fistp{s|}", "fbld", "fild{ll|}", "fbstp", @@ -13831,15 +13741,15 @@ static const unsigned char float_mem_mode[] = { #define ST { OP_ST, 0 } #define STi { OP_STi, 0 } -#define FGRPd9_2 NULL, { { NULL, 0 } }, 0 -#define FGRPd9_4 NULL, { { NULL, 1 } }, 0 -#define FGRPd9_5 NULL, { { NULL, 2 } }, 0 -#define FGRPd9_6 NULL, { { NULL, 3 } }, 0 -#define FGRPd9_7 NULL, { { NULL, 4 } }, 0 -#define FGRPda_5 NULL, { { NULL, 5 } }, 0 -#define FGRPdb_4 NULL, { { NULL, 6 } }, 0 -#define FGRPde_3 NULL, { { NULL, 7 } }, 0 -#define FGRPdf_4 NULL, { { NULL, 8 } }, 0 +#define FGRPd9_2 NULL, { { NULL, 1 } }, 0 +#define FGRPd9_4 NULL, { { NULL, 2 } }, 0 +#define FGRPd9_5 NULL, { { NULL, 3 } }, 0 +#define FGRPd9_6 NULL, { { NULL, 4 } }, 0 +#define FGRPd9_7 NULL, { { NULL, 5 } }, 0 +#define FGRPda_5 NULL, { { NULL, 6 } }, 0 +#define FGRPdb_4 NULL, { { NULL, 7 } }, 0 +#define FGRPde_3 NULL, { { NULL, 8 } }, 0 +#define FGRPdf_4 NULL, { { NULL, 9 } }, 0 static const struct dis386 float_reg[][8] = { /* d8 */ @@ -13892,10 +13802,10 @@ static const struct dis386 float_reg[][8] = { { "fmul", { STi, ST }, 0 }, { Bad_Opcode }, { Bad_Opcode }, - { "fsub!M", { STi, ST }, 0 }, - { "fsubM", { STi, ST }, 0 }, - { "fdiv!M", { STi, ST }, 0 }, - { "fdivM", { STi, ST }, 0 }, + { "fsub{!M|r}", { STi, ST }, 0 }, + { "fsub{M|}", { STi, ST }, 0 }, + { "fdiv{!M|r}", { STi, ST }, 0 }, + { "fdiv{M|}", { STi, ST }, 0 }, }, /* dd */ { @@ -13914,10 +13824,10 @@ static const struct dis386 float_reg[][8] = { { "fmulp", { STi, ST }, 0 }, { Bad_Opcode }, { FGRPde_3 }, - { "fsub!Mp", { STi, ST }, 0 }, - { "fsubMp", { STi, ST }, 0 }, - { "fdiv!Mp", { STi, ST }, 0 }, - { "fdivMp", { STi, ST }, 0 }, + { "fsub{!M|r}p", { STi, ST }, 0 }, + { "fsub{M|}p", { STi, ST }, 0 }, + { "fdiv{!M|r}p", { STi, ST }, 0 }, + { "fdiv{M|}p", { STi, ST }, 0 }, }, /* df */ { @@ -13933,48 +13843,53 @@ static const struct dis386 float_reg[][8] = { }; static char *fgrps[][8] = { - /* d9_2 0 */ + /* Bad opcode 0 */ + { + "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", + }, + + /* d9_2 1 */ { "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", }, - /* d9_4 1 */ + /* d9_4 2 */ { "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", }, - /* d9_5 2 */ + /* d9_5 3 */ { "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", }, - /* d9_6 3 */ + /* d9_6 4 */ { "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", }, - /* d9_7 4 */ + /* d9_7 5 */ { "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", }, - /* da_5 5 */ + /* da_5 6 */ { "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", }, - /* db_4 6 */ + /* db_4 7 */ { "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", }, - /* de_3 7 */ + /* de_3 8 */ { "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", }, - /* df_4 8 */ + /* df_4 9 */ { "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", }, @@ -14560,16 +14475,7 @@ case_S: break; case 'Y': if (l == 0 && len == 1) - { - if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) - break; - if (rex & REX_W) - { - USED_REX (REX_W); - *obufp++ = 'q'; - } - break; - } + abort (); else { if (l != 1 || len != 2 || last[0] != 'X') @@ -14841,7 +14747,6 @@ intel_operand_size (int bytemode, int sizeflag) case w_mode: case dw_mode: case dqw_mode: - case dqw_swap_mode: oappend ("WORD PTR "); break; case indir_v_mode: @@ -14920,6 +14825,8 @@ intel_operand_size (int bytemode, int sizeflag) case x_swap_mode: case evex_x_gscat_mode: case evex_x_nobcst_mode: + case b_scalar_mode: + case w_scalar_mode: if (need_vex) { switch (vex.length) @@ -15179,6 +15086,7 @@ intel_operand_size (int bytemode, int sizeflag) oappend ("WORD PTR "); break; case v_bnd_mode: + case v_bndmk_mode: default: break; } @@ -15196,8 +15104,8 @@ OP_E_register (int bytemode, int sizeflag) if ((sizeflag & SUFFIX_ALWAYS) && (bytemode == b_swap_mode - || bytemode == v_swap_mode - || bytemode == dqw_swap_mode)) + || bytemode == bnd_swap_mode + || bytemode == v_swap_mode)) swap_operand (); switch (bytemode) @@ -15226,6 +15134,12 @@ OP_E_register (int bytemode, int sizeflag) names = address_mode == mode_64bit ? names64 : names32; break; case bnd_mode: + case bnd_swap_mode: + if (reg > 0x3) + { + oappend ("(bad)"); + return; + } names = names_bnd; break; case indir_v_mode: @@ -15249,7 +15163,6 @@ OP_E_register (int bytemode, int sizeflag) case dqb_mode: case dqd_mode: case dqw_mode: - case dqw_swap_mode: USED_REX (REX_W); if (rex & REX_W) names = names64; @@ -15264,8 +15177,28 @@ OP_E_register (int bytemode, int sizeflag) used_prefixes |= (prefixes & PREFIX_DATA); } break; + case va_mode: + names = (address_mode == mode_64bit + ? names64 : names32); + if (!(prefixes & PREFIX_ADDR)) + names = (address_mode == mode_16bit + ? names16 : names); + else + { + /* Remove "addr16/addr32". */ + all_prefixes[last_addr_prefix] = 0; + names = (address_mode != mode_32bit + ? names32 : names16); + used_prefixes |= PREFIX_ADDR; + } + break; case mask_bd_mode: case mask_mode: + if (reg > 0x7) + { + oappend ("(bad)"); + return; + } names = names_mask; break; case 0: @@ -15300,7 +15233,6 @@ OP_E_memory (int bytemode, int sizeflag) { case dqw_mode: case dw_mode: - case dqw_swap_mode: shift = 1; break; case dqb_mode: @@ -15365,9 +15297,11 @@ OP_E_memory (int bytemode, int sizeflag) case d_scalar_swap_mode: shift = 2; break; + case w_scalar_mode: case xmm_mw_mode: shift = 1; break; + case b_scalar_mode: case xmm_mb_mode: shift = 0; break; @@ -15407,12 +15341,15 @@ OP_E_memory (int bytemode, int sizeflag) int havebase; int haveindex; int needindex; + int needaddr32; int base, rbase; int vindex = 0; int scale = 0; int addr32flag = !((sizeflag & AFLAG) || bytemode == v_bnd_mode - || bytemode == bnd_mode); + || bytemode == v_bndmk_mode + || bytemode == bnd_mode + || bytemode == bnd_swap_mode); const char **indexes64 = names64; const char **indexes32 = names32; @@ -15487,6 +15424,11 @@ OP_E_memory (int bytemode, int sizeflag) if (address_mode == mode_64bit && !havesib) riprel = 1; disp = get32s (); + if (riprel && bytemode == v_bndmk_mode) + { + oappend ("(bad)"); + return; + } } break; case 1: @@ -15502,12 +15444,27 @@ OP_E_memory (int bytemode, int sizeflag) break; } - /* In 32bit mode, we need index register to tell [offset] from - [eiz*1 + offset]. */ - needindex = (havesib - && !havebase - && !haveindex - && address_mode == mode_32bit); + needindex = 0; + needaddr32 = 0; + if (havesib + && !havebase + && !haveindex + && address_mode != mode_16bit) + { + if (address_mode == mode_64bit) + { + /* Display eiz instead of addr32. */ + needindex = addr32flag; + needaddr32 = 1; + } + else + { + /* In 32-bit mode, we need index register to tell [offset] + from [eiz*1 + offset]. */ + needindex = 1; + } + } + havedisp = (havebase || needindex || (havesib && (haveindex || scale != 0))); @@ -15523,13 +15480,15 @@ OP_E_memory (int bytemode, int sizeflag) if (riprel) { set_op (disp, 1); - oappend (sizeflag & AFLAG ? "(%rip)" : "(%eip)"); + oappend (!addr32flag ? "(%rip)" : "(%eip)"); } } - if ((havebase || haveindex || riprel) + if ((havebase || haveindex || needaddr32 || riprel) && (bytemode != v_bnd_mode) - && (bytemode != bnd_mode)) + && (bytemode != v_bndmk_mode) + && (bytemode != bnd_mode) + && (bytemode != bnd_swap_mode)) used_prefixes |= PREFIX_ADDR; if (havedisp || (intel_syntax && riprel)) @@ -15538,7 +15497,7 @@ OP_E_memory (int bytemode, int sizeflag) if (intel_syntax && riprel) { set_op (disp, 1); - oappend (sizeflag & AFLAG ? "rip" : "eip"); + oappend (!addr32flag ? "rip" : "eip"); } *obufp = '\0'; if (havebase) @@ -15629,6 +15588,8 @@ OP_E_memory (int bytemode, int sizeflag) disp = *codep++; if ((disp & 0x80) != 0) disp -= 0x100; + if (vex.evex && shift > 0) + disp <<= shift; break; case 2: disp = get16 (); @@ -15743,6 +15704,7 @@ static void OP_G (int bytemode, int sizeflag) { int add = 0; + const char **names; USED_REX (REX_R); if (rex & REX_R) add += 8; @@ -15767,6 +15729,11 @@ OP_G (int bytemode, int sizeflag) oappend (names64[modrm.reg + add]); break; case bnd_mode: + if (modrm.reg > 0x3) + { + oappend ("(bad)"); + return; + } oappend (names_bnd[modrm.reg]); break; case v_mode: @@ -15774,7 +15741,6 @@ OP_G (int bytemode, int sizeflag) case dqb_mode: case dqd_mode: case dqw_mode: - case dqw_swap_mode: USED_REX (REX_W); if (rex & REX_W) oappend (names64[modrm.reg + add]); @@ -15787,6 +15753,24 @@ OP_G (int bytemode, int sizeflag) used_prefixes |= (prefixes & PREFIX_DATA); } break; + case va_mode: + names = (address_mode == mode_64bit + ? names64 : names32); + if (!(prefixes & PREFIX_ADDR)) + { + if (address_mode == mode_16bit) + names = names16; + } + else + { + /* Remove "addr16/addr32". */ + all_prefixes[last_addr_prefix] = 0; + names = (address_mode != mode_32bit + ? names32 : names16); + used_prefixes |= PREFIX_ADDR; + } + oappend (names[modrm.reg + add]); + break; case m_mode: if (address_mode == mode_64bit) oappend (names64[modrm.reg + add]); @@ -15795,6 +15779,11 @@ OP_G (int bytemode, int sizeflag) break; case mask_bd_mode: case mask_mode: + if ((modrm.reg + add) > 0x7) + { + oappend ("(bad)"); + return; + } oappend (names_mask[modrm.reg + add]); break; default: @@ -16624,7 +16613,6 @@ OP_EX (int bytemode, int sizeflag) if ((sizeflag & SUFFIX_ALWAYS) && (bytemode == x_swap_mode || bytemode == d_swap_mode - || bytemode == dqw_swap_mode || bytemode == d_scalar_swap_mode || bytemode == q_swap_mode || bytemode == q_scalar_swap_mode)) @@ -16994,6 +16982,23 @@ BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) all_prefixes[last_repnz_prefix] = BND_PREFIX; } +/* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as + "notrack". */ + +static void +NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED, + int sizeflag ATTRIBUTE_UNUSED) +{ + if (active_seg_prefix == PREFIX_DS + && (address_mode != mode_64bit || last_data_prefix < 0)) + { + /* NOTRACK prefix is only valid on indirect branch instructions. + NB: DATA prefix is unsupported for Intel64. */ + active_seg_prefix = 0; + all_prefixes[last_seg_prefix] = NOTRACK_PREFIX; + } +} + /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as "xacquire"/"xrelease" for memory operand if there is a LOCK prefix. */ @@ -17178,6 +17183,27 @@ FXSAVE_Fixup (int bytemode, int sizeflag) OP_M (bytemode, sizeflag); } +static void +PCMPESTR_Fixup (int bytemode, int sizeflag) +{ + /* Add proper suffix to "{,v}pcmpestr{i,m}". */ + if (!intel_syntax) + { + char *p = mnemonicendp; + + USED_REX (REX_W); + if (rex & REX_W) + *p++ = 'q'; + else if (sizeflag & SUFFIX_ALWAYS) + *p++ = 'l'; + + *p = '\0'; + mnemonicendp = p; + } + + OP_EX (bytemode, sizeflag); +} + /* Display the destination register operand for instructions with VEX. */ @@ -17194,11 +17220,10 @@ OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) return; reg = vex.register_specifier; - if (vex.evex) - { - if (!vex.v) - reg += 16; - } + if (address_mode != mode_64bit) + reg &= 7; + else if (vex.evex && !vex.v) + reg += 16; if (bytemode == vex_scalar_mode) { @@ -17218,13 +17243,18 @@ OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) names = names_xmm; break; case dq_mode: - if (vex.w) + if (rex & REX_W) names = names64; else names = names32; break; case mask_bd_mode: case mask_mode: + if (reg > 0x7) + { + oappend ("(bad)"); + return; + } names = names_mask; break; default: @@ -17245,10 +17275,16 @@ OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) break; case mask_bd_mode: case mask_mode: + if (reg > 0x7) + { + oappend ("(bad)"); + return; + } names = names_mask; break; default: - abort (); + /* See PR binutils/20893 for a reproducer. */ + oappend ("(bad)"); return; } break; @@ -17372,8 +17408,8 @@ OP_EX_VexReg (int bytemode, int sizeflag, int reg) if (rex & REX_B) reg += 8; } - else if (reg > 7 && address_mode != mode_64bit) - BadOp (); + if (address_mode != mode_64bit) + reg &= 7; } switch (vex.length) @@ -17465,7 +17501,13 @@ OP_Vex_2src_1 (int bytemode, int sizeflag) } if (vex.w) - oappend (names_xmm[vex.register_specifier]); + { + unsigned int reg = vex.register_specifier; + + if (address_mode != mode_64bit) + reg &= 7; + oappend (names_xmm[reg]); + } else OP_Vex_2src (bytemode, sizeflag); } @@ -17476,7 +17518,13 @@ OP_Vex_2src_2 (int bytemode, int sizeflag) if (vex.w) OP_Vex_2src (bytemode, sizeflag); else - oappend (names_xmm[vex.register_specifier]); + { + unsigned int reg = vex.register_specifier; + + if (address_mode != mode_64bit) + reg &= 7; + oappend (names_xmm[reg]); + } } static void @@ -17486,8 +17534,6 @@ OP_EX_VexW (int bytemode, int sizeflag) if (!vex_w_done) { - vex_w_done = 1; - /* Skip mod/rm byte. */ MODRM_CHECK; codep++; @@ -17502,16 +17548,10 @@ OP_EX_VexW (int bytemode, int sizeflag) } OP_EX_VexReg (bytemode, sizeflag, reg); -} -static void -VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED, - int sizeflag ATTRIBUTE_UNUSED) -{ - /* Skip the immediate byte and check for invalid bits. */ - FETCH_DATA (the_info, codep + 1); - if (*codep++ & 0xf) - BadOp (); + if (vex_w_done) + codep++; + vex_w_done = 1; } static void @@ -17526,12 +17566,9 @@ OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) if (bytemode != x_mode) abort (); - if (reg & 0xf) - BadOp (); - reg >>= 4; - if (reg > 7 && address_mode != mode_64bit) - BadOp (); + if (address_mode != mode_64bit) + reg &= 7; switch (vex.length) { @@ -17706,6 +17743,58 @@ VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, } } +static const struct op xop_cmp_op[] = +{ + { STRING_COMMA_LEN ("lt") }, + { STRING_COMMA_LEN ("le") }, + { STRING_COMMA_LEN ("gt") }, + { STRING_COMMA_LEN ("ge") }, + { STRING_COMMA_LEN ("eq") }, + { STRING_COMMA_LEN ("neq") }, + { STRING_COMMA_LEN ("false") }, + { STRING_COMMA_LEN ("true") } +}; + +static void +VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED, + int sizeflag ATTRIBUTE_UNUSED) +{ + unsigned int cmp_type; + + FETCH_DATA (the_info, codep + 1); + cmp_type = *codep++ & 0xff; + if (cmp_type < ARRAY_SIZE (xop_cmp_op)) + { + char suffix[3]; + char *p = mnemonicendp - 2; + + /* vpcom* can have both one- and two-lettered suffix. */ + if (p[0] == 'm') + { + p++; + suffix[0] = p[0]; + suffix[1] = '\0'; + } + else + { + suffix[0] = p[0]; + suffix[1] = p[1]; + suffix[2] = '\0'; + } + + sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix); + mnemonicendp += xop_cmp_op[cmp_type].len; + } + else + { + /* We have a reserved extension byte. Output it directly. */ + scratchbuf[0] = '$'; + print_operand_value (scratchbuf + 1, 1, cmp_type); + oappend_maybe_intel (scratchbuf); + scratchbuf[0] = '\0'; + } +} + static const struct op pclmul_op[] = { { STRING_COMMA_LEN ("lql") }, @@ -17802,7 +17891,7 @@ OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) MODRM_CHECK; codep++; - if (vex.w) + if (rex & REX_W) names = names64; else names = names32; @@ -17819,13 +17908,16 @@ static void OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) { const char **names; + unsigned int reg = vex.register_specifier; - if (vex.w) + if (rex & REX_W) names = names64; else names = names32; - oappend (names[vex.register_specifier]); + if (address_mode != mode_64bit) + reg &= 7; + oappend (names[reg]); } static void