X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Fi386-dis.c;h=98950e20f070dbf5e6eb95024f4363e1beae874b;hb=f67c0c9171508672167b6868c67211571421a1c6;hp=637fce398dd9d95f0a66ed84d5f929b766b81999;hpb=8cfcb7659cb844dff00efbbb644c15b650fb7e8b;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 637fce398d..98950e20f0 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -1,5 +1,5 @@ /* Print i386 instructions for GDB, the GNU debugger. - Copyright (C) 1988-2017 Free Software Foundation, Inc. + Copyright (C) 1988-2018 Free Software Foundation, Inc. This file is part of the GNU opcodes library. @@ -95,10 +95,10 @@ static void OP_XMM_VexW (int, int); static void OP_Rounding (int, int); static void OP_REG_VexI4 (int, int); static void PCLMUL_Fixup (int, int); -static void VEXI4_Fixup (int, int); static void VZERO_Fixup (int, int); static void VCMP_Fixup (int, int); static void VPCMP_Fixup (int, int); +static void VPCOM_Fixup (int, int); static void OP_0f07 (int, int); static void OP_Monitor (int, int); static void OP_Mwait (int, int); @@ -248,7 +248,9 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define Eb { OP_E, b_mode } #define Ebnd { OP_E, bnd_mode } #define EbS { OP_E, b_swap_mode } +#define EbndS { OP_E, bnd_swap_mode } #define Ev { OP_E, v_mode } +#define Eva { OP_E, va_mode } #define Ev_bnd { OP_E, v_bnd_mode } #define EvS { OP_E, v_swap_mode } #define Ed { OP_E, d_mode } @@ -422,7 +424,6 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define Vex128 { OP_VEX, vex128_mode } #define Vex256 { OP_VEX, vex256_mode } #define VexGdq { OP_VEX, dq_mode } -#define VexI4 { VEXI4_Fixup, 0} #define EXdVex { OP_EX_Vex, d_mode } #define EXdVexS { OP_EX_Vex, d_swap_mode } #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode } @@ -441,6 +442,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define VZERO { VZERO_Fixup, 0 } #define VCMP { VCMP_Fixup, 0 } #define VPCMP { VPCMP_Fixup, 0 } +#define VPCOM { VPCOM_Fixup, 0 } #define EXxEVexR { OP_Rounding, evex_rounding_mode } #define EXxEVexS { OP_Rounding, evex_sae_mode } @@ -498,6 +500,8 @@ enum v_mode, /* operand size depends on prefixes with operand swapped */ v_swap_mode, + /* operand size depends on address prefix */ + va_mode, /* word operand */ w_mode, /* double word operand */ @@ -560,7 +564,10 @@ enum dq_mode, /* registers like dq_mode, memory like w_mode. */ dqw_mode, + /* bounds operand */ bnd_mode, + /* bounds operand with operand swapped */ + bnd_swap_mode, /* 4- or 6-byte pointer operand */ f_mode, const_1_mode, @@ -731,6 +738,7 @@ enum REG_0F01, REG_0F0D, REG_0F18, + REG_0F1C_MOD_0, REG_0F1E_MOD_3, REG_0F71, REG_0F72, @@ -785,6 +793,7 @@ enum MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0, MOD_0F1B_PREFIX_1, + MOD_0F1C_PREFIX_0, MOD_0F1E_PREFIX_1, MOD_0F24, MOD_0F26, @@ -956,12 +965,14 @@ enum PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_3_0F01_REG_5_RM_0, PREFIX_MOD_3_0F01_REG_5_RM_2, + PREFIX_0F09, PREFIX_0F10, PREFIX_0F11, PREFIX_0F12, PREFIX_0F16, PREFIX_0F1A, PREFIX_0F1B, + PREFIX_0F1C, PREFIX_0F1E, PREFIX_0F2A, PREFIX_0F2B, @@ -1003,7 +1014,8 @@ enum PREFIX_MOD_3_0FAE_REG_4, PREFIX_MOD_0_0FAE_REG_5, PREFIX_MOD_3_0FAE_REG_5, - PREFIX_0FAE_REG_6, + PREFIX_MOD_0_0FAE_REG_6, + PREFIX_MOD_1_0FAE_REG_6, PREFIX_0FAE_REG_7, PREFIX_0FB8, PREFIX_0FBC, @@ -1576,6 +1588,7 @@ enum PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853, + PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859, @@ -1607,6 +1620,7 @@ enum PREFIX_EVEX_0F388A, PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, + PREFIX_EVEX_0F388F, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892, @@ -2415,6 +2429,7 @@ enum EVEX_W_0F3839_P_1, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, + EVEX_W_0F3854_P_2, EVEX_W_0F3855_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2, @@ -2528,8 +2543,7 @@ struct dis386 { prefix and behave as 'S' otherwise 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) 'X' => print 's', 'd' depending on data16 prefix (for XMM) - 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and - suffix_always is true. + 'Y' unused. 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise '!' => change condition from true to false or from false to true. '%' => add 1 upper case letter to the macro. @@ -2866,7 +2880,7 @@ static const struct dis386 dis386_twobyte[] = { { "sysret%LP", { XX }, 0 }, /* 08 */ { "invd", { XX }, 0 }, - { "wbinvd", { XX }, 0 }, + { PREFIX_TABLE (PREFIX_0F09) }, { Bad_Opcode }, { "ud2", { XX }, 0 }, { Bad_Opcode }, @@ -2887,7 +2901,7 @@ static const struct dis386 dis386_twobyte[] = { { "nopQ", { Ev }, 0 }, { PREFIX_TABLE (PREFIX_0F1A) }, { PREFIX_TABLE (PREFIX_0F1B) }, - { "nopQ", { Ev }, 0 }, + { PREFIX_TABLE (PREFIX_0F1C) }, { "nopQ", { Ev }, 0 }, { PREFIX_TABLE (PREFIX_0F1E) }, { "nopQ", { Ev }, 0 }, @@ -3064,7 +3078,7 @@ static const struct dis386 dis386_twobyte[] = { { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */ /* b8 */ { PREFIX_TABLE (PREFIX_0FB8) }, - { "ud1", { XX }, 0 }, + { "ud1S", { Gv, Ev }, 0 }, { REG_TABLE (REG_0FBA) }, { "btcS", { Evh1, Gv }, 0 }, { PREFIX_TABLE (PREFIX_0FBC) }, @@ -3142,7 +3156,7 @@ static const struct dis386 dis386_twobyte[] = { { "paddb", { MX, EM }, PREFIX_OPCODE }, { "paddw", { MX, EM }, PREFIX_OPCODE }, { "paddd", { MX, EM }, PREFIX_OPCODE }, - { Bad_Opcode }, + { "ud0S", { Gv, Ev }, 0 }, }; static const unsigned char onebyte_has_modrm[256] = { @@ -3182,11 +3196,11 @@ static const unsigned char twobyte_has_modrm[256] = { /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ - /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */ + /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */ /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ - /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */ + /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */ /* ------------------------------- */ /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ }; @@ -3639,6 +3653,17 @@ static const struct dis386 reg_table[][8] = { { MOD_TABLE (MOD_0F18_REG_6) }, { MOD_TABLE (MOD_0F18_REG_7) }, }, + /* REG_0F1C_MOD_0 */ + { + { "cldemote", { Mb }, 0 }, + { "nopQ", { Ev }, 0 }, + { "nopQ", { Ev }, 0 }, + { "nopQ", { Ev }, 0 }, + { "nopQ", { Ev }, 0 }, + { "nopQ", { Ev }, 0 }, + { "nopQ", { Ev }, 0 }, + { "nopQ", { Ev }, 0 }, + }, /* REG_0F1E_MOD_3 */ { { "nopQ", { Ev }, 0 }, @@ -3837,6 +3862,12 @@ static const struct dis386 prefix_table[][4] = { { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE }, }, + /* PREFIX_0F09 */ + { + { "wbinvd", { XX }, 0 }, + { "wbnoinvd", { XX }, 0 }, + }, + /* PREFIX_0F10 */ { { "movups", { XM, EXx }, PREFIX_OPCODE }, @@ -3880,10 +3911,18 @@ static const struct dis386 prefix_table[][4] = { { { MOD_TABLE (MOD_0F1B_PREFIX_0) }, { MOD_TABLE (MOD_0F1B_PREFIX_1) }, - { "bndmov", { Ebnd, Gbnd }, 0 }, + { "bndmov", { EbndS, Gbnd }, 0 }, { "bndcn", { Gbnd, Ev_bnd }, 0 }, }, + /* PREFIX_0F1C */ + { + { MOD_TABLE (MOD_0F1C_PREFIX_0) }, + { "nopQ", { Ev }, PREFIX_OPCODE }, + { "nopQ", { Ev }, PREFIX_OPCODE }, + { "nopQ", { Ev }, PREFIX_OPCODE }, + }, + /* PREFIX_0F1E */ { { "nopQ", { Ev }, PREFIX_OPCODE }, @@ -3911,17 +3950,17 @@ static const struct dis386 prefix_table[][4] = { /* PREFIX_0F2C */ { { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE }, - { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE }, + { "cvttss2si", { Gv, EXd }, PREFIX_OPCODE }, { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE }, - { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE }, + { "cvttsd2si", { Gv, EXq }, PREFIX_OPCODE }, }, /* PREFIX_0F2D */ { { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE }, - { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE }, + { "cvtss2si", { Gv, EXd }, PREFIX_OPCODE }, { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE }, - { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE }, + { "cvtsd2si", { Gv, EXq }, PREFIX_OPCODE }, }, /* PREFIX_0F2E */ @@ -4178,13 +4217,21 @@ static const struct dis386 prefix_table[][4] = { { "incsspK", { Rdq }, PREFIX_OPCODE }, }, - /* PREFIX_0FAE_REG_6 */ + /* PREFIX_MOD_0_0FAE_REG_6 */ { { "xsaveopt", { FXSAVE }, PREFIX_OPCODE }, { "clrssbsy", { Mq }, PREFIX_OPCODE }, { "clwb", { Mb }, PREFIX_OPCODE }, }, + /* PREFIX_MOD_1_0FAE_REG_6 */ + { + { RM_TABLE (RM_0FAE_REG_6) }, + { "umonitor", { Eva }, PREFIX_OPCODE }, + { "tpause", { Edq }, PREFIX_OPCODE }, + { "umwait", { Edq }, PREFIX_OPCODE }, + }, + /* PREFIX_0FAE_REG_7 */ { { "clflush", { Mb }, 0 }, @@ -6743,28 +6790,28 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, }, /* PREFIX_VEX_0F3A5D */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, }, /* PREFIX_VEX_0F3A5E */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, }, /* PREFIX_VEX_0F3A5F */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, }, /* PREFIX_VEX_0F3A60 */ @@ -6800,14 +6847,14 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, }, /* PREFIX_VEX_0F3A69 */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, }, /* PREFIX_VEX_0F3A6A */ @@ -6828,14 +6875,14 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, }, /* PREFIX_VEX_0F3A6D */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, }, /* PREFIX_VEX_0F3A6E */ @@ -6856,14 +6903,14 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, }, /* PREFIX_VEX_0F3A79 */ { { Bad_Opcode }, { Bad_Opcode }, - { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, }, /* PREFIX_VEX_0F3A7A */ @@ -6884,7 +6931,7 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, { Bad_Opcode }, }, @@ -6892,7 +6939,7 @@ static const struct dis386 prefix_table[][4] = { { { Bad_Opcode }, { Bad_Opcode }, - { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, }, /* PREFIX_VEX_0F3A7E */ @@ -7852,9 +7899,9 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, - { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, - { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, + { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, + { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, /* 88 */ { Bad_Opcode }, { Bad_Opcode }, @@ -7862,17 +7909,17 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, - { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, + { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, /* 90 */ { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, - { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, - { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, + { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, + { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, /* 98 */ { Bad_Opcode }, { Bad_Opcode }, @@ -7880,16 +7927,16 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, - { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, + { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, /* a0 */ { Bad_Opcode }, { Bad_Opcode }, - { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, - { "vpperm", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, + { "vpperm", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, { Bad_Opcode }, { Bad_Opcode }, - { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, { Bad_Opcode }, /* a8 */ { Bad_Opcode }, @@ -7907,7 +7954,7 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW, VexI4 }, 0 }, + { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, { Bad_Opcode }, /* b8 */ { Bad_Opcode }, @@ -9533,26 +9580,26 @@ static const struct dis386 vex_len_table[][2] = { /* VEX_LEN_0F2C_P_1 */ { - { "vcvttss2siY", { Gv, EXdScalar }, 0 }, - { "vcvttss2siY", { Gv, EXdScalar }, 0 }, + { "vcvttss2si", { Gv, EXdScalar }, 0 }, + { "vcvttss2si", { Gv, EXdScalar }, 0 }, }, /* VEX_LEN_0F2C_P_3 */ { - { "vcvttsd2siY", { Gv, EXqScalar }, 0 }, - { "vcvttsd2siY", { Gv, EXqScalar }, 0 }, + { "vcvttsd2si", { Gv, EXqScalar }, 0 }, + { "vcvttsd2si", { Gv, EXqScalar }, 0 }, }, /* VEX_LEN_0F2D_P_1 */ { - { "vcvtss2siY", { Gv, EXdScalar }, 0 }, - { "vcvtss2siY", { Gv, EXdScalar }, 0 }, + { "vcvtss2si", { Gv, EXdScalar }, 0 }, + { "vcvtss2si", { Gv, EXdScalar }, 0 }, }, /* VEX_LEN_0F2D_P_3 */ { - { "vcvtsd2siY", { Gv, EXqScalar }, 0 }, - { "vcvtsd2siY", { Gv, EXqScalar }, 0 }, + { "vcvtsd2si", { Gv, EXqScalar }, 0 }, + { "vcvtsd2si", { Gv, EXqScalar }, 0 }, }, /* VEX_LEN_0F2E_P_0 */ @@ -10139,42 +10186,42 @@ static const struct dis386 vex_len_table[][2] = { /* VEX_LEN_0F3A6A_P_2 */ { - { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, + { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, }, /* VEX_LEN_0F3A6B_P_2 */ { - { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, + { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, }, /* VEX_LEN_0F3A6E_P_2 */ { - { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, + { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, }, /* VEX_LEN_0F3A6F_P_2 */ { - { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, + { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, }, /* VEX_LEN_0F3A7A_P_2 */ { - { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, + { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, }, /* VEX_LEN_0F3A7B_P_2 */ { - { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, + { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, }, /* VEX_LEN_0F3A7E_P_2 */ { - { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW, VexI4 }, 0 }, + { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, }, /* VEX_LEN_0F3A7F_P_2 */ { - { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW, VexI4 }, 0 }, + { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, }, /* VEX_LEN_0F3ADF_P_2 */ @@ -10189,42 +10236,42 @@ static const struct dis386 vex_len_table[][2] = { /* VEX_LEN_0FXOP_08_CC */ { - { "vpcomb", { XM, Vex128, EXx, Ib }, 0 }, + { "vpcomb", { XM, Vex128, EXx, VPCOM }, 0 }, }, /* VEX_LEN_0FXOP_08_CD */ { - { "vpcomw", { XM, Vex128, EXx, Ib }, 0 }, + { "vpcomw", { XM, Vex128, EXx, VPCOM }, 0 }, }, /* VEX_LEN_0FXOP_08_CE */ { - { "vpcomd", { XM, Vex128, EXx, Ib }, 0 }, + { "vpcomd", { XM, Vex128, EXx, VPCOM }, 0 }, }, /* VEX_LEN_0FXOP_08_CF */ { - { "vpcomq", { XM, Vex128, EXx, Ib }, 0 }, + { "vpcomq", { XM, Vex128, EXx, VPCOM }, 0 }, }, /* VEX_LEN_0FXOP_08_EC */ { - { "vpcomub", { XM, Vex128, EXx, Ib }, 0 }, + { "vpcomub", { XM, Vex128, EXx, VPCOM }, 0 }, }, /* VEX_LEN_0FXOP_08_ED */ { - { "vpcomuw", { XM, Vex128, EXx, Ib }, 0 }, + { "vpcomuw", { XM, Vex128, EXx, VPCOM }, 0 }, }, /* VEX_LEN_0FXOP_08_EE */ { - { "vpcomud", { XM, Vex128, EXx, Ib }, 0 }, + { "vpcomud", { XM, Vex128, EXx, VPCOM }, 0 }, }, /* VEX_LEN_0FXOP_08_EF */ { - { "vpcomuq", { XM, Vex128, EXx, Ib }, 0 }, + { "vpcomuq", { XM, Vex128, EXx, VPCOM }, 0 }, }, /* VEX_LEN_0FXOP_09_80 */ @@ -11595,6 +11642,11 @@ static const struct dis386 mod_table[][2] = { { "bndmk", { Gbnd, Ev_bnd }, 0 }, { "nopQ", { Ev }, 0 }, }, + { + /* MOD_0F1C_PREFIX_0 */ + { REG_TABLE (REG_0F1C_MOD_0) }, + { "nopQ", { Ev }, 0 }, + }, { /* MOD_0F1E_PREFIX_1 */ { "nopQ", { Ev }, 0 }, @@ -11713,8 +11765,8 @@ static const struct dis386 mod_table[][2] = { }, { /* MOD_0FAE_REG_6 */ - { PREFIX_TABLE (PREFIX_0FAE_REG_6) }, - { RM_TABLE (RM_0FAE_REG_6) }, + { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_6) }, + { PREFIX_TABLE (PREFIX_MOD_1_0FAE_REG_6) }, }, { /* MOD_0FAE_REG_7 */ @@ -12249,6 +12301,7 @@ static const struct dis386 rm_table[][8] = { { "vmlaunch", { Skip_MODRM }, 0 }, { "vmresume", { Skip_MODRM }, 0 }, { "vmxoff", { Skip_MODRM }, 0 }, + { "pconfig", { Skip_MODRM }, 0 }, }, { /* RM_0F01_REG_1 */ @@ -12806,18 +12859,12 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) { /* In 16/32-bit mode REX_B is silently ignored. */ rex &= ~REX_B; - if (vex.register_specifier > 0x7) - { - dp = &bad_opcode; - return dp; - } } vex.length = (*codep & 0x4) ? 256 : 128; switch ((*codep & 0x3)) { case 0: - vex.prefix = 0; break; case 1: vex.prefix = DATA_PREFIX_OPCODE; @@ -12869,21 +12916,19 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) { if (vex.w) rex |= REX_W; - vex.register_specifier = (~(*codep >> 3)) & 0xf; } else { /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit is ignored, other REX bits are 0 and the highest bit in - VEX.vvvv is also ignored. */ + VEX.vvvv is also ignored (but we mustn't clear it here). */ rex = 0; - vex.register_specifier = (~(*codep >> 3)) & 0x7; } + vex.register_specifier = (~(*codep >> 3)) & 0xf; vex.length = (*codep & 0x4) ? 256 : 128; switch ((*codep & 0x3)) { case 0: - vex.prefix = 0; break; case 1: vex.prefix = DATA_PREFIX_OPCODE; @@ -12921,12 +12966,10 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in VEX.vvvv is 1. */ vex.register_specifier = (~(*codep >> 3)) & 0xf; - vex.w = 0; vex.length = (*codep & 0x4) ? 256 : 128; switch ((*codep & 0x3)) { case 0: - vex.prefix = 0; break; case 1: vex.prefix = DATA_PREFIX_OPCODE; @@ -12993,14 +13036,6 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) rex |= REX_W; vex.register_specifier = (~(*codep >> 3)) & 0xf; - if (address_mode != mode_64bit) - { - /* In 16/32-bit mode silently ignore following bits. */ - rex &= ~REX_B; - vex.r = 1; - vex.v = 1; - vex.register_specifier &= 0x7; - } /* The U bit. */ if (!(*codep & 0x4)) @@ -13009,7 +13044,6 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) switch ((*codep & 0x3)) { case 0: - vex.prefix = 0; break; case 1: vex.prefix = DATA_PREFIX_OPCODE; @@ -13033,6 +13067,14 @@ get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) vex.mask_register_specifier = *codep & 0x7; vex.zeroing = *codep & 0x80; + if (address_mode != mode_64bit) + { + /* In 16/32-bit mode silently ignore following bits. */ + rex &= ~REX_B; + vex.r = 1; + vex.v = 1; + } + need_vex = 1; need_vex_reg = 1; codep++; @@ -13359,7 +13401,7 @@ print_insn (bfd_vma pc, disassemble_info *info) need_vex = 0; need_vex_reg = 0; vex_w_done = 0; - vex.evex = 0; + memset (&vex, 0, sizeof (vex)); if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) { @@ -13574,19 +13616,19 @@ static const char *float_mem[] = { "fNsaveIC", "fNstsw", /* de */ - "fiadd", - "fimul", - "ficom", - "ficomp", - "fisub", - "fisubr", - "fidiv", - "fidivr", + "fiadd{s|}", + "fimul{s|}", + "ficom{s|}", + "ficomp{s|}", + "fisub{s|}", + "fisubr{s|}", + "fidiv{s|}", + "fidivr{s|}", /* df */ - "fild", - "fisttp", - "fist", - "fistp", + "fild{s|}", + "fisttp{s|}", + "fist{s|}", + "fistp{s|}", "fbld", "fild{ll|}", "fbstp", @@ -13732,10 +13774,10 @@ static const struct dis386 float_reg[][8] = { { "fmul", { STi, ST }, 0 }, { Bad_Opcode }, { Bad_Opcode }, - { "fsub!M", { STi, ST }, 0 }, - { "fsubM", { STi, ST }, 0 }, - { "fdiv!M", { STi, ST }, 0 }, - { "fdivM", { STi, ST }, 0 }, + { "fsub{!M|r}", { STi, ST }, 0 }, + { "fsub{M|}", { STi, ST }, 0 }, + { "fdiv{!M|r}", { STi, ST }, 0 }, + { "fdiv{M|}", { STi, ST }, 0 }, }, /* dd */ { @@ -13754,10 +13796,10 @@ static const struct dis386 float_reg[][8] = { { "fmulp", { STi, ST }, 0 }, { Bad_Opcode }, { FGRPde_3 }, - { "fsub!Mp", { STi, ST }, 0 }, - { "fsubMp", { STi, ST }, 0 }, - { "fdiv!Mp", { STi, ST }, 0 }, - { "fdivMp", { STi, ST }, 0 }, + { "fsub{!M|r}p", { STi, ST }, 0 }, + { "fsub{M|}p", { STi, ST }, 0 }, + { "fdiv{!M|r}p", { STi, ST }, 0 }, + { "fdiv{M|}p", { STi, ST }, 0 }, }, /* df */ { @@ -14405,16 +14447,7 @@ case_S: break; case 'Y': if (l == 0 && len == 1) - { - if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) - break; - if (rex & REX_W) - { - USED_REX (REX_W); - *obufp++ = 'q'; - } - break; - } + abort (); else { if (l != 1 || len != 2 || last[0] != 'X') @@ -15042,6 +15075,7 @@ OP_E_register (int bytemode, int sizeflag) if ((sizeflag & SUFFIX_ALWAYS) && (bytemode == b_swap_mode + || bytemode == bnd_swap_mode || bytemode == v_swap_mode)) swap_operand (); @@ -15071,6 +15105,7 @@ OP_E_register (int bytemode, int sizeflag) names = address_mode == mode_64bit ? names64 : names32; break; case bnd_mode: + case bnd_swap_mode: if (reg > 0x3) { oappend ("(bad)"); @@ -15113,6 +15148,21 @@ OP_E_register (int bytemode, int sizeflag) used_prefixes |= (prefixes & PREFIX_DATA); } break; + case va_mode: + names = (address_mode == mode_64bit + ? names64 : names32); + if (!(prefixes & PREFIX_ADDR)) + names = (address_mode == mode_16bit + ? names16 : names); + else + { + /* Remove "addr16/addr32". */ + all_prefixes[last_addr_prefix] = 0; + names = (address_mode != mode_32bit + ? names32 : names16); + used_prefixes |= PREFIX_ADDR; + } + break; case mask_bd_mode: case mask_mode: if (reg > 0x7) @@ -15267,7 +15317,8 @@ OP_E_memory (int bytemode, int sizeflag) int scale = 0; int addr32flag = !((sizeflag & AFLAG) || bytemode == v_bnd_mode - || bytemode == bnd_mode); + || bytemode == bnd_mode + || bytemode == bnd_swap_mode); const char **indexes64 = names64; const char **indexes32 = names32; @@ -15384,7 +15435,8 @@ OP_E_memory (int bytemode, int sizeflag) if ((havebase || haveindex || riprel) && (bytemode != v_bnd_mode) - && (bytemode != bnd_mode)) + && (bytemode != bnd_mode) + && (bytemode != bnd_swap_mode)) used_prefixes |= PREFIX_ADDR; if (havedisp || (intel_syntax && riprel)) @@ -15484,6 +15536,8 @@ OP_E_memory (int bytemode, int sizeflag) disp = *codep++; if ((disp & 0x80) != 0) disp -= 0x100; + if (vex.evex && shift > 0) + disp <<= shift; break; case 2: disp = get16 (); @@ -17095,11 +17149,10 @@ OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) return; reg = vex.register_specifier; - if (vex.evex) - { - if (!vex.v) - reg += 16; - } + if (address_mode != mode_64bit) + reg &= 7; + else if (vex.evex && !vex.v) + reg += 16; if (bytemode == vex_scalar_mode) { @@ -17119,7 +17172,7 @@ OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) names = names_xmm; break; case dq_mode: - if (vex.w) + if (rex & REX_W) names = names64; else names = names32; @@ -17284,8 +17337,8 @@ OP_EX_VexReg (int bytemode, int sizeflag, int reg) if (rex & REX_B) reg += 8; } - else if (reg > 7 && address_mode != mode_64bit) - BadOp (); + if (address_mode != mode_64bit) + reg &= 7; } switch (vex.length) @@ -17377,7 +17430,13 @@ OP_Vex_2src_1 (int bytemode, int sizeflag) } if (vex.w) - oappend (names_xmm[vex.register_specifier]); + { + unsigned int reg = vex.register_specifier; + + if (address_mode != mode_64bit) + reg &= 7; + oappend (names_xmm[reg]); + } else OP_Vex_2src (bytemode, sizeflag); } @@ -17388,7 +17447,13 @@ OP_Vex_2src_2 (int bytemode, int sizeflag) if (vex.w) OP_Vex_2src (bytemode, sizeflag); else - oappend (names_xmm[vex.register_specifier]); + { + unsigned int reg = vex.register_specifier; + + if (address_mode != mode_64bit) + reg &= 7; + oappend (names_xmm[reg]); + } } static void @@ -17398,8 +17463,6 @@ OP_EX_VexW (int bytemode, int sizeflag) if (!vex_w_done) { - vex_w_done = 1; - /* Skip mod/rm byte. */ MODRM_CHECK; codep++; @@ -17414,16 +17477,10 @@ OP_EX_VexW (int bytemode, int sizeflag) } OP_EX_VexReg (bytemode, sizeflag, reg); -} -static void -VEXI4_Fixup (int bytemode ATTRIBUTE_UNUSED, - int sizeflag ATTRIBUTE_UNUSED) -{ - /* Skip the immediate byte and check for invalid bits. */ - FETCH_DATA (the_info, codep + 1); - if (*codep++ & 0xf) - BadOp (); + if (vex_w_done) + codep++; + vex_w_done = 1; } static void @@ -17438,12 +17495,9 @@ OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) if (bytemode != x_mode) abort (); - if (reg & 0xf) - BadOp (); - reg >>= 4; - if (reg > 7 && address_mode != mode_64bit) - BadOp (); + if (address_mode != mode_64bit) + reg &= 7; switch (vex.length) { @@ -17618,6 +17672,58 @@ VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, } } +static const struct op xop_cmp_op[] = +{ + { STRING_COMMA_LEN ("lt") }, + { STRING_COMMA_LEN ("le") }, + { STRING_COMMA_LEN ("gt") }, + { STRING_COMMA_LEN ("ge") }, + { STRING_COMMA_LEN ("eq") }, + { STRING_COMMA_LEN ("neq") }, + { STRING_COMMA_LEN ("false") }, + { STRING_COMMA_LEN ("true") } +}; + +static void +VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED, + int sizeflag ATTRIBUTE_UNUSED) +{ + unsigned int cmp_type; + + FETCH_DATA (the_info, codep + 1); + cmp_type = *codep++ & 0xff; + if (cmp_type < ARRAY_SIZE (xop_cmp_op)) + { + char suffix[3]; + char *p = mnemonicendp - 2; + + /* vpcom* can have both one- and two-lettered suffix. */ + if (p[0] == 'm') + { + p++; + suffix[0] = p[0]; + suffix[1] = '\0'; + } + else + { + suffix[0] = p[0]; + suffix[1] = p[1]; + suffix[2] = '\0'; + } + + sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix); + mnemonicendp += xop_cmp_op[cmp_type].len; + } + else + { + /* We have a reserved extension byte. Output it directly. */ + scratchbuf[0] = '$'; + print_operand_value (scratchbuf + 1, 1, cmp_type); + oappend_maybe_intel (scratchbuf); + scratchbuf[0] = '\0'; + } +} + static const struct op pclmul_op[] = { { STRING_COMMA_LEN ("lql") }, @@ -17714,7 +17820,7 @@ OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) MODRM_CHECK; codep++; - if (vex.w) + if (rex & REX_W) names = names64; else names = names32; @@ -17731,13 +17837,16 @@ static void OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) { const char **names; + unsigned int reg = vex.register_specifier; - if (vex.w) + if (rex & REX_W) names = names64; else names = names32; - oappend (names[vex.register_specifier]); + if (address_mode != mode_64bit) + reg &= 7; + oappend (names[reg]); } static void