X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Fi386-dis.c;h=dc814209256a4609695c324518a05871e86ff3eb;hb=ed48ec2e6ec5514f01b9b3a810d6ddf39651114b;hp=bc4db68a311675560ddd65741a31ba03e4751448;hpb=04e2a1829ea137ac23ac96e98fd60f9d720dcdcb;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index bc4db68a31..dc81420925 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -1,5 +1,5 @@ /* Print i386 instructions for GDB, the GNU debugger. - Copyright (C) 1988-2018 Free Software Foundation, Inc. + Copyright (C) 1988-2019 Free Software Foundation, Inc. This file is part of the GNU opcodes library. @@ -259,7 +259,6 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define Edb { OP_E, db_mode } #define Edw { OP_E, dw_mode } #define Edqd { OP_E, dqd_mode } -#define Edqa { OP_E, dqa_mode } #define Eq { OP_E, q_mode } #define indirEv { OP_indirE, indir_v_mode } #define indirEp { OP_indirE, f_mode } @@ -292,8 +291,8 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ #define Iv { OP_I, v_mode } #define sIv { OP_sI, v_mode } -#define Iq { OP_I, q_mode } #define Iv64 { OP_I64, v_mode } +#define Id { OP_I, d_mode } #define Iw { OP_I, w_mode } #define I1 { OP_I, const_1_mode } #define Jb { OP_J, b_mode } @@ -386,7 +385,6 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define EXd { OP_EX, d_mode } #define EXdScalar { OP_EX, d_scalar_mode } #define EXdS { OP_EX, d_swap_mode } -#define EXdScalarS { OP_EX, d_scalar_swap_mode } #define EXq { OP_EX, q_mode } #define EXqScalar { OP_EX, q_scalar_mode } #define EXqScalarS { OP_EX, q_scalar_swap_mode } @@ -426,17 +424,12 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr) #define Vex128 { OP_VEX, vex128_mode } #define Vex256 { OP_VEX, vex256_mode } #define VexGdq { OP_VEX, dq_mode } -#define EXdVex { OP_EX_Vex, d_mode } -#define EXdVexS { OP_EX_Vex, d_swap_mode } #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode } -#define EXqVex { OP_EX_Vex, q_mode } -#define EXqVexS { OP_EX_Vex, q_swap_mode } #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode } #define EXVexW { OP_EX_VexW, x_mode } #define EXdVexW { OP_EX_VexW, d_mode } #define EXqVexW { OP_EX_VexW, q_mode } #define EXVexImmW { OP_EX_VexImmW, x_mode } -#define XMVex { OP_XMM_Vex, 0 } #define XMVexScalar { OP_XMM_Vex, scalar_mode } #define XMVexW { OP_XMM_VexW, 0 } #define XMVexI4 { OP_REG_VexI4, x_mode } @@ -591,8 +584,6 @@ enum dw_mode, /* registers like dq_mode, memory like d_mode. */ dqd_mode, - /* operand size depends on the W bit as well as address mode. */ - dqa_mode, /* normal vex mode */ vex_mode, /* 128bit vex mode */ @@ -845,7 +836,9 @@ enum MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0, + MOD_0F38F8_PREFIX_1, MOD_0F38F8_PREFIX_2, + MOD_0F38F8_PREFIX_3, MOD_0F38F9_PREFIX_0, MOD_62_32BIT, MOD_C4_32BIT, @@ -903,12 +896,10 @@ enum MOD_VEX_W_1_0F91_P_2_LEN_0, MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0, - MOD_VEX_W_0_0F92_P_3_LEN_0, - MOD_VEX_W_1_0F92_P_3_LEN_0, + MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0, - MOD_VEX_W_0_0F93_P_3_LEN_0, - MOD_VEX_W_1_0F93_P_3_LEN_0, + MOD_VEX_0F93_P_3_LEN_0, MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0, MOD_VEX_W_0_0F98_P_2_LEN_0, @@ -940,10 +931,6 @@ enum MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0, - MOD_EVEX_0F10_PREFIX_1, - MOD_EVEX_0F10_PREFIX_3, - MOD_EVEX_0F11_PREFIX_1, - MOD_EVEX_0F11_PREFIX_3, MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1, @@ -1613,6 +1600,7 @@ enum PREFIX_EVEX_0F3864, PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, + PREFIX_EVEX_0F3868, PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872, @@ -1820,12 +1808,6 @@ enum VEX_LEN_0F16_P_0_M_1, VEX_LEN_0F16_P_2, VEX_LEN_0F17_M_0, - VEX_LEN_0F2A_P_1, - VEX_LEN_0F2A_P_3, - VEX_LEN_0F2C_P_1, - VEX_LEN_0F2C_P_3, - VEX_LEN_0F2D_P_1, - VEX_LEN_0F2D_P_3, VEX_LEN_0F41_P_0, VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, @@ -1936,7 +1918,49 @@ enum EVEX_LEN_0F6E_P_2 = 0, EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2, - EVEX_LEN_0FD6_P_2 + EVEX_LEN_0FD6_P_2, + EVEX_LEN_0F3819_P_2_W_0, + EVEX_LEN_0F3819_P_2_W_1, + EVEX_LEN_0F381A_P_2_W_0, + EVEX_LEN_0F381A_P_2_W_1, + EVEX_LEN_0F381B_P_2_W_0, + EVEX_LEN_0F381B_P_2_W_1, + EVEX_LEN_0F385A_P_2_W_0, + EVEX_LEN_0F385A_P_2_W_1, + EVEX_LEN_0F385B_P_2_W_0, + EVEX_LEN_0F385B_P_2_W_1, + EVEX_LEN_0F38C6_REG_1_PREFIX_2, + EVEX_LEN_0F38C6_REG_2_PREFIX_2, + EVEX_LEN_0F38C6_REG_5_PREFIX_2, + EVEX_LEN_0F38C6_REG_6_PREFIX_2, + EVEX_LEN_0F38C7_R_1_P_2_W_0, + EVEX_LEN_0F38C7_R_1_P_2_W_1, + EVEX_LEN_0F38C7_R_2_P_2_W_0, + EVEX_LEN_0F38C7_R_2_P_2_W_1, + EVEX_LEN_0F38C7_R_5_P_2_W_0, + EVEX_LEN_0F38C7_R_5_P_2_W_1, + EVEX_LEN_0F38C7_R_6_P_2_W_0, + EVEX_LEN_0F38C7_R_6_P_2_W_1, + EVEX_LEN_0F3A18_P_2_W_0, + EVEX_LEN_0F3A18_P_2_W_1, + EVEX_LEN_0F3A19_P_2_W_0, + EVEX_LEN_0F3A19_P_2_W_1, + EVEX_LEN_0F3A1A_P_2_W_0, + EVEX_LEN_0F3A1A_P_2_W_1, + EVEX_LEN_0F3A1B_P_2_W_0, + EVEX_LEN_0F3A1B_P_2_W_1, + EVEX_LEN_0F3A23_P_2_W_0, + EVEX_LEN_0F3A23_P_2_W_1, + EVEX_LEN_0F3A38_P_2_W_0, + EVEX_LEN_0F3A38_P_2_W_1, + EVEX_LEN_0F3A39_P_2_W_0, + EVEX_LEN_0F3A39_P_2_W_1, + EVEX_LEN_0F3A3A_P_2_W_0, + EVEX_LEN_0F3A3A_P_2_W_1, + EVEX_LEN_0F3A3B_P_2_W_0, + EVEX_LEN_0F3A3B_P_2_W_1, + EVEX_LEN_0F3A43_P_2_W_0, + EVEX_LEN_0F3A43_P_2_W_1 }; enum @@ -1963,16 +1987,12 @@ enum VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0, VEX_W_0F92_P_2_LEN_0, - VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_0_LEN_0, VEX_W_0F93_P_2_LEN_0, - VEX_W_0F93_P_3_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0, - VEX_W_0FC4_P_2, - VEX_W_0FC5_P_2, VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2, @@ -1999,11 +2019,8 @@ enum VEX_W_0F3A04_P_2, VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2, - VEX_W_0F3A14_P_2, - VEX_W_0F3A15_P_2, VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, - VEX_W_0F3A20_P_2, VEX_W_0F3A30_P_2_LEN_0, VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0, @@ -2020,17 +2037,13 @@ enum VEX_W_0F3ACF_P_2, EVEX_W_0F10_P_0, - EVEX_W_0F10_P_1_M_0, - EVEX_W_0F10_P_1_M_1, + EVEX_W_0F10_P_1, EVEX_W_0F10_P_2, - EVEX_W_0F10_P_3_M_0, - EVEX_W_0F10_P_3_M_1, + EVEX_W_0F10_P_3, EVEX_W_0F11_P_0, - EVEX_W_0F11_P_1_M_0, - EVEX_W_0F11_P_1_M_1, + EVEX_W_0F11_P_1, EVEX_W_0F11_P_2, - EVEX_W_0F11_P_3_M_0, - EVEX_W_0F11_P_3_M_1, + EVEX_W_0F11_P_3, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1, EVEX_W_0F12_P_1, @@ -2052,7 +2065,6 @@ enum EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, - EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2, @@ -2109,7 +2121,6 @@ enum EVEX_W_0F6B_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, - EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F6F_P_3, @@ -2126,11 +2137,9 @@ enum EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_2, EVEX_W_0F7A_P_3, - EVEX_W_0F7B_P_1, EVEX_W_0F7B_P_2, EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, - EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1, EVEX_W_0F7F_P_2, EVEX_W_0F7F_P_3, @@ -2200,6 +2209,7 @@ enum EVEX_W_0F3839_P_1, EVEX_W_0F383A_P_1, EVEX_W_0F3840_P_2, + EVEX_W_0F3852_P_1, EVEX_W_0F3854_P_2, EVEX_W_0F3855_P_2, EVEX_W_0F3858_P_2, @@ -2209,9 +2219,12 @@ enum EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2, EVEX_W_0F3866_P_2, + EVEX_W_0F3868_P_3, EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, + EVEX_W_0F3872_P_1, EVEX_W_0F3872_P_2, + EVEX_W_0F3872_P_3, EVEX_W_0F3873_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, @@ -2238,14 +2251,12 @@ enum EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2, - EVEX_W_0F3A16_P_2, EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2, EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2, - EVEX_W_0F3A22_P_2, EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, @@ -3577,33 +3588,32 @@ static const struct dis386 reg_table[][8] = { }, /* REG_XOP_LWP */ { - { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 }, - { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 }, + { "lwpins", { { OP_LWP_E, 0 }, Ed, Id }, 0 }, + { "lwpval", { { OP_LWP_E, 0 }, Ed, Id }, 0 }, }, /* REG_XOP_TBM_01 */ { { Bad_Opcode }, - { "blcfill", { { OP_LWP_E, 0 }, Ev }, 0 }, - { "blsfill", { { OP_LWP_E, 0 }, Ev }, 0 }, - { "blcs", { { OP_LWP_E, 0 }, Ev }, 0 }, - { "tzmsk", { { OP_LWP_E, 0 }, Ev }, 0 }, - { "blcic", { { OP_LWP_E, 0 }, Ev }, 0 }, - { "blsic", { { OP_LWP_E, 0 }, Ev }, 0 }, - { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 }, + { "blcfill", { { OP_LWP_E, 0 }, Edq }, 0 }, + { "blsfill", { { OP_LWP_E, 0 }, Edq }, 0 }, + { "blcs", { { OP_LWP_E, 0 }, Edq }, 0 }, + { "tzmsk", { { OP_LWP_E, 0 }, Edq }, 0 }, + { "blcic", { { OP_LWP_E, 0 }, Edq }, 0 }, + { "blsic", { { OP_LWP_E, 0 }, Edq }, 0 }, + { "t1mskc", { { OP_LWP_E, 0 }, Edq }, 0 }, }, /* REG_XOP_TBM_02 */ { { Bad_Opcode }, - { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 }, + { "blcmsk", { { OP_LWP_E, 0 }, Edq }, 0 }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, - { "blci", { { OP_LWP_E, 0 }, Ev }, 0 }, + { "blci", { { OP_LWP_E, 0 }, Edq }, 0 }, }, -#define NEED_REG_TABLE -#include "i386-dis-evex.h" -#undef NEED_REG_TABLE + +#include "i386-dis-evex-reg.h" }; static const struct dis386 prefix_table[][4] = { @@ -3705,9 +3715,9 @@ static const struct dis386 prefix_table[][4] = { /* PREFIX_0F2A */ { { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE }, - { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE }, + { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE }, { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE }, - { "cvtsi2sd%LQ", { XM, Ev }, 0 }, + { "cvtsi2sd%LQ", { XM, Edq }, 0 }, }, /* PREFIX_0F2B */ @@ -3721,17 +3731,17 @@ static const struct dis386 prefix_table[][4] = { /* PREFIX_0F2C */ { { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE }, - { "cvttss2si", { Gv, EXd }, PREFIX_OPCODE }, + { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE }, { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE }, - { "cvttsd2si", { Gv, EXq }, PREFIX_OPCODE }, + { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE }, }, /* PREFIX_0F2D */ { { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE }, - { "cvtss2si", { Gv, EXd }, PREFIX_OPCODE }, + { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE }, { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE }, - { "cvtsd2si", { Gv, EXq }, PREFIX_OPCODE }, + { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE }, }, /* PREFIX_0F2E */ @@ -4040,7 +4050,7 @@ static const struct dis386 prefix_table[][4] = { /* PREFIX_MOD_0_0FC3 */ { - { "movntiS", { Ev, Gv }, PREFIX_OPCODE }, + { "movntiS", { Edq, Gdq }, PREFIX_OPCODE }, }, /* PREFIX_MOD_0_0FC7_REG_6 */ @@ -4454,8 +4464,9 @@ static const struct dis386 prefix_table[][4] = { /* PREFIX_0F38F8 */ { { Bad_Opcode }, - { Bad_Opcode }, + { MOD_TABLE (MOD_0F38F8_PREFIX_1) }, { MOD_TABLE (MOD_0F38F8_PREFIX_2) }, + { MOD_TABLE (MOD_0F38F8_PREFIX_3) }, }, /* PREFIX_0F38F9 */ @@ -4677,25 +4688,25 @@ static const struct dis386 prefix_table[][4] = { /* PREFIX_VEX_0F2A */ { { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) }, + { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Edq }, 0 }, { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) }, + { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Edq }, 0 }, }, /* PREFIX_VEX_0F2C */ { { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) }, + { "vcvttss2si", { Gdq, EXdScalar }, 0 }, { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) }, + { "vcvttsd2si", { Gdq, EXqScalar }, 0 }, }, /* PREFIX_VEX_0F2D */ { { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) }, + { "vcvtss2si", { Gdq, EXdScalar }, 0 }, { Bad_Opcode }, - { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) }, + { "vcvtsd2si", { Gdq, EXqScalar }, 0 }, }, /* PREFIX_VEX_0F2E */ @@ -6768,9 +6779,7 @@ static const struct dis386 prefix_table[][4] = { { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) }, }, -#define NEED_PREFIX_TABLE -#include "i386-dis-evex.h" -#undef NEED_PREFIX_TABLE +#include "i386-dis-evex-prefix.h" }; static const struct dis386 x86_64_table[][2] = { @@ -8133,7 +8142,7 @@ static const struct dis386 xop_table[][256] = { { Bad_Opcode }, { Bad_Opcode }, /* 10 */ - { "bextr", { Gv, Ev, Iq }, 0 }, + { "bextrS", { Gdq, Edq, Id }, 0 }, { Bad_Opcode }, { REG_TABLE (REG_XOP_LWP) }, { Bad_Opcode }, @@ -9281,9 +9290,8 @@ static const struct dis386 vex_table[][256] = { }, }; -#define NEED_OPCODE_TABLE #include "i386-dis-evex.h" -#undef NEED_OPCODE_TABLE + static const struct dis386 vex_len_table[][2] = { /* VEX_LEN_0F12_P_0_M_0 */ { @@ -9325,42 +9333,6 @@ static const struct dis386 vex_len_table[][2] = { { "vmovhpX", { EXq, XM }, 0 }, }, - /* VEX_LEN_0F2A_P_1 */ - { - { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 }, - { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 }, - }, - - /* VEX_LEN_0F2A_P_3 */ - { - { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 }, - { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 }, - }, - - /* VEX_LEN_0F2C_P_1 */ - { - { "vcvttss2si", { Gv, EXdScalar }, 0 }, - { "vcvttss2si", { Gv, EXdScalar }, 0 }, - }, - - /* VEX_LEN_0F2C_P_3 */ - { - { "vcvttsd2si", { Gv, EXqScalar }, 0 }, - { "vcvttsd2si", { Gv, EXqScalar }, 0 }, - }, - - /* VEX_LEN_0F2D_P_1 */ - { - { "vcvtss2si", { Gv, EXdScalar }, 0 }, - { "vcvtss2si", { Gv, EXdScalar }, 0 }, - }, - - /* VEX_LEN_0F2D_P_3 */ - { - { "vcvtsd2si", { Gv, EXqScalar }, 0 }, - { "vcvtsd2si", { Gv, EXqScalar }, 0 }, - }, - /* VEX_LEN_0F41_P_0 */ { { Bad_Opcode }, @@ -9493,7 +9465,7 @@ static const struct dis386 vex_len_table[][2] = { /* VEX_LEN_0F92_P_3 */ { - { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) }, + { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) }, }, /* VEX_LEN_0F93_P_0 */ @@ -9508,7 +9480,7 @@ static const struct dis386 vex_len_table[][2] = { /* VEX_LEN_0F93_P_3 */ { - { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) }, + { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) }, }, /* VEX_LEN_0F98_P_0 */ @@ -9543,12 +9515,12 @@ static const struct dis386 vex_len_table[][2] = { /* VEX_LEN_0FC4_P_2 */ { - { VEX_W_TABLE (VEX_W_0FC4_P_2) }, + { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 }, }, /* VEX_LEN_0FC5_P_2 */ { - { VEX_W_TABLE (VEX_W_0FC5_P_2) }, + { "vpextrw", { Gdq, XS, Ib }, 0 }, }, /* VEX_LEN_0FD6_P_2 */ @@ -9681,12 +9653,12 @@ static const struct dis386 vex_len_table[][2] = { /* VEX_LEN_0F3A14_P_2 */ { - { VEX_W_TABLE (VEX_W_0F3A14_P_2) }, + { "vpextrb", { Edqb, XM, Ib }, 0 }, }, /* VEX_LEN_0F3A15_P_2 */ { - { VEX_W_TABLE (VEX_W_0F3A15_P_2) }, + { "vpextrw", { Edqw, XM, Ib }, 0 }, }, /* VEX_LEN_0F3A16_P_2 */ @@ -9713,7 +9685,7 @@ static const struct dis386 vex_len_table[][2] = { /* VEX_LEN_0F3A20_P_2 */ { - { VEX_W_TABLE (VEX_W_0F3A20_P_2) }, + { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 }, }, /* VEX_LEN_0F3A21_P_2 */ @@ -9892,11 +9864,7 @@ static const struct dis386 vex_len_table[][2] = { }, }; -static const struct dis386 evex_len_table[][3] = { -#define NEED_EVEX_LEN_TABLE -#include "i386-dis-evex.h" -#undef NEED_EVEX_LEN_TABLE -}; +#include "i386-dis-evex-len.h" static const struct dis386 vex_w_table[][2] = { { @@ -10006,11 +9974,6 @@ static const struct dis386 vex_w_table[][2] = { /* VEX_W_0F92_P_2_LEN_0 */ { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) }, }, - { - /* VEX_W_0F92_P_3_LEN_0 */ - { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) }, - { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) }, - }, { /* VEX_W_0F93_P_0_LEN_0 */ { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) }, @@ -10019,11 +9982,6 @@ static const struct dis386 vex_w_table[][2] = { /* VEX_W_0F93_P_2_LEN_0 */ { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) }, }, - { - /* VEX_W_0F93_P_3_LEN_0 */ - { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) }, - { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) }, - }, { /* VEX_W_0F98_P_0_LEN_0 */ { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) }, @@ -10044,14 +10002,6 @@ static const struct dis386 vex_w_table[][2] = { { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) }, { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) }, }, - { - /* VEX_W_0FC4_P_2 */ - { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 }, - }, - { - /* VEX_W_0FC5_P_2 */ - { "vpextrw", { Gdq, XS, Ib }, 0 }, - }, { /* VEX_W_0F380C_P_2 */ { "vpermilps", { XM, Vex, EXx }, 0 }, @@ -10158,14 +10108,6 @@ static const struct dis386 vex_w_table[][2] = { /* VEX_W_0F3A06_P_2 */ { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 }, }, - { - /* VEX_W_0F3A14_P_2 */ - { "vpextrb", { Edqb, XM, Ib }, 0 }, - }, - { - /* VEX_W_0F3A15_P_2 */ - { "vpextrw", { Edqw, XM, Ib }, 0 }, - }, { /* VEX_W_0F3A18_P_2 */ { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 }, @@ -10174,10 +10116,6 @@ static const struct dis386 vex_w_table[][2] = { /* VEX_W_0F3A19_P_2 */ { "vextractf128", { EXxmm, XM, Ib }, 0 }, }, - { - /* VEX_W_0F3A20_P_2 */ - { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 }, - }, { /* VEX_W_0F3A30_P_2_LEN_0 */ { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) }, @@ -10242,9 +10180,8 @@ static const struct dis386 vex_w_table[][2] = { { Bad_Opcode }, { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, 0 }, }, -#define NEED_VEX_W_TABLE -#include "i386-dis-evex.h" -#undef NEED_VEX_W_TABLE + +#include "i386-dis-evex-w.h" }; static const struct dis386 mod_table[][2] = { @@ -10559,10 +10496,18 @@ static const struct dis386 mod_table[][2] = { /* MOD_0F38F6_PREFIX_0 */ { "wrssK", { M, Gdq }, PREFIX_OPCODE }, }, + { + /* MOD_0F38F8_PREFIX_1 */ + { "enqcmds", { Gva, M }, PREFIX_OPCODE }, + }, { /* MOD_0F38F8_PREFIX_2 */ { "movdir64b", { Gva, M }, PREFIX_OPCODE }, }, + { + /* MOD_0F38F8_PREFIX_3 */ + { "enqcmd", { Gva, M }, PREFIX_OPCODE }, + }, { /* MOD_0F38F9_PREFIX_0 */ { "movdiri", { Em, Gv }, PREFIX_OPCODE }, @@ -10845,14 +10790,9 @@ static const struct dis386 mod_table[][2] = { { "kmovb", { MaskG, Rdq }, 0 }, }, { - /* MOD_VEX_W_0_0F92_P_3_LEN_0 */ + /* MOD_VEX_0F92_P_3_LEN_0 */ { Bad_Opcode }, - { "kmovd", { MaskG, Rdq }, 0 }, - }, - { - /* MOD_VEX_W_1_0F92_P_3_LEN_0 */ - { Bad_Opcode }, - { "kmovq", { MaskG, Rdq }, 0 }, + { "kmovK", { MaskG, Rdq }, 0 }, }, { /* MOD_VEX_W_0_0F93_P_0_LEN_0 */ @@ -10865,14 +10805,9 @@ static const struct dis386 mod_table[][2] = { { "kmovb", { Gdq, MaskR }, 0 }, }, { - /* MOD_VEX_W_0_0F93_P_3_LEN_0 */ + /* MOD_VEX_0F93_P_3_LEN_0 */ { Bad_Opcode }, - { "kmovd", { Gdq, MaskR }, 0 }, - }, - { - /* MOD_VEX_W_1_0F93_P_3_LEN_0 */ - { Bad_Opcode }, - { "kmovq", { Gdq, MaskR }, 0 }, + { "kmovK", { Gdq, MaskR }, 0 }, }, { /* MOD_VEX_W_0_0F98_P_0_LEN_0 */ @@ -11011,9 +10946,8 @@ static const struct dis386 mod_table[][2] = { { Bad_Opcode }, { "kshiftlq", { MaskG, MaskR, Ib }, 0 }, }, -#define NEED_MOD_TABLE -#include "i386-dis-evex.h" -#undef NEED_MOD_TABLE + +#include "i386-dis-evex-mod.h" }; static const struct dis386 rm_table[][8] = { @@ -11027,7 +10961,7 @@ static const struct dis386 rm_table[][8] = { }, { /* RM_0F01_REG_0 */ - { Bad_Opcode }, + { "enclv", { Skip_MODRM }, 0 }, { "vmcall", { Skip_MODRM }, 0 }, { "vmlaunch", { Skip_MODRM }, 0 }, { "vmresume", { Skip_MODRM }, 0 }, @@ -12192,6 +12126,14 @@ print_insn (bfd_vma pc, disassemble_info *info) } } + /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which + are all 0s in inverted form. */ + if (need_vex && vex.register_specifier != 0) + { + (*info->fprintf_func) (info->stream, "(bad)"); + return end_codep - priv.the_buffer; + } + /* Check if the REX prefix is used. */ if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0) all_prefixes[last_rex_prefix] = 0; @@ -13531,7 +13473,6 @@ intel_operand_size (int bytemode, int sizeflag) case q_swap_mode: oappend ("QWORD PTR "); break; - case dqa_mode: case m_mode: if (address_mode == mode_64bit) oappend ("QWORD PTR "); @@ -13890,7 +13831,6 @@ OP_E_register (int bytemode, int sizeflag) case dqb_mode: case dqd_mode: case dqw_mode: - case dqa_mode: USED_REX (REX_W); if (rex & REX_W) names = names64; @@ -13967,6 +13907,13 @@ OP_E_memory (int bytemode, int sizeflag) case db_mode: shift = 0; break; + case dq_mode: + if (address_mode != mode_64bit) + { + shift = 2; + break; + } + /* fall through */ case vex_vsib_d_w_dq_mode: case vex_vsib_d_w_d_mode: case vex_vsib_q_w_dq_mode: @@ -14033,9 +13980,6 @@ OP_E_memory (int bytemode, int sizeflag) case xmm_mb_mode: shift = 0; break; - case dqa_mode: - shift = address_mode == mode_64bit ? 3 : 2; - break; default: abort (); } @@ -14215,7 +14159,7 @@ OP_E_memory (int bytemode, int sizeflag) } } - if ((havebase || haveindex || needaddr32 || riprel) + if ((havebase || haveindex || needindex || needaddr32 || riprel) && (bytemode != v_bnd_mode) && (bytemode != v_bndmk_mode) && (bytemode != bnd_mode) @@ -14741,13 +14685,6 @@ OP_I (int bytemode, int sizeflag) op = *codep++; mask = 0xff; break; - case q_mode: - if (address_mode == mode_64bit) - { - op = get32s (); - break; - } - /* Fall through. */ case v_mode: USED_REX (REX_W); if (rex & REX_W) @@ -14767,6 +14704,10 @@ OP_I (int bytemode, int sizeflag) used_prefixes |= (prefixes & PREFIX_DATA); } break; + case d_mode: + mask = 0xffffffff; + op = get32 (); + break; case w_mode: mask = 0xfffff; op = get16 (); @@ -14790,53 +14731,16 @@ OP_I (int bytemode, int sizeflag) static void OP_I64 (int bytemode, int sizeflag) { - bfd_signed_vma op; - bfd_signed_vma mask = -1; - - if (address_mode != mode_64bit) + if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W)) { OP_I (bytemode, sizeflag); return; } - switch (bytemode) - { - case b_mode: - FETCH_DATA (the_info, codep + 1); - op = *codep++; - mask = 0xff; - break; - case v_mode: - USED_REX (REX_W); - if (rex & REX_W) - op = get64 (); - else - { - if (sizeflag & DFLAG) - { - op = get32 (); - mask = 0xffffffff; - } - else - { - op = get16 (); - mask = 0xfffff; - } - used_prefixes |= (prefixes & PREFIX_DATA); - } - break; - case w_mode: - mask = 0xfffff; - op = get16 (); - break; - default: - oappend (INTERNAL_DISASSEMBLER_ERROR); - return; - } + USED_REX (REX_W); - op &= mask; scratchbuf[0] = '$'; - print_operand_value (scratchbuf + 1, 1, op); + print_operand_value (scratchbuf + 1, 1, get64 ()); oappend_maybe_intel (scratchbuf); scratchbuf[0] = '\0'; } @@ -15951,6 +15855,7 @@ OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) return; reg = vex.register_specifier; + vex.register_specifier = 0; if (address_mode != mode_64bit) reg &= 7; else if (vex.evex && !vex.v) @@ -16234,6 +16139,7 @@ OP_Vex_2src_1 (int bytemode, int sizeflag) if (vex.w) { unsigned int reg = vex.register_specifier; + vex.register_specifier = 0; if (address_mode != mode_64bit) reg &= 7; @@ -16251,6 +16157,7 @@ OP_Vex_2src_2 (int bytemode, int sizeflag) else { unsigned int reg = vex.register_specifier; + vex.register_specifier = 0; if (address_mode != mode_64bit) reg &= 7; @@ -16328,11 +16235,7 @@ static void OP_EX_Vex (int bytemode, int sizeflag) { if (modrm.mod != 3) - { - if (vex.register_specifier != 0) - BadOp (); - need_vex_reg = 0; - } + need_vex_reg = 0; OP_EX (bytemode, sizeflag); } @@ -16340,11 +16243,7 @@ static void OP_XMM_Vex (int bytemode, int sizeflag) { if (modrm.mod != 3) - { - if (vex.register_specifier != 0) - BadOp (); - need_vex_reg = 0; - } + need_vex_reg = 0; OP_XMM (bytemode, sizeflag); } @@ -16624,6 +16523,7 @@ OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) { const char **names; unsigned int reg = vex.register_specifier; + vex.register_specifier = 0; if (rex & REX_W) names = names64;