X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Fi386-opc.h;h=00fbe1c3ebaf8762c84a02ca2c3e6480b9fe973f;hb=97ab0fdd9d053ee9201c74d4234fb68c74916548;hp=5e7dbca82c6071a2323c84f7d4d5917c7cfb1d6b;hpb=40fb982012fd45d5f37c2e3c02b07789529d377f;p=deliverable%2Fbinutils-gdb.git

diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 5e7dbca82c..00fbe1c3eb 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -78,8 +78,10 @@
 #define CpuSSE4_1	(CpuABM + 1)
 /* SSE4.2 support required */
 #define CpuSSE4_2	(CpuSSE4_1 + 1)
+/* SSE5 support required */
+#define CpuSSE5         (CpuSSE4_2 + 1)
 /* 64bit support available, used by -march= in assembler.  */
-#define CpuLM		(CpuSSE4_2 + 1)
+#define CpuLM		(CpuSSE5 + 1)
 /* 64bit support required  */
 #define Cpu64		(CpuLM + 1)
 /* Not supported in the 64bit mode  */
@@ -94,7 +96,7 @@
 
 /* If you get a compiler error for zero width of the unused field,
    comment it out.  */
-#define CpuUnused	(CpuNo64 + 1)
+#define CpuUnused	(CpuMax + 1)
 
 /* We can check if an instruction is available with array instead
    of bitfield. */
@@ -126,6 +128,7 @@ typedef union i386_cpu_flags
       unsigned int cpuabm:1;
       unsigned int cpusse4_1:1;
       unsigned int cpusse4_2:1;
+      unsigned int cpusse5:1;
       unsigned int cpulm:1;
       unsigned int cpu64:1;
       unsigned int cpuno64:1;
@@ -199,8 +202,13 @@ typedef union i386_cpu_flags
 #define Rex64			(NoRex64 + 1)
 /* deprecated fp insn, gets a warning */
 #define Ugh			(Rex64 + 1)
+#define Drex                    (Ugh + 1)
+/* instruction needs DREX with multiple encodings for memory ops */
+#define Drexv                   (Drex + 1)
+/* special DREX for comparisons */
+#define Drexc                   (Drexv + 1)
 /* The last bitfield in i386_opcode_modifier.  */
-#define Opcode_Modifier_Max	Ugh
+#define Opcode_Modifier_Max	Drexc
 
 typedef struct i386_opcode_modifier
 {
@@ -234,6 +242,9 @@ typedef struct i386_opcode_modifier
   unsigned int norex64:1;
   unsigned int rex64:1;
   unsigned int ugh:1;
+  unsigned int drex:1;
+  unsigned int drexv:1;
+  unsigned int drexc:1;
 } i386_opcode_modifier;
 
 /* Position of operand_type bits.  */
@@ -334,7 +345,7 @@ typedef struct i386_opcode_modifier
 /* If you get a compiler error for zero width of the unused field,
    comment it out.  */
 #if 0
-#define OTUnused		(RegMem + 1)
+#define OTUnused		(OTMax + 1)
 #endif
 
 typedef union i386_operand_type
@@ -400,7 +411,8 @@ typedef struct template
   /* extension_opcode is the 3 bit extension for group <n> insns.
      This field is also used to store the 8-bit opcode suffix for the
      AMD 3DNow! instructions.
-     If this template has no extension opcode (the usual case) use None */
+     If this template has no extension opcode (the usual case) use None 
+     Instructions with Drex use this to specify 2 bits for OC */
   unsigned int extension_opcode;
 #define None 0xffff		/* If no extension_opcode is possible.  */
 
@@ -431,6 +443,7 @@ typedef struct
 #define RegRex	    0x1  /* Extended register.  */
 #define RegRex64    0x2  /* Extended 8 bit register.  */
   unsigned int reg_num;
+#define RegRip	((unsigned int ) ~0)
 }
 reg_entry;