X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Fi386-opc.h;h=6c48dbc54e62f58370ff127b10ed1e6220dd55a9;hb=ec15ac506168c7b0ead70d5d52c5d3fd18c5acab;hp=d66f02bbbde7208b35a7b99bff9231240c263f6c;hpb=b7240065b3828ccd6ef9f793f8f7ed885f32688c;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index d66f02bbbd..6c48dbc54e 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -1,5 +1,5 @@ /* Declarations for Intel 80386 opcode table - Copyright 2007, 2008 + Copyright 2007, 2008, 2009 Free Software Foundation, Inc. This file is part of the GNU opcodes library. @@ -30,66 +30,93 @@ /* Position of cpu flags bitfiled. */ -/* i186 or better required */ -#define Cpu186 0 -/* i286 or better required */ -#define Cpu286 (Cpu186 + 1) -/* i386 or better required */ -#define Cpu386 (Cpu286 + 1) -/* i486 or better required */ -#define Cpu486 (Cpu386 + 1) -/* i585 or better required */ -#define Cpu586 (Cpu486 + 1) -/* i686 or better required */ -#define Cpu686 (Cpu586 + 1) -/* Pentium4 or better required */ -#define CpuP4 (Cpu686 + 1) -/* AMD K6 or better required*/ -#define CpuK6 (CpuP4 + 1) -/* AMD K8 or better required */ -#define CpuK8 (CpuK6 + 1) -/* MMX support required */ -#define CpuMMX (CpuK8 + 1) -/* SSE support required */ -#define CpuSSE (CpuMMX + 1) -/* SSE2 support required */ -#define CpuSSE2 (CpuSSE + 1) -/* 3dnow! support required */ -#define Cpu3dnow (CpuSSE2 + 1) -/* 3dnow! Extensions support required */ -#define Cpu3dnowA (Cpu3dnow + 1) -/* SSE3 support required */ -#define CpuSSE3 (Cpu3dnowA + 1) -/* VIA PadLock required */ -#define CpuPadLock (CpuSSE3 + 1) -/* AMD Secure Virtual Machine Ext-s required */ -#define CpuSVME (CpuPadLock + 1) -/* VMX Instructions required */ -#define CpuVMX (CpuSVME + 1) -/* SMX Instructions required */ -#define CpuSMX (CpuVMX + 1) -/* SSSE3 support required */ -#define CpuSSSE3 (CpuSMX + 1) -/* SSE4a support required */ -#define CpuSSE4a (CpuSSSE3 + 1) -/* ABM New Instructions required */ -#define CpuABM (CpuSSE4a + 1) -/* SSE4.1 support required */ -#define CpuSSE4_1 (CpuABM + 1) -/* SSE4.2 support required */ -#define CpuSSE4_2 (CpuSSE4_1 + 1) -/* SSE5 support required */ -#define CpuSSE5 (CpuSSE4_2 + 1) -/* Xsave/xrstor New Instuctions support required */ -#define CpuXsave (CpuSSE5 + 1) -/* 64bit support available, used by -march= in assembler. */ -#define CpuLM (CpuXsave + 1) -/* 64bit support required */ -#define Cpu64 (CpuLM + 1) -/* Not supported in the 64bit mode */ -#define CpuNo64 (Cpu64 + 1) -/* The last bitfield in i386_cpu_flags. */ -#define CpuMax CpuNo64 +enum +{ + /* i186 or better required */ + Cpu186 = 0, + /* i286 or better required */ + Cpu286, + /* i386 or better required */ + Cpu386, + /* i486 or better required */ + Cpu486, + /* i585 or better required */ + Cpu586, + /* i686 or better required */ + Cpu686, + /* CLFLUSH Instuction support required */ + CpuClflush, + /* SYSCALL Instuctions support required */ + CpuSYSCALL, + /* Floating point support required */ + Cpu8087, + /* i287 support required */ + Cpu287, + /* i387 support required */ + Cpu387, + /* i686 and floating point support required */ + Cpu687, + /* SSE3 and floating point support required */ + CpuFISTTP, + /* MMX support required */ + CpuMMX, + /* SSE support required */ + CpuSSE, + /* SSE2 support required */ + CpuSSE2, + /* 3dnow! support required */ + Cpu3dnow, + /* 3dnow! Extensions support required */ + Cpu3dnowA, + /* SSE3 support required */ + CpuSSE3, + /* VIA PadLock required */ + CpuPadLock, + /* AMD Secure Virtual Machine Ext-s required */ + CpuSVME, + /* VMX Instructions required */ + CpuVMX, + /* SMX Instructions required */ + CpuSMX, + /* SSSE3 support required */ + CpuSSSE3, + /* SSE4a support required */ + CpuSSE4a, + /* ABM New Instructions required */ + CpuABM, + /* SSE4.1 support required */ + CpuSSE4_1, + /* SSE4.2 support required */ + CpuSSE4_2, + /* AVX support required */ + CpuAVX, + /* Intel L1OM support required */ + CpuL1OM, + /* Xsave/xrstor New Instuctions support required */ + CpuXsave, + /* AES support required */ + CpuAES, + /* PCLMUL support required */ + CpuPCLMUL, + /* FMA support required */ + CpuFMA, + /* FMA4 support required */ + CpuFMA4, + /* MOVBE Instuction support required */ + CpuMovbe, + /* EPT Instructions required */ + CpuEPT, + /* RDTSCP Instuction support required */ + CpuRdtscp, + /* 64bit support available, used by -march= in assembler. */ + CpuLM, + /* 64bit support required */ + Cpu64, + /* Not supported in the 64bit mode */ + CpuNo64, + /* The last bitfield in i386_cpu_flags. */ + CpuMax = CpuNo64 +}; #define CpuNumOfUints \ (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1) @@ -112,9 +139,13 @@ typedef union i386_cpu_flags unsigned int cpui486:1; unsigned int cpui586:1; unsigned int cpui686:1; - unsigned int cpup4:1; - unsigned int cpuk6:1; - unsigned int cpuk8:1; + unsigned int cpuclflush:1; + unsigned int cpusyscall:1; + unsigned int cpu8087:1; + unsigned int cpu287:1; + unsigned int cpu387:1; + unsigned int cpu687:1; + unsigned int cpufisttp:1; unsigned int cpummx:1; unsigned int cpusse:1; unsigned int cpusse2:1; @@ -130,8 +161,16 @@ typedef union i386_cpu_flags unsigned int cpuabm:1; unsigned int cpusse4_1:1; unsigned int cpusse4_2:1; - unsigned int cpusse5:1; + unsigned int cpuavx:1; + unsigned int cpul1om:1; unsigned int cpuxsave:1; + unsigned int cpuaes:1; + unsigned int cpupclmul:1; + unsigned int cpufma:1; + unsigned int cpufma4:1; + unsigned int cpumovbe:1; + unsigned int cpuept:1; + unsigned int cpurdtscp:1; unsigned int cpulm:1; unsigned int cpu64:1; unsigned int cpuno64:1; @@ -144,98 +183,131 @@ typedef union i386_cpu_flags /* Position of opcode_modifier bits. */ -/* has direction bit. */ -#define D 0 -/* set if operands can be words or dwords encoded the canonical way */ -#define W (D + 1) -/* insn has a modrm byte. */ -#define Modrm (W + 1) -/* register is in low 3 bits of opcode */ -#define ShortForm (Modrm + 1) -/* special case for jump insns. */ -#define Jump (ShortForm + 1) -/* call and jump */ -#define JumpDword (Jump + 1) -/* loop and jecxz */ -#define JumpByte (JumpDword + 1) -/* special case for intersegment leaps/calls */ -#define JumpInterSegment (JumpByte + 1) -/* FP insn memory format bit, sized by 0x4 */ -#define FloatMF (JumpInterSegment + 1) -/* src/dest swap for floats. */ -#define FloatR (FloatMF + 1) -/* has float insn direction bit. */ -#define FloatD (FloatR + 1) -/* needs size prefix if in 32-bit mode */ -#define Size16 (FloatD + 1) -/* needs size prefix if in 16-bit mode */ -#define Size32 (Size16 + 1) -/* needs size prefix if in 64-bit mode */ -#define Size64 (Size32 + 1) -/* instruction ignores operand size prefix and in Intel mode ignores - mnemonic size suffix check. */ -#define IgnoreSize (Size64 + 1) -/* default insn size depends on mode */ -#define DefaultSize (IgnoreSize + 1) -/* b suffix on instruction illegal */ -#define No_bSuf (DefaultSize + 1) -/* w suffix on instruction illegal */ -#define No_wSuf (No_bSuf + 1) -/* l suffix on instruction illegal */ -#define No_lSuf (No_wSuf + 1) -/* s suffix on instruction illegal */ -#define No_sSuf (No_lSuf + 1) -/* q suffix on instruction illegal */ -#define No_qSuf (No_sSuf + 1) -/* long double suffix on instruction illegal */ -#define No_ldSuf (No_qSuf + 1) -/* instruction needs FWAIT */ -#define FWait (No_ldSuf + 1) -/* quick test for string instructions */ -#define IsString (FWait + 1) -/* fake an extra reg operand for clr, imul and special register - processing for some instructions. */ -#define RegKludge (IsString + 1) -/* The first operand must be xmm0 */ -#define FirstXmm0 (RegKludge + 1) -/* BYTE is OK in Intel syntax. */ -#define ByteOkIntel (FirstXmm0 + 1) -/* Convert to DWORD */ -#define ToDword (ByteOkIntel + 1) -/* Convert to QWORD */ -#define ToQword (ToDword + 1) -/* Address prefix changes operand 0 */ -#define AddrPrefixOp0 (ToQword + 1) -/* opcode is a prefix */ -#define IsPrefix (AddrPrefixOp0 + 1) -/* instruction has extension in 8 bit imm */ -#define ImmExt (IsPrefix + 1) -/* instruction don't need Rex64 prefix. */ -#define NoRex64 (ImmExt + 1) -/* instruction require Rex64 prefix. */ -#define Rex64 (NoRex64 + 1) -/* deprecated fp insn, gets a warning */ -#define Ugh (Rex64 + 1) -#define Drex (Ugh + 1) -/* instruction needs DREX with multiple encodings for memory ops */ -#define Drexv (Drex + 1) -/* special DREX for comparisons */ -#define Drexc (Drexv + 1) -/* Compatible with old (<= 2.8.1) versions of gcc */ -#define OldGcc (Drexc + 1) -/* AT&T mnemonic. */ -#define ATTMnemonic (OldGcc + 1) -/* AT&T syntax. */ -#define ATTSyntax (ATTMnemonic + 1) -/* Intel syntax. */ -#define IntelSyntax (ATTSyntax + 1) -/* The last bitfield in i386_opcode_modifier. */ -#define Opcode_Modifier_Max IntelSyntax +enum +{ + /* has direction bit. */ + D = 0, + /* set if operands can be words or dwords encoded the canonical way */ + W, + /* Skip the current insn and use the next insn in i386-opc.tbl to swap + operand in encoding. */ + S, + /* insn has a modrm byte. */ + Modrm, + /* register is in low 3 bits of opcode */ + ShortForm, + /* special case for jump insns. */ + Jump, + /* call and jump */ + JumpDword, + /* loop and jecxz */ + JumpByte, + /* special case for intersegment leaps/calls */ + JumpInterSegment, + /* FP insn memory format bit, sized by 0x4 */ + FloatMF, + /* src/dest swap for floats. */ + FloatR, + /* has float insn direction bit. */ + FloatD, + /* needs size prefix if in 32-bit mode */ + Size16, + /* needs size prefix if in 16-bit mode */ + Size32, + /* needs size prefix if in 64-bit mode */ + Size64, + /* instruction ignores operand size prefix and in Intel mode ignores + mnemonic size suffix check. */ + IgnoreSize, + /* default insn size depends on mode */ + DefaultSize, + /* b suffix on instruction illegal */ + No_bSuf, + /* w suffix on instruction illegal */ + No_wSuf, + /* l suffix on instruction illegal */ + No_lSuf, + /* s suffix on instruction illegal */ + No_sSuf, + /* q suffix on instruction illegal */ + No_qSuf, + /* long double suffix on instruction illegal */ + No_ldSuf, + /* instruction needs FWAIT */ + FWait, + /* quick test for string instructions */ + IsString, + /* fake an extra reg operand for clr, imul and special register + processing for some instructions. */ + RegKludge, + /* The first operand must be xmm0 */ + FirstXmm0, + /* An implicit xmm0 as the first operand */ + Implicit1stXmm0, + /* BYTE is OK in Intel syntax. */ + ByteOkIntel, + /* Convert to DWORD */ + ToDword, + /* Convert to QWORD */ + ToQword, + /* Address prefix changes operand 0 */ + AddrPrefixOp0, + /* opcode is a prefix */ + IsPrefix, + /* instruction has extension in 8 bit imm */ + ImmExt, + /* instruction don't need Rex64 prefix. */ + NoRex64, + /* instruction require Rex64 prefix. */ + Rex64, + /* deprecated fp insn, gets a warning */ + Ugh, + /* insn has VEX prefix: + 1: 128bit VEX prefix. + 2: 256bit VEX prefix. + */ + Vex, + /* insn has VEX NDS. Register-only source is encoded in Vex prefix. + We use VexNDS on insns with VEX DDS since the register-only source + is the second source register. */ + VexNDS, + /* insn has VEX NDD. Register destination is encoded in Vex prefix. */ + VexNDD, + /* insn has VEX W0. */ + VexW0, + /* insn has VEX W1. */ + VexW1, + /* insn has VEX 0x0F opcode prefix. */ + Vex0F, + /* insn has VEX 0x0F38 opcode prefix. */ + Vex0F38, + /* insn has VEX 0x0F3A opcode prefix. */ + Vex0F3A, + /* insn has VEX prefix with 3 soures. */ + Vex3Sources, + /* instruction has VEX 8 bit imm */ + VexImmExt, + /* SSE to AVX support required */ + SSE2AVX, + /* No AVX equivalent */ + NoAVX, + /* Compatible with old (<= 2.8.1) versions of gcc */ + OldGcc, + /* AT&T mnemonic. */ + ATTMnemonic, + /* AT&T syntax. */ + ATTSyntax, + /* Intel syntax. */ + IntelSyntax, + /* The last bitfield in i386_opcode_modifier. */ + Opcode_Modifier_Max +}; typedef struct i386_opcode_modifier { unsigned int d:1; unsigned int w:1; + unsigned int s:1; unsigned int modrm:1; unsigned int shortform:1; unsigned int jump:1; @@ -260,6 +332,7 @@ typedef struct i386_opcode_modifier unsigned int isstring:1; unsigned int regkludge:1; unsigned int firstxmm0:1; + unsigned int implicit1stxmm0:1; unsigned int byteokintel:1; unsigned int todword:1; unsigned int toqword:1; @@ -269,9 +342,18 @@ typedef struct i386_opcode_modifier unsigned int norex64:1; unsigned int rex64:1; unsigned int ugh:1; - unsigned int drex:1; - unsigned int drexv:1; - unsigned int drexc:1; + unsigned int vex:2; + unsigned int vexnds:1; + unsigned int vexndd:1; + unsigned int vexw0:1; + unsigned int vexw1:1; + unsigned int vex0f:1; + unsigned int vex0f38:1; + unsigned int vex0f3a:1; + unsigned int vex3sources:1; + unsigned int veximmext:1; + unsigned int sse2avx:1; + unsigned int noavx:1; unsigned int oldgcc:1; unsigned int attmnemonic:1; unsigned int attsyntax:1; @@ -280,104 +362,111 @@ typedef struct i386_opcode_modifier /* Position of operand_type bits. */ -/* 8bit register */ -#define Reg8 0 -/* 16bit register */ -#define Reg16 (Reg8 + 1) -/* 32bit register */ -#define Reg32 (Reg16 + 1) -/* 64bit register */ -#define Reg64 (Reg32 + 1) -/* Floating pointer stack register */ -#define FloatReg (Reg64 + 1) -/* MMX register */ -#define RegMMX (FloatReg + 1) -/* SSE register */ -#define RegXMM (RegMMX + 1) -/* Control register */ -#define Control (RegXMM + 1) -/* Debug register */ -#define Debug (Control + 1) -/* Test register */ -#define Test (Debug + 1) -/* 2 bit segment register */ -#define SReg2 (Test + 1) -/* 3 bit segment register */ -#define SReg3 (SReg2 + 1) -/* 1 bit immediate */ -#define Imm1 (SReg3 + 1) -/* 8 bit immediate */ -#define Imm8 (Imm1 + 1) -/* 8 bit immediate sign extended */ -#define Imm8S (Imm8 + 1) -/* 16 bit immediate */ -#define Imm16 (Imm8S + 1) -/* 32 bit immediate */ -#define Imm32 (Imm16 + 1) -/* 32 bit immediate sign extended */ -#define Imm32S (Imm32 + 1) -/* 64 bit immediate */ -#define Imm64 (Imm32S + 1) -/* 8bit/16bit/32bit displacements are used in different ways, - depending on the instruction. For jumps, they specify the - size of the PC relative displacement, for instructions with - memory operand, they specify the size of the offset relative - to the base register, and for instructions with memory offset - such as `mov 1234,%al' they specify the size of the offset - relative to the segment base. */ -/* 8 bit displacement */ -#define Disp8 (Imm64 + 1) -/* 16 bit displacement */ -#define Disp16 (Disp8 + 1) -/* 32 bit displacement */ -#define Disp32 (Disp16 + 1) -/* 32 bit signed displacement */ -#define Disp32S (Disp32 + 1) -/* 64 bit displacement */ -#define Disp64 (Disp32S + 1) -/* Accumulator %al/%ax/%eax/%rax */ -#define Acc (Disp64 + 1) -/* Floating pointer top stack register %st(0) */ -#define FloatAcc (Acc + 1) -/* Register which can be used for base or index in memory operand. */ -#define BaseIndex (FloatAcc + 1) -/* Register to hold in/out port addr = dx */ -#define InOutPortReg (BaseIndex + 1) -/* Register to hold shift count = cl */ -#define ShiftCount (InOutPortReg + 1) -/* Absolute address for jump. */ -#define JumpAbsolute (ShiftCount + 1) -/* String insn operand with fixed es segment */ -#define EsSeg (JumpAbsolute + 1) -/* RegMem is for instructions with a modrm byte where the register - destination operand should be encoded in the mod and regmem fields. - Normally, it will be encoded in the reg field. We add a RegMem - flag to the destination register operand to indicate that it should - be encoded in the regmem field. */ -#define RegMem (EsSeg + 1) -/* Memory. */ -#define Mem (RegMem + 1) -/* BYTE memory. */ -#define Byte (Mem + 1) -/* WORD memory. 2 byte */ -#define Word (Byte + 1) -/* DWORD memory. 4 byte */ -#define Dword (Word + 1) -/* FWORD memory. 6 byte */ -#define Fword (Dword + 1) -/* QWORD memory. 8 byte */ -#define Qword (Fword + 1) -/* TBYTE memory. 10 byte */ -#define Tbyte (Qword + 1) -/* XMMWORD memory. */ -#define Xmmword (Tbyte + 1) -/* Unspecified memory size. */ -#define Unspecified (Xmmword + 1) -/* Any memory size. */ -#define Anysize (Unspecified + 1) - -/* The last bitfield in i386_operand_type. */ -#define OTMax Anysize +enum +{ + /* 8bit register */ + Reg8 = 0, + /* 16bit register */ + Reg16, + /* 32bit register */ + Reg32, + /* 64bit register */ + Reg64, + /* Floating pointer stack register */ + FloatReg, + /* MMX register */ + RegMMX, + /* SSE register */ + RegXMM, + /* AVX registers */ + RegYMM, + /* Control register */ + Control, + /* Debug register */ + Debug, + /* Test register */ + Test, + /* 2 bit segment register */ + SReg2, + /* 3 bit segment register */ + SReg3, + /* 1 bit immediate */ + Imm1, + /* 8 bit immediate */ + Imm8, + /* 8 bit immediate sign extended */ + Imm8S, + /* 16 bit immediate */ + Imm16, + /* 32 bit immediate */ + Imm32, + /* 32 bit immediate sign extended */ + Imm32S, + /* 64 bit immediate */ + Imm64, + /* 8bit/16bit/32bit displacements are used in different ways, + depending on the instruction. For jumps, they specify the + size of the PC relative displacement, for instructions with + memory operand, they specify the size of the offset relative + to the base register, and for instructions with memory offset + such as `mov 1234,%al' they specify the size of the offset + relative to the segment base. */ + /* 8 bit displacement */ + Disp8, + /* 16 bit displacement */ + Disp16, + /* 32 bit displacement */ + Disp32, + /* 32 bit signed displacement */ + Disp32S, + /* 64 bit displacement */ + Disp64, + /* Accumulator %al/%ax/%eax/%rax */ + Acc, + /* Floating pointer top stack register %st(0) */ + FloatAcc, + /* Register which can be used for base or index in memory operand. */ + BaseIndex, + /* Register to hold in/out port addr = dx */ + InOutPortReg, + /* Register to hold shift count = cl */ + ShiftCount, + /* Absolute address for jump. */ + JumpAbsolute, + /* String insn operand with fixed es segment */ + EsSeg, + /* RegMem is for instructions with a modrm byte where the register + destination operand should be encoded in the mod and regmem fields. + Normally, it will be encoded in the reg field. We add a RegMem + flag to the destination register operand to indicate that it should + be encoded in the regmem field. */ + RegMem, + /* Memory. */ + Mem, + /* BYTE memory. */ + Byte, + /* WORD memory. 2 byte */ + Word, + /* DWORD memory. 4 byte */ + Dword, + /* FWORD memory. 6 byte */ + Fword, + /* QWORD memory. 8 byte */ + Qword, + /* TBYTE memory. 10 byte */ + Tbyte, + /* XMMWORD memory. */ + Xmmword, + /* YMMWORD memory. */ + Ymmword, + /* Unspecified memory size. */ + Unspecified, + /* Any memory size. */ + Anysize, + + /* The last bitfield in i386_operand_type. */ + OTMax +}; #define OTNumOfUints \ (OTMax / sizeof (unsigned int) / CHAR_BIT + 1) @@ -399,6 +488,7 @@ typedef union i386_operand_type unsigned int floatreg:1; unsigned int regmmx:1; unsigned int regxmm:1; + unsigned int regymm:1; unsigned int control:1; unsigned int debug:1; unsigned int test:1; @@ -432,6 +522,7 @@ typedef union i386_operand_type unsigned int qword:1; unsigned int tbyte:1; unsigned int xmmword:1; + unsigned int ymmword:1; unsigned int unspecified:1; unsigned int anysize:1; #ifdef OTUnused @@ -441,7 +532,7 @@ typedef union i386_operand_type unsigned int array[OTNumOfUints]; } i386_operand_type; -typedef struct template +typedef struct insn_template { /* instruction name sans width suffix ("mov" for movl insns) */ char *name; @@ -462,7 +553,7 @@ typedef struct template This field is also used to store the 8-bit opcode suffix for the AMD 3DNow! instructions. If this template has no extension opcode (the usual case) use None - Instructions with Drex use this to specify 2 bits for OC */ + Instructions */ unsigned int extension_opcode; #define None 0xffff /* If no extension_opcode is possible. */ @@ -483,9 +574,9 @@ typedef struct template either a register or an immediate operand. */ i386_operand_type operand_types[MAX_OPERANDS]; } -template; +insn_template; -extern const template i386_optab[]; +extern const insn_template i386_optab[]; /* these are for register name --> number & type hash lookup */ typedef struct