X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Fi386-opc.h;h=8d5dade9ab2121895200ecee8efb895b62a6287a;hb=ea783ef3a075b7581b93615f8aec39490d272b4f;hp=9442211f225d380cc7e78fdf0832101aec38d363;hpb=77321f536016efc2e18fbef88016b1fbad25afd1;p=deliverable%2Fbinutils-gdb.git

diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 9442211f22..8d5dade9ab 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -44,9 +44,11 @@ enum
   Cpu586,
   /* i686 or better required */
   Cpu686,
-  /* CLFLUSH Instuction support required */
+  /* CLFLUSH Instruction support required */
   CpuClflush,
-  /* SYSCALL Instuctions support required */
+  /* NOP Instruction support required */
+  CpuNop,
+  /* SYSCALL Instructions support required */
   CpuSYSCALL,
   /* Floating point support required */
   Cpu8087,
@@ -90,11 +92,15 @@ enum
   CpuSSE4_2,
   /* AVX support required */
   CpuAVX,
+  /* AVX2 support required */
+  CpuAVX2,
   /* Intel L1OM support required */
   CpuL1OM,
-  /* Xsave/xrstor New Instuctions support required */
+  /* Intel K1OM support required */
+  CpuK1OM,
+  /* Xsave/xrstor New Instructions support required */
   CpuXsave,
-  /* Xsaveopt New Instuctions support required */
+  /* Xsaveopt New Instructions support required */
   CpuXsaveopt,
   /* AES support required */
   CpuAES,
@@ -108,11 +114,15 @@ enum
   CpuXOP,
   /* LWP support required */
   CpuLWP,
-  /* MOVBE Instuction support required */
+  /* BMI support required */
+  CpuBMI,
+  /* TBM support required */
+  CpuTBM,
+  /* MOVBE Instruction support required */
   CpuMovbe,
   /* EPT Instructions required */
   CpuEPT,
-  /* RDTSCP Instuction support required */
+  /* RDTSCP Instruction support required */
   CpuRdtscp,
   /* FSGSBASE Instructions required */
   CpuFSGSBase,
@@ -120,6 +130,12 @@ enum
   CpuRdRnd,
   /* F16C Instructions required */
   CpuF16C,
+  /* Intel BMI2 support required */
+  CpuBMI2,
+  /* LZCNT support required */
+  CpuLZCNT,
+  /* INVPCID Instructions required */
+  CpuINVPCID,
   /* 64bit support available, used by -march= in assembler.  */
   CpuLM,
   /* 64bit support required  */
@@ -152,6 +168,7 @@ typedef union i386_cpu_flags
       unsigned int cpui586:1;
       unsigned int cpui686:1;
       unsigned int cpuclflush:1;
+      unsigned int cpunop:1;
       unsigned int cpusyscall:1;
       unsigned int cpu8087:1;
       unsigned int cpu287:1;
@@ -174,7 +191,9 @@ typedef union i386_cpu_flags
       unsigned int cpusse4_1:1;
       unsigned int cpusse4_2:1;
       unsigned int cpuavx:1;
+      unsigned int cpuavx2:1;
       unsigned int cpul1om:1;
+      unsigned int cpuk1om:1;
       unsigned int cpuxsave:1;
       unsigned int cpuxsaveopt:1;
       unsigned int cpuaes:1;
@@ -183,12 +202,17 @@ typedef union i386_cpu_flags
       unsigned int cpufma4:1;
       unsigned int cpuxop:1;
       unsigned int cpulwp:1;
+      unsigned int cpubmi:1;
+      unsigned int cputbm:1;
       unsigned int cpumovbe:1;
       unsigned int cpuept:1;
       unsigned int cpurdtscp:1;
       unsigned int cpufsgsbase:1;
       unsigned int cpurdrnd:1;
       unsigned int cpuf16c:1;
+      unsigned int cpubmi2:1;
+      unsigned int cpulzcnt:1;
+      unsigned int cpuinvpcid:1;
       unsigned int cpulm:1;
       unsigned int cpu64:1;
       unsigned int cpuno64:1;
@@ -234,6 +258,8 @@ enum
   Size32,
   /* needs size prefix if in 64-bit mode */
   Size64,
+  /* check register size.  */
+  CheckRegSize,
   /* instruction ignores operand size prefix and in Intel mode ignores
      mnemonic size suffix check.  */
   IgnoreSize,
@@ -296,9 +322,12 @@ enum
 	VEX.DDS.  The second register operand is encoded in VEX.vvvv 
 	where the content of first source register will be overwritten
 	by the result.
-	For assembler, there are no difference between VEX.NDS and
-	VEX.DDS.
-     2. VEX.NDD.  Register destination is encoded in VEX.vvvv.
+	VEX.NDD2.  The second destination register operand is encoded in
+	VEX.vvvv for instructions with 2 destination register operands.
+	For assembler, there are no difference between VEX.NDS, VEX.DDS
+	and VEX.NDD2.
+     2. VEX.NDD.  Register destination is encoded in VEX.vvvv for
+     instructions with 1 destination register operand.
      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
 	of the operands can access a memory location.
    */
@@ -339,6 +368,13 @@ enum
   VexSources,
   /* instruction has VEX 8 bit imm */
   VexImmExt,
+  /* Instruction with vector SIB byte:
+	1: 128bit vector register.
+	2: 256bit vector register.
+   */
+#define VecSIB128	1
+#define VecSIB256	2
+  VecSIB,
   /* SSE to AVX support required */
   SSE2AVX,
   /* No AVX equivalent */
@@ -372,6 +408,7 @@ typedef struct i386_opcode_modifier
   unsigned int size16:1;
   unsigned int size32:1;
   unsigned int size64:1;
+  unsigned int checkregsize:1;
   unsigned int ignoresize:1;
   unsigned int defaultsize:1;
   unsigned int no_bsuf:1;
@@ -400,6 +437,7 @@ typedef struct i386_opcode_modifier
   unsigned int vexopcode:3;
   unsigned int vexsources:2;
   unsigned int veximmext:1;
+  unsigned int vecsib:2;
   unsigned int sse2avx:1;
   unsigned int noavx:1;
   unsigned int oldgcc:1;