X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Fi386-opc.h;h=bbf2ff864a442a7721d43020c8aa4d5ed286231a;hb=475a2301db23da20a59a59814f8b1a9eebce7855;hp=90387306d57f986cb64a894932a62e1c602cfafd;hpb=d978b5be20c2584a9a4b58b1292c191a950f04e5;p=deliverable%2Fbinutils-gdb.git

diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 90387306d5..bbf2ff864a 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -1,5 +1,5 @@
 /* Declarations for Intel 80386 opcode table
-   Copyright 2007
+   Copyright 2007, 2008
    Free Software Foundation, Inc.
 
    This file is part of the GNU opcodes library.
@@ -50,10 +50,8 @@
 #define CpuK8		(CpuK6 + 1)
 /* MMX support required */
 #define CpuMMX		(CpuK8 + 1)
-/* extended MMX support (with SSE or 3DNow!Ext) required */
-#define CpuMMX2		(CpuMMX + 1)
 /* SSE support required */
-#define CpuSSE		(CpuMMX2 + 1)
+#define CpuSSE		(CpuMMX + 1)
 /* SSE2 support required */
 #define CpuSSE2		(CpuSSE + 1)
 /* 3dnow! support required */
@@ -82,10 +80,10 @@
 #define CpuSSE4_2	(CpuSSE4_1 + 1)
 /* SSE5 support required */
 #define CpuSSE5		(CpuSSE4_2 + 1)
-/* SSE4.1 or SSE5 support required */
-#define CpuSSE4_1_Or_5	(CpuSSE5 + 1)
+/* Xsave/xrstor New Instuctions support required */
+#define CpuXsave	(CpuSSE5 + 1)
 /* 64bit support available, used by -march= in assembler.  */
-#define CpuLM		(CpuSSE4_1_Or_5 + 1)
+#define CpuLM		(CpuXsave + 1)
 /* 64bit support required  */
 #define Cpu64		(CpuLM + 1)
 /* Not supported in the 64bit mode  */
@@ -118,7 +116,6 @@ typedef union i386_cpu_flags
       unsigned int cpuk6:1;
       unsigned int cpuk8:1;
       unsigned int cpummx:1;
-      unsigned int cpummx2:1;
       unsigned int cpusse:1;
       unsigned int cpusse2:1;
       unsigned int cpua3dnow:1;
@@ -134,7 +131,7 @@ typedef union i386_cpu_flags
       unsigned int cpusse4_1:1;
       unsigned int cpusse4_2:1;
       unsigned int cpusse5:1;
-      unsigned int cpusse4_1_or_5:1;
+      unsigned int cpuxsave:1;
       unsigned int cpulm:1;
       unsigned int cpu64:1;
       unsigned int cpuno64:1;
@@ -175,7 +172,8 @@ typedef union i386_cpu_flags
 #define Size32			(Size16 + 1)
 /* needs size prefix if in 64-bit mode */
 #define Size64			(Size32 + 1)
-/* instruction ignores operand size prefix and mnemonic size suffix */
+/* instruction ignores operand size prefix and in Intel mode ignores
+   mnemonic size suffix check.  */
 #define IgnoreSize		(Size64 + 1)
 /* default insn size depends on mode */
 #define DefaultSize		(IgnoreSize + 1)
@@ -191,23 +189,8 @@ typedef union i386_cpu_flags
 #define No_qSuf			(No_sSuf + 1)
 /* long double suffix on instruction illegal */
 #define No_ldSuf		(No_qSuf + 1)
-/* x suffix on instruction illegal */
-#define No_xSuf			(No_ldSuf + 1)
-/* check PTR size on instruction in Intel mode.
-   FIXME: Can it be merged with IgnoreSize? */
-#define CheckSize		(No_xSuf + 1)
-/* BYTE PTR on instruction */
-#define Byte			(CheckSize + 1)
-/* WORD PTR on instruction */
-#define Word			(Byte + 1)
-/* DWORD PTR on instruction */
-#define Dword			(Word + 1)
-/* QWORD PTR on instruction */
-#define Qword			(Dword + 1)
-/* XMMWORD PTR on instruction */
-#define Xmmword			(Qword + 1)
 /* instruction needs FWAIT */
-#define FWait			(Xmmword + 1)
+#define FWait			(No_ldSuf + 1)
 /* quick test for string instructions */
 #define IsString		(FWait + 1)
 /* fake an extra reg operand for clr, imul and special register
@@ -242,10 +225,12 @@ typedef union i386_cpu_flags
 #define OldGcc			(Drexc + 1)
 /* AT&T mnemonic.  */
 #define ATTMnemonic		(OldGcc + 1)
-/* Intel mnemonic.  */
-#define IntelMnemonic		(ATTMnemonic + 1)
+/* AT&T syntax.  */
+#define ATTSyntax		(ATTMnemonic + 1)
+/* Intel syntax.  */
+#define IntelSyntax		(ATTSyntax + 1)
 /* The last bitfield in i386_opcode_modifier.  */
-#define Opcode_Modifier_Max	IntelMnemonic
+#define Opcode_Modifier_Max	IntelSyntax
 
 typedef struct i386_opcode_modifier
 {
@@ -271,13 +256,6 @@ typedef struct i386_opcode_modifier
   unsigned int no_ssuf:1;
   unsigned int no_qsuf:1;
   unsigned int no_ldsuf:1;
-  unsigned int no_xsuf:1;
-  unsigned int checksize:1;
-  unsigned int byte:1;
-  unsigned int word:1;
-  unsigned int dword:1;
-  unsigned int qword:1;
-  unsigned int xmmword:1;
   unsigned int fwait:1;
   unsigned int isstring:1;
   unsigned int regkludge:1;
@@ -296,26 +274,40 @@ typedef struct i386_opcode_modifier
   unsigned int drexc:1;
   unsigned int oldgcc:1;
   unsigned int attmnemonic:1;
-  unsigned int intelmnemonic:1;
+  unsigned int attsyntax:1;
+  unsigned int intelsyntax:1;
 } i386_opcode_modifier;
 
 /* Position of operand_type bits.  */
 
-/* Registers  */
-
-/* 8 bit reg */
+/* 8bit register */
 #define Reg8			0
-/* 16 bit reg */
+/* 16bit register */
 #define Reg16			(Reg8 + 1)
-/* 32 bit reg */
+/* 32bit register */
 #define Reg32			(Reg16 + 1)
-/* 64 bit reg */
+/* 64bit register */
 #define Reg64			(Reg32 + 1)
-
-/* immediate */
-
+/* Floating pointer stack register */
+#define FloatReg		(Reg64 + 1)
+/* MMX register */
+#define RegMMX			(FloatReg + 1)
+/* SSE register */
+#define RegXMM			(RegMMX + 1)
+/* Control register */
+#define Control			(RegXMM + 1)
+/* Debug register */
+#define Debug			(Control + 1)
+/* Test register */
+#define Test			(Debug + 1)
+/* 2 bit segment register */
+#define SReg2			(Test + 1)
+/* 3 bit segment register */
+#define SReg3			(SReg2 + 1)
+/* 1 bit immediate */
+#define Imm1			(SReg3 + 1)
 /* 8 bit immediate */
-#define Imm8			(Reg64 + 1)
+#define Imm8			(Imm1 + 1)
 /* 8 bit immediate sign extended */
 #define Imm8S			(Imm8 + 1)
 /* 16 bit immediate */
@@ -326,20 +318,15 @@ typedef struct i386_opcode_modifier
 #define Imm32S			(Imm32 + 1)
 /* 64 bit immediate */
 #define Imm64			(Imm32S + 1)
-/* 1 bit immediate */
-#define Imm1			(Imm64 + 1)
-
-/* memory */
-
-#define BaseIndex		(Imm1 + 1)
-/* Disp8,16,32 are used in different ways, depending on the
-   instruction.  For jumps, they specify the size of the PC relative
-   displacement, for baseindex type instructions, they specify the
-   size of the offset relative to the base register, and for memory
-   offset instructions such as `mov 1234,%al' they specify the size of
-   the offset relative to the segment base.  */
+/* 8bit/16bit/32bit displacements are used in different ways,
+   depending on the instruction.  For jumps, they specify the
+   size of the PC relative displacement, for instructions with
+   memory operand, they specify the size of the offset relative
+   to the base register, and for instructions with memory offset
+   such as `mov 1234,%al' they specify the size of the offset
+   relative to the segment base.  */
 /* 8 bit displacement */
-#define Disp8			(BaseIndex + 1)
+#define Disp8			(Imm64 + 1)
 /* 16 bit displacement */
 #define Disp16			(Disp8 + 1)
 /* 32 bit displacement */
@@ -348,46 +335,49 @@ typedef struct i386_opcode_modifier
 #define Disp32S			(Disp32 + 1)
 /* 64 bit displacement */
 #define Disp64			(Disp32S + 1)
-
-/* specials */
-
-/* register to hold in/out port addr = dx */
-#define InOutPortReg		(Disp64 + 1)
-/* register to hold shift count = cl */
+/* Accumulator %al/%ax/%eax/%rax */
+#define Acc			(Disp64 + 1)
+/* Floating pointer top stack register %st(0) */
+#define FloatAcc		(Acc + 1)
+/* Register which can be used for base or index in memory operand.  */
+#define BaseIndex		(FloatAcc + 1)
+/* Register to hold in/out port addr = dx */
+#define InOutPortReg		(BaseIndex + 1)
+/* Register to hold shift count = cl */
 #define ShiftCount		(InOutPortReg + 1)
-/* Control register */
-#define Control			(ShiftCount + 1)
-/* Debug register */
-#define Debug			(Control + 1)
-/* Test register */
-#define Test			(Debug + 1)
-/* Float register */
-#define FloatReg		(Test + 1)
-/* Float stack top %st(0) */
-#define FloatAcc		(FloatReg + 1)
-/* 2 bit segment register */
-#define SReg2			(FloatAcc + 1)
-/* 3 bit segment register */
-#define SReg3			(SReg2 + 1)
-/* Accumulator %al or %ax or %eax */
-#define Acc			(SReg3 + 1)
-#define JumpAbsolute		(Acc + 1)
-/* MMX register */
-#define RegMMX			(JumpAbsolute + 1)
-/* XMM registers in PIII */
-#define RegXMM			(RegMMX + 1)
+/* Absolute address for jump.  */
+#define JumpAbsolute		(ShiftCount + 1)
 /* String insn operand with fixed es segment */
-#define EsSeg			(RegXMM + 1)
-
+#define EsSeg			(JumpAbsolute + 1)
 /* RegMem is for instructions with a modrm byte where the register
    destination operand should be encoded in the mod and regmem fields.
    Normally, it will be encoded in the reg field. We add a RegMem
    flag to the destination register operand to indicate that it should
    be encoded in the regmem field.  */
 #define RegMem			(EsSeg + 1)
+/* Memory.  */
+#define Mem			(RegMem + 1)
+/* BYTE memory. */
+#define Byte			(Mem + 1)
+/* WORD memory. 2 byte */
+#define Word			(Byte + 1)
+/* DWORD memory. 4 byte */
+#define Dword			(Word + 1)
+/* FWORD memory. 6 byte */
+#define Fword			(Dword + 1)
+/* QWORD memory. 8 byte */
+#define Qword			(Fword + 1)
+/* TBYTE memory. 10 byte */
+#define Tbyte			(Qword + 1)
+/* XMMWORD memory. */
+#define Xmmword			(Tbyte + 1)
+/* Unspecified memory size.  */
+#define Unspecified		(Xmmword + 1)
+/* Any memory size.  */
+#define Anysize			(Unspecified  + 1)
 
 /* The last bitfield in i386_operand_type.  */
-#define OTMax			RegMem
+#define OTMax			Anysize
 
 #define OTNumOfUints \
   (OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
@@ -396,9 +386,7 @@ typedef struct i386_opcode_modifier
 
 /* If you get a compiler error for zero width of the unused field,
    comment it out.  */
-#if 0
 #define OTUnused		(OTMax + 1)
-#endif
 
 typedef union i386_operand_type
 {
@@ -408,34 +396,44 @@ typedef union i386_operand_type
       unsigned int reg16:1;
       unsigned int reg32:1;
       unsigned int reg64:1;
+      unsigned int floatreg:1;
+      unsigned int regmmx:1;
+      unsigned int regxmm:1;
+      unsigned int control:1;
+      unsigned int debug:1;
+      unsigned int test:1;
+      unsigned int sreg2:1;
+      unsigned int sreg3:1;
+      unsigned int imm1:1;
       unsigned int imm8:1;
       unsigned int imm8s:1;
       unsigned int imm16:1;
       unsigned int imm32:1;
       unsigned int imm32s:1;
       unsigned int imm64:1;
-      unsigned int imm1:1;
-      unsigned int baseindex:1;
       unsigned int disp8:1;
       unsigned int disp16:1;
       unsigned int disp32:1;
       unsigned int disp32s:1;
       unsigned int disp64:1;
+      unsigned int acc:1;
+      unsigned int floatacc:1;
+      unsigned int baseindex:1;
       unsigned int inoutportreg:1;
       unsigned int shiftcount:1;
-      unsigned int control:1;
-      unsigned int debug:1;
-      unsigned int test:1;
-      unsigned int floatreg:1;
-      unsigned int floatacc:1;
-      unsigned int sreg2:1;
-      unsigned int sreg3:1;
-      unsigned int acc:1;
       unsigned int jumpabsolute:1;
-      unsigned int regmmx:1;
-      unsigned int regxmm:1;
       unsigned int esseg:1;
       unsigned int regmem:1;
+      unsigned int mem:1;
+      unsigned int byte:1;
+      unsigned int word:1;
+      unsigned int dword:1;
+      unsigned int fword:1;
+      unsigned int qword:1;
+      unsigned int tbyte:1;
+      unsigned int xmmword:1;
+      unsigned int unspecified:1;
+      unsigned int anysize:1;
 #ifdef OTUnused
       unsigned int unused:(OTNumOfBits - OTUnused);
 #endif