X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Fi386-opc.h;h=ed486a39b3fcc3ac31b6a749d32885203f2da522;hb=3d875af5759b6ac3d0a722ce8b598426c26bf46c;hp=a8f3fd2229b83ec236f6378f29d3fb4d1ee73710;hpb=f0ae4a24b0ae1649cc3a835ba0dd407c0bd8dc56;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index a8f3fd2229..ed486a39b3 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -1,6 +1,5 @@ /* Declarations for Intel 80386 opcode table - Copyright 2007, 2008, 2009 - Free Software Foundation, Inc. + Copyright (C) 2007-2015 Free Software Foundation, Inc. This file is part of the GNU opcodes library. @@ -44,9 +43,11 @@ enum Cpu586, /* i686 or better required */ Cpu686, - /* CLFLUSH Instuction support required */ + /* CLFLUSH Instruction support required */ CpuClflush, - /* SYSCALL Instuctions support required */ + /* NOP Instruction support required */ + CpuNop, + /* SYSCALL Instructions support required */ CpuSYSCALL, /* Floating point support required */ Cpu8087, @@ -90,10 +91,31 @@ enum CpuSSE4_2, /* AVX support required */ CpuAVX, + /* AVX2 support required */ + CpuAVX2, + /* Intel AVX-512 Foundation Instructions support required */ + CpuAVX512F, + /* Intel AVX-512 Conflict Detection Instructions support required */ + CpuAVX512CD, + /* Intel AVX-512 Exponential and Reciprocal Instructions support + required */ + CpuAVX512ER, + /* Intel AVX-512 Prefetch Instructions support required */ + CpuAVX512PF, + /* Intel AVX-512 VL Instructions support required. */ + CpuAVX512VL, + /* Intel AVX-512 DQ Instructions support required. */ + CpuAVX512DQ, + /* Intel AVX-512 BW Instructions support required. */ + CpuAVX512BW, /* Intel L1OM support required */ CpuL1OM, - /* Xsave/xrstor New Instuctions support required */ + /* Intel K1OM support required */ + CpuK1OM, + /* Xsave/xrstor New Instructions support required */ CpuXsave, + /* Xsaveopt New Instructions support required */ + CpuXsaveopt, /* AES support required */ CpuAES, /* PCLMUL support required */ @@ -106,14 +128,72 @@ enum CpuXOP, /* LWP support required */ CpuLWP, - /* MOVBE Instuction support required */ + /* BMI support required */ + CpuBMI, + /* TBM support required */ + CpuTBM, + /* MOVBE Instruction support required */ CpuMovbe, + /* CMPXCHG16B instruction support required. */ + CpuCX16, /* EPT Instructions required */ CpuEPT, - /* RDTSCP Instuction support required */ + /* RDTSCP Instruction support required */ CpuRdtscp, + /* FSGSBASE Instructions required */ + CpuFSGSBase, + /* RDRND Instructions required */ + CpuRdRnd, + /* F16C Instructions required */ + CpuF16C, + /* Intel BMI2 support required */ + CpuBMI2, + /* LZCNT support required */ + CpuLZCNT, + /* HLE support required */ + CpuHLE, + /* RTM support required */ + CpuRTM, + /* INVPCID Instructions required */ + CpuINVPCID, + /* VMFUNC Instruction required */ + CpuVMFUNC, + /* Intel MPX Instructions required */ + CpuMPX, /* 64bit support available, used by -march= in assembler. */ CpuLM, + /* RDRSEED instruction required. */ + CpuRDSEED, + /* Multi-presisionn add-carry instructions are required. */ + CpuADX, + /* Supports prefetchw and prefetch instructions. */ + CpuPRFCHW, + /* SMAP instructions required. */ + CpuSMAP, + /* SHA instructions required. */ + CpuSHA, + /* VREX support required */ + CpuVREX, + /* CLFLUSHOPT instruction required */ + CpuClflushOpt, + /* XSAVES/XRSTORS instruction required */ + CpuXSAVES, + /* XSAVEC instruction required */ + CpuXSAVEC, + /* PREFETCHWT1 instruction required */ + CpuPREFETCHWT1, + /* SE1 instruction required */ + CpuSE1, + /* CLWB instruction required */ + CpuCLWB, + /* PCOMMIT instruction required */ + CpuPCOMMIT, + /* Intel AVX-512 IFMA Instructions support required. */ + CpuAVX512IFMA, + /* Intel AVX-512 VBMI Instructions support required. */ + CpuAVX512VBMI, + /* Clzero instruction required */ + CpuCLZERO, /* 64bit support required */ Cpu64, /* Not supported in the 64bit mode */ @@ -144,6 +224,7 @@ typedef union i386_cpu_flags unsigned int cpui586:1; unsigned int cpui686:1; unsigned int cpuclflush:1; + unsigned int cpunop:1; unsigned int cpusyscall:1; unsigned int cpu8087:1; unsigned int cpu287:1; @@ -166,18 +247,57 @@ typedef union i386_cpu_flags unsigned int cpusse4_1:1; unsigned int cpusse4_2:1; unsigned int cpuavx:1; + unsigned int cpuavx2:1; + unsigned int cpuavx512f:1; + unsigned int cpuavx512cd:1; + unsigned int cpuavx512er:1; + unsigned int cpuavx512pf:1; + unsigned int cpuavx512vl:1; + unsigned int cpuavx512dq:1; + unsigned int cpuavx512bw:1; unsigned int cpul1om:1; + unsigned int cpuk1om:1; unsigned int cpuxsave:1; + unsigned int cpuxsaveopt:1; unsigned int cpuaes:1; unsigned int cpupclmul:1; unsigned int cpufma:1; unsigned int cpufma4:1; unsigned int cpuxop:1; unsigned int cpulwp:1; + unsigned int cpubmi:1; + unsigned int cputbm:1; unsigned int cpumovbe:1; + unsigned int cpucx16:1; unsigned int cpuept:1; unsigned int cpurdtscp:1; + unsigned int cpufsgsbase:1; + unsigned int cpurdrnd:1; + unsigned int cpuf16c:1; + unsigned int cpubmi2:1; + unsigned int cpulzcnt:1; + unsigned int cpuhle:1; + unsigned int cpurtm:1; + unsigned int cpuinvpcid:1; + unsigned int cpuvmfunc:1; + unsigned int cpumpx:1; unsigned int cpulm:1; + unsigned int cpurdseed:1; + unsigned int cpuadx:1; + unsigned int cpuprfchw:1; + unsigned int cpusmap:1; + unsigned int cpusha:1; + unsigned int cpuvrex:1; + unsigned int cpuclflushopt:1; + unsigned int cpuxsaves:1; + unsigned int cpuxsavec:1; + unsigned int cpuprefetchwt1:1; + unsigned int cpuse1:1; + unsigned int cpuclwb:1; + unsigned int cpupcommit:1; + unsigned int cpuavx512ifma:1; + unsigned int cpuavx512vbmi:1; + unsigned int cpuclzero:1; unsigned int cpu64:1; unsigned int cpuno64:1; #ifdef CpuUnused @@ -222,6 +342,8 @@ enum Size32, /* needs size prefix if in 64-bit mode */ Size64, + /* check register size. */ + CheckRegSize, /* instruction ignores operand size prefix and in Intel mode ignores mnemonic size suffix check. */ IgnoreSize, @@ -243,6 +365,8 @@ enum FWait, /* quick test for string instructions */ IsString, + /* quick test if branch instruction is MPX supported */ + BNDPrefixOk, /* quick test for lockable instructions */ IsLockable, /* fake an extra reg operand for clr, imul and special register @@ -252,8 +376,18 @@ enum FirstXmm0, /* An implicit xmm0 as the first operand */ Implicit1stXmm0, - /* BYTE is OK in Intel syntax. */ - ByteOkIntel, + /* The HLE prefix is OK: + 1. With a LOCK prefix. + 2. With or without a LOCK prefix. + 3. With a RELEASE (0xf3) prefix. + */ +#define HLEPrefixNone 0 +#define HLEPrefixLock 1 +#define HLEPrefixAny 2 +#define HLEPrefixRelease 3 + HLEPrefixOk, + /* An instruction on which a "rep" prefix is acceptable. */ + RepPrefixOk, /* Convert to DWORD */ ToDword, /* Convert to QWORD */ @@ -273,43 +407,131 @@ enum /* insn has VEX prefix: 1: 128bit VEX prefix. 2: 256bit VEX prefix. + 3: Scalar VEX prefix. */ +#define VEX128 1 +#define VEX256 2 +#define VEXScalar 3 Vex, - /* insn has VEX NDS. Register-only source is encoded in Vex prefix. - We use VexNDS on insns with VEX DDS since the register-only source - is the second source register. */ - VexNDS, - /* insn has VEX NDD. Register destination is encoded in Vex prefix. */ - VexNDD, - /* insn has VEX NDD. Register destination is encoded in Vex prefix - and one of the operands can access a memory location. */ - VexLWP, - /* insn has VEX W0. */ - VexW0, - /* insn has VEX W1. */ - VexW1, - /* insn has VEX 0x0F opcode prefix. */ - Vex0F, - /* insn has VEX 0x0F38 opcode prefix. */ - Vex0F38, - /* insn has VEX 0x0F3A opcode prefix. */ - Vex0F3A, - /* insn has XOP 0x08 opcode prefix. */ - XOP08, - /* insn has XOP 0x09 opcode prefix. */ - XOP09, - /* insn has XOP 0x0A opcode prefix. */ - XOP0A, - /* insn has VEX prefix with 2 sources. */ - Vex2Sources, - /* insn has VEX prefix with 3 sources. */ - Vex3Sources, + /* How to encode VEX.vvvv: + 0: VEX.vvvv must be 1111b. + 1: VEX.NDS. Register-only source is encoded in VEX.vvvv where + the content of source registers will be preserved. + VEX.DDS. The second register operand is encoded in VEX.vvvv + where the content of first source register will be overwritten + by the result. + VEX.NDD2. The second destination register operand is encoded in + VEX.vvvv for instructions with 2 destination register operands. + For assembler, there are no difference between VEX.NDS, VEX.DDS + and VEX.NDD2. + 2. VEX.NDD. Register destination is encoded in VEX.vvvv for + instructions with 1 destination register operand. + 3. VEX.LWP. Register destination is encoded in VEX.vvvv and one + of the operands can access a memory location. + */ +#define VEXXDS 1 +#define VEXNDD 2 +#define VEXLWP 3 + VexVVVV, + /* How the VEX.W bit is used: + 0: Set by the REX.W bit. + 1: VEX.W0. Should always be 0. + 2: VEX.W1. Should always be 1. + */ +#define VEXW0 1 +#define VEXW1 2 + VexW, + /* VEX opcode prefix: + 0: VEX 0x0F opcode prefix. + 1: VEX 0x0F38 opcode prefix. + 2: VEX 0x0F3A opcode prefix + 3: XOP 0x08 opcode prefix. + 4: XOP 0x09 opcode prefix + 5: XOP 0x0A opcode prefix. + */ +#define VEX0F 0 +#define VEX0F38 1 +#define VEX0F3A 2 +#define XOP08 3 +#define XOP09 4 +#define XOP0A 5 + VexOpcode, + /* number of VEX source operands: + 0: <= 2 source operands. + 1: 2 XOP source operands. + 2: 3 source operands. + */ +#define XOP2SOURCES 1 +#define VEX3SOURCES 2 + VexSources, /* instruction has VEX 8 bit imm */ VexImmExt, + /* Instruction with vector SIB byte: + 1: 128bit vector register. + 2: 256bit vector register. + 3: 512bit vector register. + */ +#define VecSIB128 1 +#define VecSIB256 2 +#define VecSIB512 3 + VecSIB, /* SSE to AVX support required */ SSE2AVX, /* No AVX equivalent */ NoAVX, + + /* insn has EVEX prefix: + 1: 512bit EVEX prefix. + 2: 128bit EVEX prefix. + 3: 256bit EVEX prefix. + 4: Length-ignored (LIG) EVEX prefix. + */ +#define EVEX512 1 +#define EVEX128 2 +#define EVEX256 3 +#define EVEXLIG 4 + EVex, + + /* AVX512 masking support: + 1: Zeroing-masking. + 2: Merging-masking. + 3: Both zeroing and merging masking. + */ +#define ZEROING_MASKING 1 +#define MERGING_MASKING 2 +#define BOTH_MASKING 3 + Masking, + + /* Input element size of vector insn: + 0: 32bit. + 1: 64bit. + */ + VecESize, + + /* Broadcast factor. + 0: No broadcast. + 1: 1to16 broadcast. + 2: 1to8 broadcast. + */ +#define NO_BROADCAST 0 +#define BROADCAST_1TO16 1 +#define BROADCAST_1TO8 2 +#define BROADCAST_1TO4 3 +#define BROADCAST_1TO2 4 + Broadcast, + + /* Static rounding control is supported. */ + StaticRounding, + + /* Supress All Exceptions is supported. */ + SAE, + + /* Copressed Disp8*N attribute. */ + Disp8MemShift, + + /* Default mask isn't allowed. */ + NoDefMask, + /* Compatible with old (<= 2.8.1) versions of gcc */ OldGcc, /* AT&T mnemonic. */ @@ -339,6 +561,7 @@ typedef struct i386_opcode_modifier unsigned int size16:1; unsigned int size32:1; unsigned int size64:1; + unsigned int checkregsize:1; unsigned int ignoresize:1; unsigned int defaultsize:1; unsigned int no_bsuf:1; @@ -349,11 +572,13 @@ typedef struct i386_opcode_modifier unsigned int no_ldsuf:1; unsigned int fwait:1; unsigned int isstring:1; + unsigned int bndprefixok:1; unsigned int islockable:1; unsigned int regkludge:1; unsigned int firstxmm0:1; unsigned int implicit1stxmm0:1; - unsigned int byteokintel:1; + unsigned int hleprefixok:2; + unsigned int repprefixok:1; unsigned int todword:1; unsigned int toqword:1; unsigned int addrprefixop0:1; @@ -363,22 +588,22 @@ typedef struct i386_opcode_modifier unsigned int rex64:1; unsigned int ugh:1; unsigned int vex:2; - unsigned int vexnds:1; - unsigned int vexndd:1; - unsigned int vexlwp:1; - unsigned int vexw0:1; - unsigned int vexw1:1; - unsigned int vex0f:1; - unsigned int vex0f38:1; - unsigned int vex0f3a:1; - unsigned int xop08:1; - unsigned int xop09:1; - unsigned int xop0a:1; - unsigned int vex2sources:1; - unsigned int vex3sources:1; + unsigned int vexvvvv:2; + unsigned int vexw:2; + unsigned int vexopcode:3; + unsigned int vexsources:2; unsigned int veximmext:1; + unsigned int vecsib:2; unsigned int sse2avx:1; unsigned int noavx:1; + unsigned int evex:3; + unsigned int masking:2; + unsigned int vecesize:1; + unsigned int broadcast:3; + unsigned int staticrounding:1; + unsigned int sae:1; + unsigned int disp8memshift:3; + unsigned int nodefmask:1; unsigned int oldgcc:1; unsigned int attmnemonic:1; unsigned int attsyntax:1; @@ -405,6 +630,10 @@ enum RegXMM, /* AVX registers */ RegYMM, + /* AVX512 registers */ + RegZMM, + /* Vector Mask registers */ + RegMask, /* Control register */ Control, /* Debug register */ @@ -484,11 +713,22 @@ enum Xmmword, /* YMMWORD memory. */ Ymmword, + /* ZMMWORD memory. */ + Zmmword, /* Unspecified memory size. */ Unspecified, /* Any memory size. */ Anysize, + /* Vector 4 bit immediate. */ + Vec_Imm4, + + /* Bound register. */ + RegBND, + + /* Vector 8bit displacement */ + Vec_Disp8, + /* The last bitfield in i386_operand_type. */ OTMax }; @@ -514,6 +754,8 @@ typedef union i386_operand_type unsigned int regmmx:1; unsigned int regxmm:1; unsigned int regymm:1; + unsigned int regzmm:1; + unsigned int regmask:1; unsigned int control:1; unsigned int debug:1; unsigned int test:1; @@ -548,8 +790,12 @@ typedef union i386_operand_type unsigned int tbyte:1; unsigned int xmmword:1; unsigned int ymmword:1; + unsigned int zmmword:1; unsigned int unspecified:1; unsigned int anysize:1; + unsigned int vec_imm4:1; + unsigned int regbnd:1; + unsigned int vec_disp8:1; #ifdef OTUnused unsigned int unused:(OTNumOfBits - OTUnused); #endif @@ -577,7 +823,7 @@ typedef struct insn_template /* extension_opcode is the 3 bit extension for group insns. This field is also used to store the 8-bit opcode suffix for the AMD 3DNow! instructions. - If this template has no extension opcode (the usual case) use None + If this template has no extension opcode (the usual case) use None Instructions */ unsigned int extension_opcode; #define None 0xffff /* If no extension_opcode is possible. */ @@ -611,6 +857,7 @@ typedef struct unsigned char reg_flags; #define RegRex 0x1 /* Extended register. */ #define RegRex64 0x2 /* Extended 8 bit register. */ +#define RegVRex 0x4 /* Extended vector register. */ unsigned char reg_num; #define RegRip ((unsigned char ) ~0) #define RegEip (RegRip - 1)