X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Fi386-reg.tbl;h=0c4e796db072acc2202813b928a930ecb1bdf7cf;hb=5f847646eeb0107cb8c5e44c8bca3a4c88c91673;hp=694e55fa8f5e5b2cd0376502ac14fb03b08ec54a;hpb=40b8e679e84c3c5160ffbd14fb990dd6d5fee7fb;p=deliverable%2Fbinutils-gdb.git

diff --git a/opcodes/i386-reg.tbl b/opcodes/i386-reg.tbl
index 694e55fa8f..0c4e796db0 100644
--- a/opcodes/i386-reg.tbl
+++ b/opcodes/i386-reg.tbl
@@ -1,182 +1,321 @@
 // i386 register table.
+// Copyright (C) 2007-2017 Free Software Foundation, Inc.
+//
+// This file is part of the GNU opcodes library.
+//
+// This library is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 3, or (at your option)
+// any later version.
+//
+// It is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+// or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+// License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with GAS; see the file COPYING.  If not, write to the Free
+// Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+// 02110-1301, USA.
 
 // Make %st first as we test for it.
-st, FloatReg|FloatAcc, 0, 0
+st, FloatReg|FloatAcc, 0, 0, 11, 33
 // 8 bit regs
-al, Reg8|Acc, 0, 0
-cl, Reg8|ShiftCount, 0, 1
-dl, Reg8, 0, 2
-bl, Reg8, 0, 3
-ah, Reg8, 0, 4
-ch, Reg8, 0, 5
-dh, Reg8, 0, 6
-bh, Reg8, 0, 7
-axl, Reg8|Acc, RegRex64, 0
-cxl, Reg8, RegRex64, 1
-dxl, Reg8, RegRex64, 2
-bxl, Reg8, RegRex64, 3
-spl, Reg8, RegRex64, 4
-bpl, Reg8, RegRex64, 5
-sil, Reg8, RegRex64, 6
-dil, Reg8, RegRex64, 7
-r8b, Reg8, RegRex|RegRex64, 0
-r9b, Reg8, RegRex|RegRex64, 1
-r10b, Reg8, RegRex|RegRex64, 2
-r11b, Reg8, RegRex|RegRex64, 3
-r12b, Reg8, RegRex|RegRex64, 4
-r13b, Reg8, RegRex|RegRex64, 5
-r14b, Reg8, RegRex|RegRex64, 6
-r15b, Reg8, RegRex|RegRex64, 7
+al, Reg8|Acc|Byte, 0, 0, Dw2Inval, Dw2Inval
+cl, Reg8|ShiftCount, 0, 1, Dw2Inval, Dw2Inval
+dl, Reg8, 0, 2, Dw2Inval, Dw2Inval
+bl, Reg8, 0, 3, Dw2Inval, Dw2Inval
+ah, Reg8, 0, 4, Dw2Inval, Dw2Inval
+ch, Reg8, 0, 5, Dw2Inval, Dw2Inval
+dh, Reg8, 0, 6, Dw2Inval, Dw2Inval
+bh, Reg8, 0, 7, Dw2Inval, Dw2Inval
+axl, Reg8, RegRex64, 0, Dw2Inval, Dw2Inval
+cxl, Reg8, RegRex64, 1, Dw2Inval, Dw2Inval
+dxl, Reg8, RegRex64, 2, Dw2Inval, Dw2Inval
+bxl, Reg8, RegRex64, 3, Dw2Inval, Dw2Inval
+spl, Reg8, RegRex64, 4, Dw2Inval, Dw2Inval
+bpl, Reg8, RegRex64, 5, Dw2Inval, Dw2Inval
+sil, Reg8, RegRex64, 6, Dw2Inval, Dw2Inval
+dil, Reg8, RegRex64, 7, Dw2Inval, Dw2Inval
+r8b, Reg8, RegRex|RegRex64, 0, Dw2Inval, Dw2Inval
+r9b, Reg8, RegRex|RegRex64, 1, Dw2Inval, Dw2Inval
+r10b, Reg8, RegRex|RegRex64, 2, Dw2Inval, Dw2Inval
+r11b, Reg8, RegRex|RegRex64, 3, Dw2Inval, Dw2Inval
+r12b, Reg8, RegRex|RegRex64, 4, Dw2Inval, Dw2Inval
+r13b, Reg8, RegRex|RegRex64, 5, Dw2Inval, Dw2Inval
+r14b, Reg8, RegRex|RegRex64, 6, Dw2Inval, Dw2Inval
+r15b, Reg8, RegRex|RegRex64, 7, Dw2Inval, Dw2Inval
 // 16 bit regs
-ax, Reg16|Acc, 0, 0
-cx, Reg16, 0, 1
-dx, Reg16|InOutPortReg, 0, 2
-bx, Reg16|BaseIndex, 0, 3
-sp, Reg16, 0, 4
-bp, Reg16|BaseIndex, 0, 5
-si, Reg16|BaseIndex, 0, 6
-di, Reg16|BaseIndex, 0, 7
-r8w, Reg16, RegRex, 0
-r9w, Reg16, RegRex, 1
-r10w, Reg16, RegRex, 2
-r11w, Reg16, RegRex, 3
-r12w, Reg16, RegRex, 4
-r13w, Reg16, RegRex, 5
-r14w, Reg16, RegRex, 6
-r15w, Reg16, RegRex, 7
+ax, Reg16|Acc|Word, 0, 0, Dw2Inval, Dw2Inval
+cx, Reg16, 0, 1, Dw2Inval, Dw2Inval
+dx, Reg16|InOutPortReg, 0, 2, Dw2Inval, Dw2Inval
+bx, Reg16|BaseIndex, 0, 3, Dw2Inval, Dw2Inval
+sp, Reg16, 0, 4, Dw2Inval, Dw2Inval
+bp, Reg16|BaseIndex, 0, 5, Dw2Inval, Dw2Inval
+si, Reg16|BaseIndex, 0, 6, Dw2Inval, Dw2Inval
+di, Reg16|BaseIndex, 0, 7, Dw2Inval, Dw2Inval
+r8w, Reg16, RegRex, 0, Dw2Inval, Dw2Inval
+r9w, Reg16, RegRex, 1, Dw2Inval, Dw2Inval
+r10w, Reg16, RegRex, 2, Dw2Inval, Dw2Inval
+r11w, Reg16, RegRex, 3, Dw2Inval, Dw2Inval
+r12w, Reg16, RegRex, 4, Dw2Inval, Dw2Inval
+r13w, Reg16, RegRex, 5, Dw2Inval, Dw2Inval
+r14w, Reg16, RegRex, 6, Dw2Inval, Dw2Inval
+r15w, Reg16, RegRex, 7, Dw2Inval, Dw2Inval
 // 32 bit regs
-eax, Reg32|BaseIndex|Acc, 0, 0
-ecx, Reg32|BaseIndex, 0, 1
-edx, Reg32|BaseIndex, 0, 2
-ebx, Reg32|BaseIndex, 0, 3
-esp, Reg32, 0, 4
-ebp, Reg32|BaseIndex, 0, 5
-esi, Reg32|BaseIndex, 0, 6
-edi, Reg32|BaseIndex, 0, 7
-r8d, Reg32|BaseIndex, RegRex, 0
-r9d, Reg32|BaseIndex, RegRex, 1
-r10d, Reg32|BaseIndex, RegRex, 2
-r11d, Reg32|BaseIndex, RegRex, 3
-r12d, Reg32|BaseIndex, RegRex, 4
-r13d, Reg32|BaseIndex, RegRex, 5
-r14d, Reg32|BaseIndex, RegRex, 6
-r15d, Reg32|BaseIndex, RegRex, 7
-rax, Reg64|BaseIndex|Acc, 0, 0
-rcx, Reg64|BaseIndex, 0, 1
-rdx, Reg64|BaseIndex, 0, 2
-rbx, Reg64|BaseIndex, 0, 3
-rsp, Reg64, 0, 4
-rbp, Reg64|BaseIndex, 0, 5
-rsi, Reg64|BaseIndex, 0, 6
-rdi, Reg64|BaseIndex, 0, 7
-r8, Reg64|BaseIndex, RegRex, 0
-r9, Reg64|BaseIndex, RegRex, 1
-r10, Reg64|BaseIndex, RegRex, 2
-r11, Reg64|BaseIndex, RegRex, 3
-r12, Reg64|BaseIndex, RegRex, 4
-r13, Reg64|BaseIndex, RegRex, 5
-r14, Reg64|BaseIndex, RegRex, 6
-r15, Reg64|BaseIndex, RegRex, 7
-  // Segment registers.
-es, SReg2, 0, 0
-cs, SReg2, 0, 1
-ss, SReg2, 0, 2
-ds, SReg2, 0, 3
-fs, SReg3, 0, 4
-gs, SReg3, 0, 5
+eax, Reg32|BaseIndex|Acc|Dword, 0, 0, 0, Dw2Inval
+ecx, Reg32|BaseIndex, 0, 1, 1, Dw2Inval
+edx, Reg32|BaseIndex, 0, 2, 2, Dw2Inval
+ebx, Reg32|BaseIndex, 0, 3, 3, Dw2Inval
+esp, Reg32, 0, 4, 4, Dw2Inval
+ebp, Reg32|BaseIndex, 0, 5, 5, Dw2Inval
+esi, Reg32|BaseIndex, 0, 6, 6, Dw2Inval
+edi, Reg32|BaseIndex, 0, 7, 7, Dw2Inval
+r8d, Reg32|BaseIndex, RegRex, 0, Dw2Inval, Dw2Inval
+r9d, Reg32|BaseIndex, RegRex, 1, Dw2Inval, Dw2Inval
+r10d, Reg32|BaseIndex, RegRex, 2, Dw2Inval, Dw2Inval
+r11d, Reg32|BaseIndex, RegRex, 3, Dw2Inval, Dw2Inval
+r12d, Reg32|BaseIndex, RegRex, 4, Dw2Inval, Dw2Inval
+r13d, Reg32|BaseIndex, RegRex, 5, Dw2Inval, Dw2Inval
+r14d, Reg32|BaseIndex, RegRex, 6, Dw2Inval, Dw2Inval
+r15d, Reg32|BaseIndex, RegRex, 7, Dw2Inval, Dw2Inval
+rax, Reg64|BaseIndex|Acc|Qword, 0, 0, Dw2Inval, 0
+rcx, Reg64|BaseIndex, 0, 1, Dw2Inval, 2
+rdx, Reg64|BaseIndex, 0, 2, Dw2Inval, 1
+rbx, Reg64|BaseIndex, 0, 3, Dw2Inval, 3
+rsp, Reg64, 0, 4, Dw2Inval, 7
+rbp, Reg64|BaseIndex, 0, 5, Dw2Inval, 6
+rsi, Reg64|BaseIndex, 0, 6, Dw2Inval, 4
+rdi, Reg64|BaseIndex, 0, 7, Dw2Inval, 5
+r8, Reg64|BaseIndex, RegRex, 0, Dw2Inval, 8
+r9, Reg64|BaseIndex, RegRex, 1, Dw2Inval, 9
+r10, Reg64|BaseIndex, RegRex, 2, Dw2Inval, 10
+r11, Reg64|BaseIndex, RegRex, 3, Dw2Inval, 11
+r12, Reg64|BaseIndex, RegRex, 4, Dw2Inval, 12
+r13, Reg64|BaseIndex, RegRex, 5, Dw2Inval, 13
+r14, Reg64|BaseIndex, RegRex, 6, Dw2Inval, 14
+r15, Reg64|BaseIndex, RegRex, 7, Dw2Inval, 15
+// Vector mask registers.
+k0, RegMask, 0, 0, 93, 118
+k1, RegMask, 0, 1, 94, 119
+k2, RegMask, 0, 2, 95, 120
+k3, RegMask, 0, 3, 96, 121
+k4, RegMask, 0, 4, 97, 122
+k5, RegMask, 0, 5, 98, 123
+k6, RegMask, 0, 6, 99, 124
+k7, RegMask, 0, 7, 100, 125
+// Segment registers.
+es, SReg2, 0, 0, 40, 50
+cs, SReg2, 0, 1, 41, 51
+ss, SReg2, 0, 2, 42, 52
+ds, SReg2, 0, 3, 43, 53
+fs, SReg3, 0, 4, 44, 54
+gs, SReg3, 0, 5, 45, 55
+flat, SReg3, 0, RegFlat, Dw2Inval, Dw2Inval
 // Control registers.
-cr0, Control, 0, 0
-cr1, Control, 0, 1
-cr2, Control, 0, 2
-cr3, Control, 0, 3
-cr4, Control, 0, 4
-cr5, Control, 0, 5
-cr6, Control, 0, 6
-cr7, Control, 0, 7
-cr8, Control, RegRex, 0
-cr9, Control, RegRex, 1
-cr10, Control, RegRex, 2
-cr11, Control, RegRex, 3
-cr12, Control, RegRex, 4
-cr13, Control, RegRex, 5
-cr14, Control, RegRex, 6
-cr15, Control, RegRex, 7
+cr0, Control, 0, 0, Dw2Inval, Dw2Inval
+cr1, Control, 0, 1, Dw2Inval, Dw2Inval
+cr2, Control, 0, 2, Dw2Inval, Dw2Inval
+cr3, Control, 0, 3, Dw2Inval, Dw2Inval
+cr4, Control, 0, 4, Dw2Inval, Dw2Inval
+cr5, Control, 0, 5, Dw2Inval, Dw2Inval
+cr6, Control, 0, 6, Dw2Inval, Dw2Inval
+cr7, Control, 0, 7, Dw2Inval, Dw2Inval
+cr8, Control, RegRex, 0, Dw2Inval, Dw2Inval
+cr9, Control, RegRex, 1, Dw2Inval, Dw2Inval
+cr10, Control, RegRex, 2, Dw2Inval, Dw2Inval
+cr11, Control, RegRex, 3, Dw2Inval, Dw2Inval
+cr12, Control, RegRex, 4, Dw2Inval, Dw2Inval
+cr13, Control, RegRex, 5, Dw2Inval, Dw2Inval
+cr14, Control, RegRex, 6, Dw2Inval, Dw2Inval
+cr15, Control, RegRex, 7, Dw2Inval, Dw2Inval
 // Debug registers.
-db0, Debug, 0, 0
-db1, Debug, 0, 1
-db2, Debug, 0, 2
-db3, Debug, 0, 3
-db4, Debug, 0, 4
-db5, Debug, 0, 5
-db6, Debug, 0, 6
-db7, Debug, 0, 7
-db8, Debug, RegRex, 0
-db9, Debug, RegRex, 1
-db10, Debug, RegRex, 2
-db11, Debug, RegRex, 3
-db12, Debug, RegRex, 4
-db13, Debug, RegRex, 5
-db14, Debug, RegRex, 6
-db15, Debug, RegRex, 7
-dr0, Debug, 0, 0
-dr1, Debug, 0, 1
-dr2, Debug, 0, 2
-dr3, Debug, 0, 3
-dr4, Debug, 0, 4
-dr5, Debug, 0, 5
-dr6, Debug, 0, 6
-dr7, Debug, 0, 7
-dr8, Debug, RegRex, 0
-dr9, Debug, RegRex, 1
-dr10, Debug, RegRex, 2
-dr11, Debug, RegRex, 3
-dr12, Debug, RegRex, 4
-dr13, Debug, RegRex, 5
-dr14, Debug, RegRex, 6
-dr15, Debug, RegRex, 7
+db0, Debug, 0, 0, Dw2Inval, Dw2Inval
+db1, Debug, 0, 1, Dw2Inval, Dw2Inval
+db2, Debug, 0, 2, Dw2Inval, Dw2Inval
+db3, Debug, 0, 3, Dw2Inval, Dw2Inval
+db4, Debug, 0, 4, Dw2Inval, Dw2Inval
+db5, Debug, 0, 5, Dw2Inval, Dw2Inval
+db6, Debug, 0, 6, Dw2Inval, Dw2Inval
+db7, Debug, 0, 7, Dw2Inval, Dw2Inval
+db8, Debug, RegRex, 0, Dw2Inval, Dw2Inval
+db9, Debug, RegRex, 1, Dw2Inval, Dw2Inval
+db10, Debug, RegRex, 2, Dw2Inval, Dw2Inval
+db11, Debug, RegRex, 3, Dw2Inval, Dw2Inval
+db12, Debug, RegRex, 4, Dw2Inval, Dw2Inval
+db13, Debug, RegRex, 5, Dw2Inval, Dw2Inval
+db14, Debug, RegRex, 6, Dw2Inval, Dw2Inval
+db15, Debug, RegRex, 7, Dw2Inval, Dw2Inval
+dr0, Debug, 0, 0, Dw2Inval, Dw2Inval
+dr1, Debug, 0, 1, Dw2Inval, Dw2Inval
+dr2, Debug, 0, 2, Dw2Inval, Dw2Inval
+dr3, Debug, 0, 3, Dw2Inval, Dw2Inval
+dr4, Debug, 0, 4, Dw2Inval, Dw2Inval
+dr5, Debug, 0, 5, Dw2Inval, Dw2Inval
+dr6, Debug, 0, 6, Dw2Inval, Dw2Inval
+dr7, Debug, 0, 7, Dw2Inval, Dw2Inval
+dr8, Debug, RegRex, 0, Dw2Inval, Dw2Inval
+dr9, Debug, RegRex, 1, Dw2Inval, Dw2Inval
+dr10, Debug, RegRex, 2, Dw2Inval, Dw2Inval
+dr11, Debug, RegRex, 3, Dw2Inval, Dw2Inval
+dr12, Debug, RegRex, 4, Dw2Inval, Dw2Inval
+dr13, Debug, RegRex, 5, Dw2Inval, Dw2Inval
+dr14, Debug, RegRex, 6, Dw2Inval, Dw2Inval
+dr15, Debug, RegRex, 7, Dw2Inval, Dw2Inval
 // Test registers.
-tr0, Test, 0, 0
-tr1, Test, 0, 1
-tr2, Test, 0, 2
-tr3, Test, 0, 3
-tr4, Test, 0, 4
-tr5, Test, 0, 5
-tr6, Test, 0, 6
-tr7, Test, 0, 7
+tr0, Test, 0, 0, Dw2Inval, Dw2Inval
+tr1, Test, 0, 1, Dw2Inval, Dw2Inval
+tr2, Test, 0, 2, Dw2Inval, Dw2Inval
+tr3, Test, 0, 3, Dw2Inval, Dw2Inval
+tr4, Test, 0, 4, Dw2Inval, Dw2Inval
+tr5, Test, 0, 5, Dw2Inval, Dw2Inval
+tr6, Test, 0, 6, Dw2Inval, Dw2Inval
+tr7, Test, 0, 7, Dw2Inval, Dw2Inval
 // MMX and simd registers.
-mm0, RegMMX, 0, 0
-mm1, RegMMX, 0, 1
-mm2, RegMMX, 0, 2
-mm3, RegMMX, 0, 3
-mm4, RegMMX, 0, 4
-mm5, RegMMX, 0, 5
-mm6, RegMMX, 0, 6
-mm7, RegMMX, 0, 7
-xmm0, RegXMM, 0, 0
-xmm1, RegXMM, 0, 1
-xmm2, RegXMM, 0, 2
-xmm3, RegXMM, 0, 3
-xmm4, RegXMM, 0, 4
-xmm5, RegXMM, 0, 5
-xmm6, RegXMM, 0, 6
-xmm7, RegXMM, 0, 7
-xmm8, RegXMM, RegRex, 0
-xmm9, RegXMM, RegRex, 1
-xmm10, RegXMM, RegRex, 2
-xmm11, RegXMM, RegRex, 3
-xmm12, RegXMM, RegRex, 4
-xmm13, RegXMM, RegRex, 5
-xmm14, RegXMM, RegRex, 6
-xmm15, RegXMM, RegRex, 7
-// No type will make this register rejected for all purposes except
-// for addressing.  This saves creating one extra type for RIP.
-rip, BaseIndex, 0, 0
+mm0, RegMMX, 0, 0, 29, 41
+mm1, RegMMX, 0, 1, 30, 42
+mm2, RegMMX, 0, 2, 31, 43
+mm3, RegMMX, 0, 3, 32, 44
+mm4, RegMMX, 0, 4, 33, 45
+mm5, RegMMX, 0, 5, 34, 46
+mm6, RegMMX, 0, 6, 35, 47
+mm7, RegMMX, 0, 7, 36, 48
+xmm0, RegXMM, 0, 0, 21, 17
+xmm1, RegXMM, 0, 1, 22, 18
+xmm2, RegXMM, 0, 2, 23, 19
+xmm3, RegXMM, 0, 3, 24, 20
+xmm4, RegXMM, 0, 4, 25, 21
+xmm5, RegXMM, 0, 5, 26, 22
+xmm6, RegXMM, 0, 6, 27, 23
+xmm7, RegXMM, 0, 7, 28, 24
+xmm8, RegXMM, RegRex, 0, Dw2Inval, 25
+xmm9, RegXMM, RegRex, 1, Dw2Inval, 26
+xmm10, RegXMM, RegRex, 2, Dw2Inval, 27
+xmm11, RegXMM, RegRex, 3, Dw2Inval, 28
+xmm12, RegXMM, RegRex, 4, Dw2Inval, 29
+xmm13, RegXMM, RegRex, 5, Dw2Inval, 30
+xmm14, RegXMM, RegRex, 6, Dw2Inval, 31
+xmm15, RegXMM, RegRex, 7, Dw2Inval, 32
+xmm16, RegXMM, RegVRex, 0, Dw2Inval, 67
+xmm17, RegXMM, RegVRex, 1, Dw2Inval, 68
+xmm18, RegXMM, RegVRex, 2, Dw2Inval, 69
+xmm19, RegXMM, RegVRex, 3, Dw2Inval, 70
+xmm20, RegXMM, RegVRex, 4, Dw2Inval, 71
+xmm21, RegXMM, RegVRex, 5, Dw2Inval, 72
+xmm22, RegXMM, RegVRex, 6, Dw2Inval, 73
+xmm23, RegXMM, RegVRex, 7, Dw2Inval, 74
+xmm24, RegXMM, RegVRex|RegRex, 0, Dw2Inval, 75
+xmm25, RegXMM, RegVRex|RegRex, 1, Dw2Inval, 76
+xmm26, RegXMM, RegVRex|RegRex, 2, Dw2Inval, 77
+xmm27, RegXMM, RegVRex|RegRex, 3, Dw2Inval, 78
+xmm28, RegXMM, RegVRex|RegRex, 4, Dw2Inval, 79
+xmm29, RegXMM, RegVRex|RegRex, 5, Dw2Inval, 80
+xmm30, RegXMM, RegVRex|RegRex, 6, Dw2Inval, 81
+xmm31, RegXMM, RegVRex|RegRex, 7, Dw2Inval, 82
+// AVX registers.
+ymm0, RegYMM, 0, 0, Dw2Inval, Dw2Inval
+ymm1, RegYMM, 0, 1, Dw2Inval, Dw2Inval
+ymm2, RegYMM, 0, 2, Dw2Inval, Dw2Inval
+ymm3, RegYMM, 0, 3, Dw2Inval, Dw2Inval
+ymm4, RegYMM, 0, 4, Dw2Inval, Dw2Inval
+ymm5, RegYMM, 0, 5, Dw2Inval, Dw2Inval
+ymm6, RegYMM, 0, 6, Dw2Inval, Dw2Inval
+ymm7, RegYMM, 0, 7, Dw2Inval, Dw2Inval
+ymm8, RegYMM, RegRex, 0, Dw2Inval, Dw2Inval
+ymm9, RegYMM, RegRex, 1, Dw2Inval, Dw2Inval
+ymm10, RegYMM, RegRex, 2, Dw2Inval, Dw2Inval
+ymm11, RegYMM, RegRex, 3, Dw2Inval, Dw2Inval
+ymm12, RegYMM, RegRex, 4, Dw2Inval, Dw2Inval
+ymm13, RegYMM, RegRex, 5, Dw2Inval, Dw2Inval
+ymm14, RegYMM, RegRex, 6, Dw2Inval, Dw2Inval
+ymm15, RegYMM, RegRex, 7, Dw2Inval, Dw2Inval
+ymm16, RegYMM, RegVRex, 0, Dw2Inval, Dw2Inval
+ymm17, RegYMM, RegVRex, 1, Dw2Inval, Dw2Inval
+ymm18, RegYMM, RegVRex, 2, Dw2Inval, Dw2Inval
+ymm19, RegYMM, RegVRex, 3, Dw2Inval, Dw2Inval
+ymm20, RegYMM, RegVRex, 4, Dw2Inval, Dw2Inval
+ymm21, RegYMM, RegVRex, 5, Dw2Inval, Dw2Inval
+ymm22, RegYMM, RegVRex, 6, Dw2Inval, Dw2Inval
+ymm23, RegYMM, RegVRex, 7, Dw2Inval, Dw2Inval
+ymm24, RegYMM, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval
+ymm25, RegYMM, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval
+ymm26, RegYMM, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval
+ymm27, RegYMM, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval
+ymm28, RegYMM, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval
+ymm29, RegYMM, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval
+ymm30, RegYMM, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval
+ymm31, RegYMM, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval
+// AVX512 registers.
+zmm0, RegZMM, 0, 0, Dw2Inval, Dw2Inval
+zmm1, RegZMM, 0, 1, Dw2Inval, Dw2Inval
+zmm2, RegZMM, 0, 2, Dw2Inval, Dw2Inval
+zmm3, RegZMM, 0, 3, Dw2Inval, Dw2Inval
+zmm4, RegZMM, 0, 4, Dw2Inval, Dw2Inval
+zmm5, RegZMM, 0, 5, Dw2Inval, Dw2Inval
+zmm6, RegZMM, 0, 6, Dw2Inval, Dw2Inval
+zmm7, RegZMM, 0, 7, Dw2Inval, Dw2Inval
+zmm8, RegZMM, RegRex, 0, Dw2Inval, Dw2Inval
+zmm9, RegZMM, RegRex, 1, Dw2Inval, Dw2Inval
+zmm10, RegZMM, RegRex, 2, Dw2Inval, Dw2Inval
+zmm11, RegZMM, RegRex, 3, Dw2Inval, Dw2Inval
+zmm12, RegZMM, RegRex, 4, Dw2Inval, Dw2Inval
+zmm13, RegZMM, RegRex, 5, Dw2Inval, Dw2Inval
+zmm14, RegZMM, RegRex, 6, Dw2Inval, Dw2Inval
+zmm15, RegZMM, RegRex, 7, Dw2Inval, Dw2Inval
+zmm16, RegZMM, RegVRex, 0, Dw2Inval, Dw2Inval
+zmm17, RegZMM, RegVRex, 1, Dw2Inval, Dw2Inval
+zmm18, RegZMM, RegVRex, 2, Dw2Inval, Dw2Inval
+zmm19, RegZMM, RegVRex, 3, Dw2Inval, Dw2Inval
+zmm20, RegZMM, RegVRex, 4, Dw2Inval, Dw2Inval
+zmm21, RegZMM, RegVRex, 5, Dw2Inval, Dw2Inval
+zmm22, RegZMM, RegVRex, 6, Dw2Inval, Dw2Inval
+zmm23, RegZMM, RegVRex, 7, Dw2Inval, Dw2Inval
+zmm24, RegZMM, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval
+zmm25, RegZMM, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval
+zmm26, RegZMM, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval
+zmm27, RegZMM, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval
+zmm28, RegZMM, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval
+zmm29, RegZMM, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval
+zmm30, RegZMM, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval
+zmm31, RegZMM, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval
+// Bound registers for MPX
+bnd0, RegBND, 0, 0, Dw2Inval, Dw2Inval
+bnd1, RegBND, 0, 1, Dw2Inval, Dw2Inval
+bnd2, RegBND, 0, 2, Dw2Inval, Dw2Inval
+bnd3, RegBND, 0, 3, Dw2Inval, Dw2Inval
+// No type will make these registers rejected for all purposes except
+// for addressing.  This saves creating one extra type for RIP/EIP.
+rip, BaseIndex, RegRex64, RegRip, Dw2Inval, 16
+eip, BaseIndex, RegRex64, RegEip, 8, Dw2Inval
+// No type will make these registers rejected for all purposes except
+// for addressing.
+riz, BaseIndex, RegRex64, RegRiz, Dw2Inval, Dw2Inval
+eiz, BaseIndex, 0, RegEiz, Dw2Inval, Dw2Inval
 // fp regs.
-st(0), FloatReg|FloatAcc, 0, 0
-st(1), FloatReg, 0, 1
-st(2), FloatReg, 0, 2
-st(3), FloatReg, 0, 3
-st(4), FloatReg, 0, 4
-st(5), FloatReg, 0, 5
-st(6), FloatReg, 0, 6
-st(7), FloatReg, 0, 7
+st(0), FloatReg|FloatAcc, 0, 0, 11, 33
+st(1), FloatReg, 0, 1, 12, 34
+st(2), FloatReg, 0, 2, 13, 35
+st(3), FloatReg, 0, 3, 14, 36
+st(4), FloatReg, 0, 4, 15, 37
+st(5), FloatReg, 0, 5, 16, 38
+st(6), FloatReg, 0, 6, 17, 39
+st(7), FloatReg, 0, 7, 18, 40
+// Pseudo-register names only used in .cfi_* directives
+eflags, 0, 0, 0, 9, 49
+rflags, 0, 0, 0, Dw2Inval, 49
+fs.base, 0, 0, 0, Dw2Inval, 58
+gs.base, 0, 0, 0, Dw2Inval, 59
+tr, 0, 0, 0, 48, 62
+ldtr, 0, 0, 0, 49, 63
+// st0...7 for backward compatibility
+st0, 0, 0, 0, 11, 33
+st1, 0, 0, 1, 12, 34
+st2, 0, 0, 2, 13, 35
+st3, 0, 0, 3, 14, 36
+st4, 0, 0, 4, 15, 37
+st5, 0, 0, 5, 16, 38
+st6, 0, 0, 6, 17, 39
+st7, 0, 0, 7, 18, 40
+fcw, 0, 0, 0, 37, 65
+fsw, 0, 0, 0, 38, 66
+mxcsr, 0, 0, 0, 39, 64