X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Flm32-desc.c;h=7470c3f9f1ba1dfd63a70030465c764a4f6c0eb7;hb=50d036364fb2a71b3ac9a0b0cdbe58296832a1b2;hp=1a2bd28af4ac6b96a8b7ecca750bd1b7e0da1491;hpb=87337981d937b6b00c55827ea15438e19c518884;p=deliverable%2Fbinutils-gdb.git

diff --git a/opcodes/lm32-desc.c b/opcodes/lm32-desc.c
index 1a2bd28af4..7470c3f9f1 100644
--- a/opcodes/lm32-desc.c
+++ b/opcodes/lm32-desc.c
@@ -1,8 +1,9 @@
+/* DO NOT EDIT!  -*- buffer-read-only: t -*- vi:set ro:  */
 /* CPU data for lm32.
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996-2009 Free Software Foundation, Inc.
+Copyright (C) 1996-2020 Free Software Foundation, Inc.
 
 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
 
@@ -185,6 +186,7 @@ static CGEN_KEYWORD_ENTRY lm32_cgen_opval_h_csr_entries[] =
   { "EBA", 7, {0, {{{0, 0}}}}, 0, 0 },
   { "DC", 8, {0, {{{0, 0}}}}, 0, 0 },
   { "DEBA", 9, {0, {{{0, 0}}}}, 0, 0 },
+  { "CFG2", 10, {0, {{{0, 0}}}}, 0, 0 },
   { "JTX", 14, {0, {{{0, 0}}}}, 0, 0 },
   { "JRX", 15, {0, {{{0, 0}}}}, 0, 0 },
   { "BP0", 16, {0, {{{0, 0}}}}, 0, 0 },
@@ -194,24 +196,24 @@ static CGEN_KEYWORD_ENTRY lm32_cgen_opval_h_csr_entries[] =
   { "WP0", 24, {0, {{{0, 0}}}}, 0, 0 },
   { "WP1", 25, {0, {{{0, 0}}}}, 0, 0 },
   { "WP2", 26, {0, {{{0, 0}}}}, 0, 0 },
-  { "WP3", 27, {0, {{{0, 0}}}}, 0, 0 }
+  { "WP3", 27, {0, {{{0, 0}}}}, 0, 0 },
+  { "PSW", 29, {0, {{{0, 0}}}}, 0, 0 },
+  { "TLBVADDR", 30, {0, {{{0, 0}}}}, 0, 0 },
+  { "TLBPADDR", 31, {0, {{{0, 0}}}}, 0, 0 },
+  { "TLBBADVADDR", 31, {0, {{{0, 0}}}}, 0, 0 }
 };
 
 CGEN_KEYWORD lm32_cgen_opval_h_csr =
 {
   & lm32_cgen_opval_h_csr_entries[0],
-  20,
+  25,
   0, 0, 0, 0, ""
 };
 
 
 /* The hardware table.  */
 
-#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 #define A(a) (1 << CGEN_HW_##a)
-#else
-#define A(a) (1 << CGEN_HW_/**/a)
-#endif
 
 const CGEN_HW_ENTRY lm32_cgen_hw_table[] =
 {
@@ -231,11 +233,7 @@ const CGEN_HW_ENTRY lm32_cgen_hw_table[] =
 
 /* The instruction field table.  */
 
-#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 #define A(a) (1 << CGEN_IFLD_##a)
-#else
-#define A(a) (1 << CGEN_IFLD_/**/a)
-#endif
 
 const CGEN_IFLD lm32_cgen_ifld_table[] =
 {
@@ -270,90 +268,82 @@ const CGEN_IFLD lm32_cgen_ifld_table[] =
 
 /* The operand table.  */
 
-#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 #define A(a) (1 << CGEN_OPERAND_##a)
-#else
-#define A(a) (1 << CGEN_OPERAND_/**/a)
-#endif
-#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 #define OPERAND(op) LM32_OPERAND_##op
-#else
-#define OPERAND(op) LM32_OPERAND_/**/op
-#endif
 
 const CGEN_OPERAND lm32_cgen_operand_table[] =
 {
 /* pc: program counter */
   { "pc", LM32_OPERAND_PC, HW_H_PC, 0, 0,
-    { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_NIL] } }, 
+    { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_NIL] } },
     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* r0: register 0 */
   { "r0", LM32_OPERAND_R0, HW_H_GR, 25, 5,
-    { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_R0] } }, 
+    { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_R0] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* r1: register 1 */
   { "r1", LM32_OPERAND_R1, HW_H_GR, 20, 5,
-    { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_R1] } }, 
+    { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_R1] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* r2: register 2 */
   { "r2", LM32_OPERAND_R2, HW_H_GR, 15, 5,
-    { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_R2] } }, 
+    { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_R2] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* shift: shift amout */
   { "shift", LM32_OPERAND_SHIFT, HW_H_UINT, 4, 5,
-    { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_SHIFT] } }, 
+    { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_SHIFT] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* imm: signed immediate */
   { "imm", LM32_OPERAND_IMM, HW_H_SINT, 15, 16,
-    { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_IMM] } }, 
+    { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_IMM] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* uimm: unsigned immediate */
   { "uimm", LM32_OPERAND_UIMM, HW_H_UINT, 15, 16,
-    { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_UIMM] } }, 
+    { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_UIMM] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* branch: branch offset */
   { "branch", LM32_OPERAND_BRANCH, HW_H_IADDR, 15, 16,
-    { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_BRANCH] } }, 
+    { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_BRANCH] } },
     { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 /* call: call offset */
   { "call", LM32_OPERAND_CALL, HW_H_IADDR, 25, 26,
-    { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_CALL] } }, 
+    { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_CALL] } },
     { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 /* csr: csr */
   { "csr", LM32_OPERAND_CSR, HW_H_CSR, 25, 5,
-    { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_CSR] } }, 
+    { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_CSR] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* user: user */
   { "user", LM32_OPERAND_USER, HW_H_UINT, 10, 11,
-    { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_USER] } }, 
+    { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_USER] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* exception: exception */
   { "exception", LM32_OPERAND_EXCEPTION, HW_H_UINT, 25, 26,
-    { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_EXCEPTION] } }, 
+    { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_EXCEPTION] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* hi16: high 16-bit immediate */
   { "hi16", LM32_OPERAND_HI16, HW_H_UINT, 15, 16,
-    { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_UIMM] } }, 
+    { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_UIMM] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* lo16: low 16-bit immediate */
   { "lo16", LM32_OPERAND_LO16, HW_H_UINT, 15, 16,
-    { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_UIMM] } }, 
+    { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_UIMM] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* gp16: gp relative 16-bit immediate */
   { "gp16", LM32_OPERAND_GP16, HW_H_SINT, 15, 16,
-    { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_IMM] } }, 
+    { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_IMM] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* got16: got 16-bit immediate */
   { "got16", LM32_OPERAND_GOT16, HW_H_SINT, 15, 16,
-    { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_IMM] } }, 
+    { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_IMM] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* gotoffhi16: got offset high 16-bit immediate */
   { "gotoffhi16", LM32_OPERAND_GOTOFFHI16, HW_H_SINT, 15, 16,
-    { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_IMM] } }, 
+    { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_IMM] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* gotofflo16: got offset low 16-bit immediate */
   { "gotofflo16", LM32_OPERAND_GOTOFFLO16, HW_H_SINT, 15, 16,
-    { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_IMM] } }, 
+    { 0, { (const PTR) &lm32_cgen_ifld_table[LM32_F_IMM] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* sentinel */
   { 0, 0, 0, 0, 0,
@@ -367,11 +357,7 @@ const CGEN_OPERAND lm32_cgen_operand_table[] =
 /* The instruction table.  */
 
 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
-#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 #define A(a) (1 << CGEN_INSN_##a)
-#else
-#define A(a) (1 << CGEN_INSN_/**/a)
-#endif
 
 static const CGEN_IBASE lm32_cgen_insn_table[MAX_INSNS] =
 {
@@ -846,6 +832,11 @@ init_tables (void)
 {
 }
 
+#ifndef opcodes_error_handler
+#define opcodes_error_handler(...) \
+  fprintf (stderr, __VA_ARGS__); fputc ('\n', stderr)
+#endif
+
 static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
 static void build_hw_table      (CGEN_CPU_TABLE *);
 static void build_ifield_table  (CGEN_CPU_TABLE *);
@@ -864,7 +855,7 @@ lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
 	return table;
       ++table;
     }
-  abort ();
+  return NULL;
 }
 
 /* Subroutine of lm32_cgen_cpu_open to build the hardware table.  */
@@ -1006,8 +997,11 @@ lm32_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
 	{
 	  if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
 	    {
-	      fprintf (stderr, "lm32_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
-		       cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
+	      opcodes_error_handler
+		(/* xgettext:c-format */
+		 _("internal error: lm32_cgen_rebuild_tables: "
+		   "conflicting insn-chunk-bitsize values: `%d' vs. `%d'"),
+		 cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
 	      abort ();
 	    }
 
@@ -1041,11 +1035,7 @@ lm32_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
    CGEN_CPU_OPEN_END:     terminates arguments
 
    ??? Simultaneous multiple isas might not make sense, but it's not (yet)
-   precluded.
-
-   ??? We only support ISO C stdargs here, not K&R.
-   Laziness, plus experiment to see if anything requires K&R - eventually
-   K&R will no longer be supported - e.g. GDB is currently trying this.  */
+   precluded.  */
 
 CGEN_CPU_DESC
 lm32_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
@@ -1082,15 +1072,19 @@ lm32_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
 	    const CGEN_MACH *mach =
 	      lookup_mach_via_bfd_name (lm32_cgen_mach_table, name);
 
-	    machs |= 1 << mach->num;
+	    if (mach != NULL)
+	      machs |= 1 << mach->num;
 	    break;
 	  }
 	case CGEN_CPU_OPEN_ENDIAN :
 	  endian = va_arg (ap, enum cgen_endian);
 	  break;
 	default :
-	  fprintf (stderr, "lm32_cgen_cpu_open: unsupported argument `%d'\n",
-		   arg_type);
+	  opcodes_error_handler
+	    (/* xgettext:c-format */
+	     _("internal error: lm32_cgen_cpu_open: "
+	       "unsupported argument `%d'"),
+	     arg_type);
 	  abort (); /* ??? return NULL? */
 	}
       arg_type = va_arg (ap, enum cgen_cpu_open_arg);
@@ -1105,7 +1099,9 @@ lm32_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
   if (endian == CGEN_ENDIAN_UNKNOWN)
     {
       /* ??? If target has only one, could have a default.  */
-      fprintf (stderr, "lm32_cgen_cpu_open: no endianness specified\n");
+      opcodes_error_handler
+	(/* xgettext:c-format */
+	 _("internal error: lm32_cgen_cpu_open: no endianness specified"));
       abort ();
     }
 
@@ -1124,7 +1120,7 @@ lm32_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
 
   /* Default to not allowing signed overflow.  */
   cd->signed_overflow_ok_p = 0;
-  
+
   return (CGEN_CPU_DESC) cd;
 }
 
@@ -1164,20 +1160,12 @@ lm32_cgen_cpu_close (CGEN_CPU_DESC cd)
       for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
 	if (CGEN_INSN_RX (insns))
 	  regfree (CGEN_INSN_RX (insns));
-    }  
-
-  if (cd->macro_insn_table.init_entries)
-    free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
-
-  if (cd->insn_table.init_entries)
-    free ((CGEN_INSN *) cd->insn_table.init_entries);
-
-  if (cd->hw_table.entries)
-    free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
-
-  if (cd->operand_table.entries)
-    free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
+    }
 
+  free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
+  free ((CGEN_INSN *) cd->insn_table.init_entries);
+  free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
+  free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
   free (cd);
 }