X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Fm32c-dis.c;h=37a5ad18923e7645f0c1583d767cee7bcadfc275;hb=1047201fd0f402428bb3331638a198413f97f476;hp=b2ddb16b99bc3e2ae56e3380d95027fe04af6b7d;hpb=e729279b04301d65a619b1bad04b6aff686899b2;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/m32c-dis.c b/opcodes/m32c-dis.c index b2ddb16b99..37a5ad1892 100644 --- a/opcodes/m32c-dis.c +++ b/opcodes/m32c-dis.c @@ -4,20 +4,19 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. - the resultant file is machine generated, cgen-dis.in isn't - Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005 - Free Software Foundation, Inc. + Copyright (C) 1996-2016 Free Software Foundation, Inc. - This file is part of the GNU Binutils and GDB, the GNU debugger. + This file is part of libopcodes. - This program is free software; you can redistribute it and/or modify + This library is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2, or (at your option) + the Free Software Foundation; either version 3, or (at your option) any later version. - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., @@ -204,27 +203,27 @@ print_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, int length ATTRIBUTE_UNUSED, int push) { - static char * m16c_register_names [] = + static char * m16c_register_names [] = { "r0", "r1", "r2", "r3", "a0", "a1", "sb", "fb" }; disassemble_info *info = dis_info; int mask; - int index = 0; + int reg_index = 0; char* comma = ""; if (push) mask = 0x80; else mask = 1; - + if (value & mask) { (*info->fprintf_func) (info->stream, "%s", m16c_register_names [0]); comma = ","; } - for (index = 1; index <= 7; ++index) + for (reg_index = 1; reg_index <= 7; ++reg_index) { if (push) mask >>= 1; @@ -234,7 +233,7 @@ print_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, if (value & mask) { (*info->fprintf_func) (info->stream, "%s%s", comma, - m16c_register_names [index]); + m16c_register_names [reg_index]); comma = ","; } } @@ -262,6 +261,19 @@ print_push_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, print_regset (cd, dis_info, value, attrs, pc, length, PUSH); } +static void +print_signed4n (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + signed long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = dis_info; + + (*info->fprintf_func) (info->stream, "%ld", -value); +} + void m32c_cgen_print_operand (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int); @@ -308,6 +320,9 @@ m32c_cgen_print_operand (CGEN_CPU_DESC cd, case M32C_OPERAND_BIT16RN : print_keyword (cd, info, & m32c_cgen_opval_h_gr_HI, fields->f_dst16_rn, 0); break; + case M32C_OPERAND_BIT3_S : + print_normal (cd, info, fields->f_imm3_S, 0|(1<f_dst32_an_prefixed, 0); break; @@ -437,6 +452,9 @@ m32c_cgen_print_operand (CGEN_CPU_DESC cd, case M32C_OPERAND_DSP_40_U16 : print_normal (cd, info, fields->f_dsp_40_u16, 0, pc, length); break; + case M32C_OPERAND_DSP_40_U20 : + print_normal (cd, info, fields->f_dsp_40_u20, 0, pc, length); + break; case M32C_OPERAND_DSP_40_U24 : print_normal (cd, info, fields->f_dsp_40_u24, 0, pc, length); break; @@ -452,12 +470,18 @@ m32c_cgen_print_operand (CGEN_CPU_DESC cd, case M32C_OPERAND_DSP_48_U16 : print_normal (cd, info, fields->f_dsp_48_u16, 0, pc, length); break; + case M32C_OPERAND_DSP_48_U20 : + print_normal (cd, info, fields->f_dsp_48_u20, 0|(1<f_dsp_48_u24, 0|(1<f_dsp_48_u8, 0, pc, length); break; + case M32C_OPERAND_DSP_8_S24 : + print_normal (cd, info, fields->f_dsp_8_s24, 0|(1<f_dsp_8_s8, 0|(1<f_imm_12_s4, 0|(1<f_imm_12_s4, 0|(1<f_imm_13_u3, 0|(1<f_imm_8_s4, 0|(1<f_imm_8_s4, 0|(1<f_imm_12_s4, 0); break; @@ -657,13 +687,13 @@ m32c_cgen_print_operand (CGEN_CPU_DESC cd, print_address (cd, info, fields->f_lab_16_8, 0|(1<f_lab_24_8, 0|(1<f_lab_24_8, 0|(1<f_lab_32_8, 0|(1<f_lab_32_8, 0|(1<f_lab_40_8, 0|(1<f_lab_40_8, 0|(1<f_lab_5_3, 0|(1<f_lab_8_16, 0|(1<f_lab_8_24, 0|(1<f_lab_8_24, 0|(1<f_lab_8_8, 0|(1<endian == BFD_ENDIAN_BIG); else insn_value_cropped = insn_value; @@ -1168,7 +1190,7 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) typedef struct cpu_desc_list { struct cpu_desc_list *next; - int isa; + CGEN_BITSET *isa; int mach; int endian; CGEN_CPU_DESC cd; @@ -1180,11 +1202,12 @@ print_insn_m32c (bfd_vma pc, disassemble_info *info) static cpu_desc_list *cd_list = 0; cpu_desc_list *cl = 0; static CGEN_CPU_DESC cd = 0; - static int prev_isa; + static CGEN_BITSET *prev_isa; static int prev_mach; static int prev_endian; int length; - int isa,mach; + CGEN_BITSET *isa; + int mach; int endian = (info->endian == BFD_ENDIAN_BIG ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE); @@ -1197,7 +1220,7 @@ print_insn_m32c (bfd_vma pc, disassemble_info *info) arch = info->arch; if (arch == bfd_arch_unknown) arch = CGEN_BFD_ARCH; - + /* There's no standard way to compute the machine or isa number so we leave it to the target. */ #ifdef CGEN_COMPUTE_MACH @@ -1207,25 +1230,34 @@ print_insn_m32c (bfd_vma pc, disassemble_info *info) #endif #ifdef CGEN_COMPUTE_ISA - isa = CGEN_COMPUTE_ISA (info); + { + static CGEN_BITSET *permanent_isa; + + if (!permanent_isa) + permanent_isa = cgen_bitset_create (MAX_ISAS); + isa = permanent_isa; + cgen_bitset_clear (isa); + cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); + } #else isa = info->insn_sets; #endif /* If we've switched cpu's, try to find a handle we've used before */ if (cd - && (isa != prev_isa + && (cgen_bitset_compare (isa, prev_isa) != 0 || mach != prev_mach || endian != prev_endian)) { cd = 0; for (cl = cd_list; cl; cl = cl->next) { - if (cl->isa == isa && + if (cgen_bitset_compare (cl->isa, isa) == 0 && cl->mach == mach && cl->endian == endian) { cd = cl->cd; + prev_isa = cd->isas; break; } } @@ -1241,7 +1273,7 @@ print_insn_m32c (bfd_vma pc, disassemble_info *info) abort (); mach_name = arch_type->printable_name; - prev_isa = isa; + prev_isa = cgen_bitset_copy (isa); prev_mach = mach; prev_endian = endian; cd = m32c_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, @@ -1254,7 +1286,7 @@ print_insn_m32c (bfd_vma pc, disassemble_info *info) /* Save this away for future reference. */ cl = xmalloc (sizeof (struct cpu_desc_list)); cl->cd = cd; - cl->isa = isa; + cl->isa = prev_isa; cl->mach = mach; cl->endian = endian; cl->next = cd_list;