X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Fm32r-desc.c;h=4acf72044c566e8e92ab2aa29038b1e31418383a;hb=0b3301c329b795e789267f18fbe1efd45d002eb9;hp=9cb5462502e2d98f6aebad0117af5c60a4b0fd01;hpb=5b64ad42d36e6d487e1f7287d37fbc243a178e72;p=deliverable%2Fbinutils-gdb.git

diff --git a/opcodes/m32r-desc.c b/opcodes/m32r-desc.c
index 9cb5462502..4acf72044c 100644
--- a/opcodes/m32r-desc.c
+++ b/opcodes/m32r-desc.c
@@ -2,7 +2,7 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
 
 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
 
@@ -23,7 +23,6 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 */
 
 #include "sysdep.h"
-#include <ctype.h>
 #include <stdio.h>
 #include <stdarg.h>
 #include "ansidecl.h"
@@ -32,6 +31,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 #include "m32r-desc.h"
 #include "m32r-opc.h"
 #include "opintl.h"
+#include "libiberty.h"
 
 /* Attributes.  */
 
@@ -46,6 +46,7 @@ static const CGEN_ATTR_ENTRY MACH_attr[] =
 {
   { "base", MACH_BASE },
   { "m32r", MACH_M32R },
+  { "m32rx", MACH_M32RX },
   { "max", MACH_MAX },
   { 0, 0 }
 };
@@ -57,9 +58,18 @@ static const CGEN_ATTR_ENTRY ISA_attr[] =
   { 0, 0 }
 };
 
+static const CGEN_ATTR_ENTRY PIPE_attr[] =
+{
+  { "NONE", PIPE_NONE },
+  { "O", PIPE_O },
+  { "S", PIPE_S },
+  { "OS", PIPE_OS },
+  { 0, 0 }
+};
+
 const CGEN_ATTR_TABLE m32r_cgen_ifield_attr_table[] =
 {
-  { "MACH", & MACH_attr[0] },
+  { "MACH", & MACH_attr[0], & MACH_attr[0] },
   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
@@ -72,7 +82,7 @@ const CGEN_ATTR_TABLE m32r_cgen_ifield_attr_table[] =
 
 const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table[] =
 {
-  { "MACH", & MACH_attr[0] },
+  { "MACH", & MACH_attr[0], & MACH_attr[0] },
   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
   { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
   { "PC", &bool_attr[0], &bool_attr[0] },
@@ -82,7 +92,7 @@ const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table[] =
 
 const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
 {
-  { "MACH", & MACH_attr[0] },
+  { "MACH", & MACH_attr[0], & MACH_attr[0] },
   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
@@ -98,7 +108,8 @@ const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] =
 
 const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
 {
-  { "MACH", & MACH_attr[0] },
+  { "MACH", & MACH_attr[0], & MACH_attr[0] },
+  { "PIPE", & PIPE_attr[0], & PIPE_attr[0] },
   { "ALIAS", &bool_attr[0], &bool_attr[0] },
   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
   { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
@@ -110,90 +121,110 @@ const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] =
   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
   { "PBB", &bool_attr[0], &bool_attr[0] },
   { "FILL-SLOT", &bool_attr[0], &bool_attr[0] },
+  { "SPECIAL", &bool_attr[0], &bool_attr[0] },
   { 0, 0, 0 }
 };
 
 /* Instruction set variants.  */
 
 static const CGEN_ISA m32r_cgen_isa_table[] = {
-  { "m32r", 32, 32, 16, 32,  },
-  { 0 }
+  { "m32r", 32, 32, 16, 32 },
+  { 0, 0, 0, 0, 0 }
 };
 
 /* Machine variants.  */
 
 static const CGEN_MACH m32r_cgen_mach_table[] = {
-  { "m32r", "m32r", MACH_M32R },
-  { 0 }
+  { "m32r", "m32r", MACH_M32R, 0 },
+  { "m32rx", "m32rx", MACH_M32RX, 0 },
+  { 0, 0, 0, 0 }
 };
 
 static CGEN_KEYWORD_ENTRY m32r_cgen_opval_gr_names_entries[] =
 {
-  { "fp", 13 },
-  { "lr", 14 },
-  { "sp", 15 },
-  { "r0", 0 },
-  { "r1", 1 },
-  { "r2", 2 },
-  { "r3", 3 },
-  { "r4", 4 },
-  { "r5", 5 },
-  { "r6", 6 },
-  { "r7", 7 },
-  { "r8", 8 },
-  { "r9", 9 },
-  { "r10", 10 },
-  { "r11", 11 },
-  { "r12", 12 },
-  { "r13", 13 },
-  { "r14", 14 },
-  { "r15", 15 }
+  { "fp", 13, {0, {0}}, 0, 0 },
+  { "lr", 14, {0, {0}}, 0, 0 },
+  { "sp", 15, {0, {0}}, 0, 0 },
+  { "r0", 0, {0, {0}}, 0, 0 },
+  { "r1", 1, {0, {0}}, 0, 0 },
+  { "r2", 2, {0, {0}}, 0, 0 },
+  { "r3", 3, {0, {0}}, 0, 0 },
+  { "r4", 4, {0, {0}}, 0, 0 },
+  { "r5", 5, {0, {0}}, 0, 0 },
+  { "r6", 6, {0, {0}}, 0, 0 },
+  { "r7", 7, {0, {0}}, 0, 0 },
+  { "r8", 8, {0, {0}}, 0, 0 },
+  { "r9", 9, {0, {0}}, 0, 0 },
+  { "r10", 10, {0, {0}}, 0, 0 },
+  { "r11", 11, {0, {0}}, 0, 0 },
+  { "r12", 12, {0, {0}}, 0, 0 },
+  { "r13", 13, {0, {0}}, 0, 0 },
+  { "r14", 14, {0, {0}}, 0, 0 },
+  { "r15", 15, {0, {0}}, 0, 0 }
 };
 
 CGEN_KEYWORD m32r_cgen_opval_gr_names =
 {
   & m32r_cgen_opval_gr_names_entries[0],
-  19
+  19,
+  0, 0, 0, 0, ""
 };
 
 static CGEN_KEYWORD_ENTRY m32r_cgen_opval_cr_names_entries[] =
 {
-  { "psw", 0 },
-  { "cbr", 1 },
-  { "spi", 2 },
-  { "spu", 3 },
-  { "bpc", 6 },
-  { "bbpsw", 8 },
-  { "bbpc", 14 },
-  { "cr0", 0 },
-  { "cr1", 1 },
-  { "cr2", 2 },
-  { "cr3", 3 },
-  { "cr4", 4 },
-  { "cr5", 5 },
-  { "cr6", 6 },
-  { "cr7", 7 },
-  { "cr8", 8 },
-  { "cr9", 9 },
-  { "cr10", 10 },
-  { "cr11", 11 },
-  { "cr12", 12 },
-  { "cr13", 13 },
-  { "cr14", 14 },
-  { "cr15", 15 }
+  { "psw", 0, {0, {0}}, 0, 0 },
+  { "cbr", 1, {0, {0}}, 0, 0 },
+  { "spi", 2, {0, {0}}, 0, 0 },
+  { "spu", 3, {0, {0}}, 0, 0 },
+  { "bpc", 6, {0, {0}}, 0, 0 },
+  { "bbpsw", 8, {0, {0}}, 0, 0 },
+  { "bbpc", 14, {0, {0}}, 0, 0 },
+  { "cr0", 0, {0, {0}}, 0, 0 },
+  { "cr1", 1, {0, {0}}, 0, 0 },
+  { "cr2", 2, {0, {0}}, 0, 0 },
+  { "cr3", 3, {0, {0}}, 0, 0 },
+  { "cr4", 4, {0, {0}}, 0, 0 },
+  { "cr5", 5, {0, {0}}, 0, 0 },
+  { "cr6", 6, {0, {0}}, 0, 0 },
+  { "cr7", 7, {0, {0}}, 0, 0 },
+  { "cr8", 8, {0, {0}}, 0, 0 },
+  { "cr9", 9, {0, {0}}, 0, 0 },
+  { "cr10", 10, {0, {0}}, 0, 0 },
+  { "cr11", 11, {0, {0}}, 0, 0 },
+  { "cr12", 12, {0, {0}}, 0, 0 },
+  { "cr13", 13, {0, {0}}, 0, 0 },
+  { "cr14", 14, {0, {0}}, 0, 0 },
+  { "cr15", 15, {0, {0}}, 0, 0 }
 };
 
 CGEN_KEYWORD m32r_cgen_opval_cr_names =
 {
   & m32r_cgen_opval_cr_names_entries[0],
-  23
+  23,
+  0, 0, 0, 0, ""
 };
 
+static CGEN_KEYWORD_ENTRY m32r_cgen_opval_h_accums_entries[] =
+{
+  { "a0", 0, {0, {0}}, 0, 0 },
+  { "a1", 1, {0, {0}}, 0, 0 }
+};
+
+CGEN_KEYWORD m32r_cgen_opval_h_accums =
+{
+  & m32r_cgen_opval_h_accums_entries[0],
+  2,
+  0, 0, 0, 0, ""
+};
 
 
 /* The hardware table.  */
 
-#define A(a) (1 << CONCAT2 (CGEN_HW_,a))
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define A(a) (1 << CGEN_HW_##a)
+#else
+#define A(a) (1 << CGEN_HW_/**/a)
+#endif
 
 const CGEN_HW_ENTRY m32r_cgen_hw_table[] =
 {
@@ -209,23 +240,30 @@ const CGEN_HW_ENTRY m32r_cgen_hw_table[] =
   { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } },
   { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_cr_names, { 0, { (1<<MACH_BASE) } } },
   { "h-accum", HW_H_ACCUM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
+  { "h-accums", HW_H_ACCUMS, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums, { 0, { (1<<MACH_M32RX) } } },
   { "h-cond", HW_H_COND, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
   { "h-psw", HW_H_PSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
   { "h-bpsw", HW_H_BPSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
   { "h-bbpsw", HW_H_BBPSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
   { "h-lock", HW_H_LOCK, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
-  { 0 }
+  { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
 };
 
 #undef A
 
+
 /* The instruction field table.  */
 
-#define A(a) (1 << CONCAT2 (CGEN_IFLD_,a))
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define A(a) (1 << CGEN_IFLD_##a)
+#else
+#define A(a) (1 << CGEN_IFLD_/**/a)
+#endif
 
 const CGEN_IFLD m32r_cgen_ifld_table[] =
 {
   { M32R_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
+  { M32R_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
   { M32R_F_OP1, "f-op1", 0, 32, 0, 4, { 0, { (1<<MACH_BASE) } }  },
   { M32R_F_OP2, "f-op2", 0, 32, 8, 4, { 0, { (1<<MACH_BASE) } }  },
   { M32R_F_COND, "f-cond", 0, 32, 4, 4, { 0, { (1<<MACH_BASE) } }  },
@@ -242,608 +280,859 @@ const CGEN_IFLD m32r_cgen_ifld_table[] =
   { M32R_F_DISP8, "f-disp8", 0, 32, 8, 8, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
   { M32R_F_DISP16, "f-disp16", 0, 32, 16, 16, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
   { M32R_F_DISP24, "f-disp24", 0, 32, 8, 24, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
-  { 0 }
+  { M32R_F_OP23, "f-op23", 0, 32, 9, 3, { 0, { (1<<MACH_BASE) } }  },
+  { M32R_F_OP3, "f-op3", 0, 32, 14, 2, { 0, { (1<<MACH_BASE) } }  },
+  { M32R_F_ACC, "f-acc", 0, 32, 8, 1, { 0, { (1<<MACH_BASE) } }  },
+  { M32R_F_ACCS, "f-accs", 0, 32, 12, 2, { 0, { (1<<MACH_BASE) } }  },
+  { M32R_F_ACCD, "f-accd", 0, 32, 4, 2, { 0, { (1<<MACH_BASE) } }  },
+  { M32R_F_BITS67, "f-bits67", 0, 32, 6, 2, { 0, { (1<<MACH_BASE) } }  },
+  { M32R_F_BIT14, "f-bit14", 0, 32, 14, 1, { 0, { (1<<MACH_BASE) } }  },
+  { M32R_F_IMM1, "f-imm1", 0, 32, 15, 1, { 0, { (1<<MACH_BASE) } }  },
+  { 0, 0, 0, 0, 0, 0, {0, {0}} }
 };
 
 #undef A
 
+
+
+/* multi ifield declarations */
+
+
+
+/* multi ifield definitions */
+
+
 /* The operand table.  */
 
-#define A(a) (1 << CONCAT2 (CGEN_OPERAND_,a))
-#define OPERAND(op) CONCAT2 (M32R_OPERAND_,op)
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define A(a) (1 << CGEN_OPERAND_##a)
+#else
+#define A(a) (1 << CGEN_OPERAND_/**/a)
+#endif
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define OPERAND(op) M32R_OPERAND_##op
+#else
+#define OPERAND(op) M32R_OPERAND_/**/op
+#endif
 
 const CGEN_OPERAND m32r_cgen_operand_table[] =
 {
 /* pc: program counter */
   { "pc", M32R_OPERAND_PC, HW_H_PC, 0, 0,
+    { 0, &(m32r_cgen_ifld_table[0]) }, 
     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 /* sr: source register */
   { "sr", M32R_OPERAND_SR, HW_H_GR, 12, 4,
+    { 0, &(m32r_cgen_ifld_table[6]) }, 
     { 0, { (1<<MACH_BASE) } }  },
 /* dr: destination register */
   { "dr", M32R_OPERAND_DR, HW_H_GR, 4, 4,
+    { 0, &(m32r_cgen_ifld_table[5]) }, 
     { 0, { (1<<MACH_BASE) } }  },
 /* src1: source register 1 */
   { "src1", M32R_OPERAND_SRC1, HW_H_GR, 4, 4,
+    { 0, &(m32r_cgen_ifld_table[5]) }, 
     { 0, { (1<<MACH_BASE) } }  },
 /* src2: source register 2 */
   { "src2", M32R_OPERAND_SRC2, HW_H_GR, 12, 4,
+    { 0, &(m32r_cgen_ifld_table[6]) }, 
     { 0, { (1<<MACH_BASE) } }  },
 /* scr: source control register */
   { "scr", M32R_OPERAND_SCR, HW_H_CR, 12, 4,
+    { 0, &(m32r_cgen_ifld_table[6]) }, 
     { 0, { (1<<MACH_BASE) } }  },
 /* dcr: destination control register */
   { "dcr", M32R_OPERAND_DCR, HW_H_CR, 4, 4,
+    { 0, &(m32r_cgen_ifld_table[5]) }, 
     { 0, { (1<<MACH_BASE) } }  },
 /* simm8: 8 bit signed immediate */
   { "simm8", M32R_OPERAND_SIMM8, HW_H_SINT, 8, 8,
+    { 0, &(m32r_cgen_ifld_table[7]) }, 
     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 /* simm16: 16 bit signed immediate */
   { "simm16", M32R_OPERAND_SIMM16, HW_H_SINT, 16, 16,
+    { 0, &(m32r_cgen_ifld_table[8]) }, 
     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 /* uimm4: 4 bit trap number */
   { "uimm4", M32R_OPERAND_UIMM4, HW_H_UINT, 12, 4,
+    { 0, &(m32r_cgen_ifld_table[10]) }, 
     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 /* uimm5: 5 bit shift count */
   { "uimm5", M32R_OPERAND_UIMM5, HW_H_UINT, 11, 5,
+    { 0, &(m32r_cgen_ifld_table[11]) }, 
     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
 /* uimm16: 16 bit unsigned immediate */
   { "uimm16", M32R_OPERAND_UIMM16, HW_H_UINT, 16, 16,
+    { 0, &(m32r_cgen_ifld_table[12]) }, 
     { 0|A(HASH_PREFIX), { (1<<MACH_BASE) } }  },
+/* imm1: 1 bit immediate */
+  { "imm1", M32R_OPERAND_IMM1, HW_H_UINT, 15, 1,
+    { 0, &(m32r_cgen_ifld_table[25]) }, 
+    { 0|A(HASH_PREFIX), { (1<<MACH_M32RX) } }  },
+/* accd: accumulator destination register */
+  { "accd", M32R_OPERAND_ACCD, HW_H_ACCUMS, 4, 2,
+    { 0, &(m32r_cgen_ifld_table[22]) }, 
+    { 0, { (1<<MACH_M32RX) } }  },
+/* accs: accumulator source register */
+  { "accs", M32R_OPERAND_ACCS, HW_H_ACCUMS, 12, 2,
+    { 0, &(m32r_cgen_ifld_table[21]) }, 
+    { 0, { (1<<MACH_M32RX) } }  },
+/* acc: accumulator reg (d) */
+  { "acc", M32R_OPERAND_ACC, HW_H_ACCUMS, 8, 1,
+    { 0, &(m32r_cgen_ifld_table[20]) }, 
+    { 0, { (1<<MACH_M32RX) } }  },
 /* hash: # prefix */
   { "hash", M32R_OPERAND_HASH, HW_H_SINT, 0, 0,
+    { 0, 0 }, 
     { 0, { (1<<MACH_BASE) } }  },
 /* hi16: high 16 bit immediate, sign optional */
   { "hi16", M32R_OPERAND_HI16, HW_H_HI16, 16, 16,
+    { 0, &(m32r_cgen_ifld_table[14]) }, 
     { 0|A(SIGN_OPT), { (1<<MACH_BASE) } }  },
 /* slo16: 16 bit signed immediate, for low() */
   { "slo16", M32R_OPERAND_SLO16, HW_H_SLO16, 16, 16,
+    { 0, &(m32r_cgen_ifld_table[8]) }, 
     { 0, { (1<<MACH_BASE) } }  },
 /* ulo16: 16 bit unsigned immediate, for low() */
   { "ulo16", M32R_OPERAND_ULO16, HW_H_ULO16, 16, 16,
+    { 0, &(m32r_cgen_ifld_table[12]) }, 
     { 0, { (1<<MACH_BASE) } }  },
 /* uimm24: 24 bit address */
   { "uimm24", M32R_OPERAND_UIMM24, HW_H_ADDR, 8, 24,
+    { 0, &(m32r_cgen_ifld_table[13]) }, 
     { 0|A(HASH_PREFIX)|A(RELOC)|A(ABS_ADDR), { (1<<MACH_BASE) } }  },
 /* disp8: 8 bit displacement */
   { "disp8", M32R_OPERAND_DISP8, HW_H_IADDR, 8, 8,
+    { 0, &(m32r_cgen_ifld_table[15]) }, 
     { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
 /* disp16: 16 bit displacement */
   { "disp16", M32R_OPERAND_DISP16, HW_H_IADDR, 16, 16,
+    { 0, &(m32r_cgen_ifld_table[16]) }, 
     { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
 /* disp24: 24 bit displacement */
   { "disp24", M32R_OPERAND_DISP24, HW_H_IADDR, 8, 24,
+    { 0, &(m32r_cgen_ifld_table[17]) }, 
     { 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
 /* condbit: condition bit */
   { "condbit", M32R_OPERAND_CONDBIT, HW_H_COND, 0, 0,
+    { 0, 0 }, 
     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
 /* accum: accumulator */
   { "accum", M32R_OPERAND_ACCUM, HW_H_ACCUM, 0, 0,
+    { 0, 0 }, 
     { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
-  { 0 }
+  { 0, 0, 0, 0, 0, {0, {0}} }
 };
 
 #undef A
 
-#define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
-#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
 
 /* The instruction table.  */
 
+#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
+#define A(a) (1 << CGEN_INSN_##a)
+#else
+#define A(a) (1 << CGEN_INSN_/**/a)
+#endif
+
 static const CGEN_IBASE m32r_cgen_insn_table[MAX_INSNS] =
 {
   /* Special null first entry.
      A `num' value of zero is thus invalid.
      Also, the special `invalid' insn resides here.  */
-  { 0, 0, 0 },
+  { 0, 0, 0, 0, {0, {0}} },
 /* add $dr,$sr */
   {
     M32R_INSN_ADD, "add", "add", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_OS } }
   },
 /* add3 $dr,$sr,$hash$slo16 */
   {
     M32R_INSN_ADD3, "add3", "add3", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* and $dr,$sr */
   {
     M32R_INSN_AND, "and", "and", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_OS } }
   },
 /* and3 $dr,$sr,$uimm16 */
   {
     M32R_INSN_AND3, "and3", "and3", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* or $dr,$sr */
   {
     M32R_INSN_OR, "or", "or", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_OS } }
   },
 /* or3 $dr,$sr,$hash$ulo16 */
   {
     M32R_INSN_OR3, "or3", "or3", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* xor $dr,$sr */
   {
     M32R_INSN_XOR, "xor", "xor", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_OS } }
   },
 /* xor3 $dr,$sr,$uimm16 */
   {
     M32R_INSN_XOR3, "xor3", "xor3", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* addi $dr,$simm8 */
   {
     M32R_INSN_ADDI, "addi", "addi", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_OS } }
   },
 /* addv $dr,$sr */
   {
     M32R_INSN_ADDV, "addv", "addv", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_OS } }
   },
 /* addv3 $dr,$sr,$simm16 */
   {
     M32R_INSN_ADDV3, "addv3", "addv3", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* addx $dr,$sr */
   {
     M32R_INSN_ADDX, "addx", "addx", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_OS } }
   },
 /* bc.s $disp8 */
   {
     M32R_INSN_BC8, "bc8", "bc.s", 16,
-    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } }
   },
 /* bc.l $disp24 */
   {
     M32R_INSN_BC24, "bc24", "bc.l", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* beq $src1,$src2,$disp16 */
   {
     M32R_INSN_BEQ, "beq", "beq", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* beqz $src2,$disp16 */
   {
     M32R_INSN_BEQZ, "beqz", "beqz", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* bgez $src2,$disp16 */
   {
     M32R_INSN_BGEZ, "bgez", "bgez", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* bgtz $src2,$disp16 */
   {
     M32R_INSN_BGTZ, "bgtz", "bgtz", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* blez $src2,$disp16 */
   {
     M32R_INSN_BLEZ, "blez", "blez", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* bltz $src2,$disp16 */
   {
     M32R_INSN_BLTZ, "bltz", "bltz", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* bnez $src2,$disp16 */
   {
     M32R_INSN_BNEZ, "bnez", "bnez", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* bl.s $disp8 */
   {
     M32R_INSN_BL8, "bl8", "bl.s", 16,
-    { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
   },
 /* bl.l $disp24 */
   {
     M32R_INSN_BL24, "bl24", "bl.l", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
+  },
+/* bcl.s $disp8 */
+  {
+    M32R_INSN_BCL8, "bcl8", "bcl.s", 16,
+    { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
+  },
+/* bcl.l $disp24 */
+  {
+    M32R_INSN_BCL24, "bcl24", "bcl.l", 32,
+    { 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
   },
 /* bnc.s $disp8 */
   {
     M32R_INSN_BNC8, "bnc8", "bnc.s", 16,
-    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } }
   },
 /* bnc.l $disp24 */
   {
     M32R_INSN_BNC24, "bnc24", "bnc.l", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* bne $src1,$src2,$disp16 */
   {
     M32R_INSN_BNE, "bne", "bne", 32,
-    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* bra.s $disp8 */
   {
     M32R_INSN_BRA8, "bra8", "bra.s", 16,
-    { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
   },
 /* bra.l $disp24 */
   {
     M32R_INSN_BRA24, "bra24", "bra.l", 32,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
+  },
+/* bncl.s $disp8 */
+  {
+    M32R_INSN_BNCL8, "bncl8", "bncl.s", 16,
+    { 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
+  },
+/* bncl.l $disp24 */
+  {
+    M32R_INSN_BNCL24, "bncl24", "bncl.l", 32,
+    { 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
   },
 /* cmp $src1,$src2 */
   {
     M32R_INSN_CMP, "cmp", "cmp", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_OS } }
   },
 /* cmpi $src2,$simm16 */
   {
     M32R_INSN_CMPI, "cmpi", "cmpi", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* cmpu $src1,$src2 */
   {
     M32R_INSN_CMPU, "cmpu", "cmpu", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_OS } }
   },
 /* cmpui $src2,$simm16 */
   {
     M32R_INSN_CMPUI, "cmpui", "cmpui", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
+  },
+/* cmpeq $src1,$src2 */
+  {
+    M32R_INSN_CMPEQ, "cmpeq", "cmpeq", 16,
+    { 0, { (1<<MACH_M32RX), PIPE_OS } }
+  },
+/* cmpz $src2 */
+  {
+    M32R_INSN_CMPZ, "cmpz", "cmpz", 16,
+    { 0, { (1<<MACH_M32RX), PIPE_OS } }
   },
 /* div $dr,$sr */
   {
     M32R_INSN_DIV, "div", "div", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* divu $dr,$sr */
   {
     M32R_INSN_DIVU, "divu", "divu", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* rem $dr,$sr */
   {
     M32R_INSN_REM, "rem", "rem", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* remu $dr,$sr */
   {
     M32R_INSN_REMU, "remu", "remu", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
+  },
+/* divh $dr,$sr */
+  {
+    M32R_INSN_DIVH, "divh", "divh", 32,
+    { 0, { (1<<MACH_M32RX), PIPE_NONE } }
+  },
+/* jc $sr */
+  {
+    M32R_INSN_JC, "jc", "jc", 16,
+    { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
+  },
+/* jnc $sr */
+  {
+    M32R_INSN_JNC, "jnc", "jnc", 16,
+    { 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
   },
 /* jl $sr */
   {
     M32R_INSN_JL, "jl", "jl", 16,
-    { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
   },
 /* jmp $sr */
   {
     M32R_INSN_JMP, "jmp", "jmp", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
   },
 /* ld $dr,@$sr */
   {
     M32R_INSN_LD, "ld", "ld", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_O } }
   },
 /* ld $dr,@($slo16,$sr) */
   {
     M32R_INSN_LD_D, "ld-d", "ld", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* ldb $dr,@$sr */
   {
     M32R_INSN_LDB, "ldb", "ldb", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_O } }
   },
 /* ldb $dr,@($slo16,$sr) */
   {
     M32R_INSN_LDB_D, "ldb-d", "ldb", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* ldh $dr,@$sr */
   {
     M32R_INSN_LDH, "ldh", "ldh", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_O } }
   },
 /* ldh $dr,@($slo16,$sr) */
   {
     M32R_INSN_LDH_D, "ldh-d", "ldh", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* ldub $dr,@$sr */
   {
     M32R_INSN_LDUB, "ldub", "ldub", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_O } }
   },
 /* ldub $dr,@($slo16,$sr) */
   {
     M32R_INSN_LDUB_D, "ldub-d", "ldub", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* lduh $dr,@$sr */
   {
     M32R_INSN_LDUH, "lduh", "lduh", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_O } }
   },
 /* lduh $dr,@($slo16,$sr) */
   {
     M32R_INSN_LDUH_D, "lduh-d", "lduh", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* ld $dr,@$sr+ */
   {
     M32R_INSN_LD_PLUS, "ld-plus", "ld", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_O } }
   },
 /* ld24 $dr,$uimm24 */
   {
     M32R_INSN_LD24, "ld24", "ld24", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* ldi8 $dr,$simm8 */
   {
     M32R_INSN_LDI8, "ldi8", "ldi8", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_OS } }
   },
 /* ldi16 $dr,$hash$slo16 */
   {
     M32R_INSN_LDI16, "ldi16", "ldi16", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* lock $dr,@$sr */
   {
     M32R_INSN_LOCK, "lock", "lock", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_O } }
   },
 /* machi $src1,$src2 */
   {
     M32R_INSN_MACHI, "machi", "machi", 16,
-    { 0, { (1<<MACH_M32R) } }
+    { 0, { (1<<MACH_M32R), PIPE_S } }
+  },
+/* machi $src1,$src2,$acc */
+  {
+    M32R_INSN_MACHI_A, "machi-a", "machi", 16,
+    { 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* maclo $src1,$src2 */
   {
     M32R_INSN_MACLO, "maclo", "maclo", 16,
-    { 0, { (1<<MACH_M32R) } }
+    { 0, { (1<<MACH_M32R), PIPE_S } }
+  },
+/* maclo $src1,$src2,$acc */
+  {
+    M32R_INSN_MACLO_A, "maclo-a", "maclo", 16,
+    { 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* macwhi $src1,$src2 */
   {
     M32R_INSN_MACWHI, "macwhi", "macwhi", 16,
-    { 0, { (1<<MACH_M32R) } }
+    { 0, { (1<<MACH_M32R), PIPE_S } }
+  },
+/* macwhi $src1,$src2,$acc */
+  {
+    M32R_INSN_MACWHI_A, "macwhi-a", "macwhi", 16,
+    { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
   },
 /* macwlo $src1,$src2 */
   {
     M32R_INSN_MACWLO, "macwlo", "macwlo", 16,
-    { 0, { (1<<MACH_M32R) } }
+    { 0, { (1<<MACH_M32R), PIPE_S } }
+  },
+/* macwlo $src1,$src2,$acc */
+  {
+    M32R_INSN_MACWLO_A, "macwlo-a", "macwlo", 16,
+    { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
   },
 /* mul $dr,$sr */
   {
     M32R_INSN_MUL, "mul", "mul", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_S } }
   },
 /* mulhi $src1,$src2 */
   {
     M32R_INSN_MULHI, "mulhi", "mulhi", 16,
-    { 0, { (1<<MACH_M32R) } }
+    { 0, { (1<<MACH_M32R), PIPE_S } }
+  },
+/* mulhi $src1,$src2,$acc */
+  {
+    M32R_INSN_MULHI_A, "mulhi-a", "mulhi", 16,
+    { 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* mullo $src1,$src2 */
   {
     M32R_INSN_MULLO, "mullo", "mullo", 16,
-    { 0, { (1<<MACH_M32R) } }
+    { 0, { (1<<MACH_M32R), PIPE_S } }
+  },
+/* mullo $src1,$src2,$acc */
+  {
+    M32R_INSN_MULLO_A, "mullo-a", "mullo", 16,
+    { 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* mulwhi $src1,$src2 */
   {
     M32R_INSN_MULWHI, "mulwhi", "mulwhi", 16,
-    { 0, { (1<<MACH_M32R) } }
+    { 0, { (1<<MACH_M32R), PIPE_S } }
+  },
+/* mulwhi $src1,$src2,$acc */
+  {
+    M32R_INSN_MULWHI_A, "mulwhi-a", "mulwhi", 16,
+    { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
   },
 /* mulwlo $src1,$src2 */
   {
     M32R_INSN_MULWLO, "mulwlo", "mulwlo", 16,
-    { 0, { (1<<MACH_M32R) } }
+    { 0, { (1<<MACH_M32R), PIPE_S } }
+  },
+/* mulwlo $src1,$src2,$acc */
+  {
+    M32R_INSN_MULWLO_A, "mulwlo-a", "mulwlo", 16,
+    { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
   },
 /* mv $dr,$sr */
   {
     M32R_INSN_MV, "mv", "mv", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_OS } }
   },
 /* mvfachi $dr */
   {
     M32R_INSN_MVFACHI, "mvfachi", "mvfachi", 16,
-    { 0, { (1<<MACH_M32R) } }
+    { 0, { (1<<MACH_M32R), PIPE_S } }
+  },
+/* mvfachi $dr,$accs */
+  {
+    M32R_INSN_MVFACHI_A, "mvfachi-a", "mvfachi", 16,
+    { 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* mvfaclo $dr */
   {
     M32R_INSN_MVFACLO, "mvfaclo", "mvfaclo", 16,
-    { 0, { (1<<MACH_M32R) } }
+    { 0, { (1<<MACH_M32R), PIPE_S } }
+  },
+/* mvfaclo $dr,$accs */
+  {
+    M32R_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo", 16,
+    { 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* mvfacmi $dr */
   {
     M32R_INSN_MVFACMI, "mvfacmi", "mvfacmi", 16,
-    { 0, { (1<<MACH_M32R) } }
+    { 0, { (1<<MACH_M32R), PIPE_S } }
+  },
+/* mvfacmi $dr,$accs */
+  {
+    M32R_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi", 16,
+    { 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* mvfc $dr,$scr */
   {
     M32R_INSN_MVFC, "mvfc", "mvfc", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_O } }
   },
 /* mvtachi $src1 */
   {
     M32R_INSN_MVTACHI, "mvtachi", "mvtachi", 16,
-    { 0, { (1<<MACH_M32R) } }
+    { 0, { (1<<MACH_M32R), PIPE_S } }
+  },
+/* mvtachi $src1,$accs */
+  {
+    M32R_INSN_MVTACHI_A, "mvtachi-a", "mvtachi", 16,
+    { 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* mvtaclo $src1 */
   {
     M32R_INSN_MVTACLO, "mvtaclo", "mvtaclo", 16,
-    { 0, { (1<<MACH_M32R) } }
+    { 0, { (1<<MACH_M32R), PIPE_S } }
+  },
+/* mvtaclo $src1,$accs */
+  {
+    M32R_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo", 16,
+    { 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* mvtc $sr,$dcr */
   {
     M32R_INSN_MVTC, "mvtc", "mvtc", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_O } }
   },
 /* neg $dr,$sr */
   {
     M32R_INSN_NEG, "neg", "neg", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_OS } }
   },
 /* nop */
   {
     M32R_INSN_NOP, "nop", "nop", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_OS } }
   },
 /* not $dr,$sr */
   {
     M32R_INSN_NOT, "not", "not", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_OS } }
   },
 /* rac */
   {
     M32R_INSN_RAC, "rac", "rac", 16,
-    { 0, { (1<<MACH_M32R) } }
+    { 0, { (1<<MACH_M32R), PIPE_S } }
+  },
+/* rac $accd,$accs,$imm1 */
+  {
+    M32R_INSN_RAC_DSI, "rac-dsi", "rac", 16,
+    { 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* rach */
   {
     M32R_INSN_RACH, "rach", "rach", 16,
-    { 0, { (1<<MACH_M32R) } }
+    { 0, { (1<<MACH_M32R), PIPE_S } }
+  },
+/* rach $accd,$accs,$imm1 */
+  {
+    M32R_INSN_RACH_DSI, "rach-dsi", "rach", 16,
+    { 0, { (1<<MACH_M32RX), PIPE_S } }
   },
 /* rte */
   {
     M32R_INSN_RTE, "rte", "rte", 16,
-    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
   },
 /* seth $dr,$hash$hi16 */
   {
     M32R_INSN_SETH, "seth", "seth", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* sll $dr,$sr */
   {
     M32R_INSN_SLL, "sll", "sll", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_O } }
   },
 /* sll3 $dr,$sr,$simm16 */
   {
     M32R_INSN_SLL3, "sll3", "sll3", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* slli $dr,$uimm5 */
   {
     M32R_INSN_SLLI, "slli", "slli", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_O } }
   },
 /* sra $dr,$sr */
   {
     M32R_INSN_SRA, "sra", "sra", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_O } }
   },
 /* sra3 $dr,$sr,$simm16 */
   {
     M32R_INSN_SRA3, "sra3", "sra3", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* srai $dr,$uimm5 */
   {
     M32R_INSN_SRAI, "srai", "srai", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_O } }
   },
 /* srl $dr,$sr */
   {
     M32R_INSN_SRL, "srl", "srl", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_O } }
   },
 /* srl3 $dr,$sr,$simm16 */
   {
     M32R_INSN_SRL3, "srl3", "srl3", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* srli $dr,$uimm5 */
   {
     M32R_INSN_SRLI, "srli", "srli", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_O } }
   },
 /* st $src1,@$src2 */
   {
     M32R_INSN_ST, "st", "st", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_O } }
   },
 /* st $src1,@($slo16,$src2) */
   {
     M32R_INSN_ST_D, "st-d", "st", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* stb $src1,@$src2 */
   {
     M32R_INSN_STB, "stb", "stb", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_O } }
   },
 /* stb $src1,@($slo16,$src2) */
   {
     M32R_INSN_STB_D, "stb-d", "stb", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* sth $src1,@$src2 */
   {
     M32R_INSN_STH, "sth", "sth", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_O } }
   },
 /* sth $src1,@($slo16,$src2) */
   {
     M32R_INSN_STH_D, "sth-d", "sth", 32,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_NONE } }
   },
 /* st $src1,@+$src2 */
   {
     M32R_INSN_ST_PLUS, "st-plus", "st", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_O } }
   },
 /* st $src1,@-$src2 */
   {
     M32R_INSN_ST_MINUS, "st-minus", "st", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_O } }
   },
 /* sub $dr,$sr */
   {
     M32R_INSN_SUB, "sub", "sub", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_OS } }
   },
 /* subv $dr,$sr */
   {
     M32R_INSN_SUBV, "subv", "subv", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_OS } }
   },
 /* subx $dr,$sr */
   {
     M32R_INSN_SUBX, "subx", "subx", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_OS } }
   },
 /* trap $uimm4 */
   {
     M32R_INSN_TRAP, "trap", "trap", 16,
-    { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE) } }
+    { 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
   },
 /* unlock $src1,@$src2 */
   {
     M32R_INSN_UNLOCK, "unlock", "unlock", 16,
-    { 0, { (1<<MACH_BASE) } }
+    { 0, { (1<<MACH_BASE), PIPE_O } }
+  },
+/* satb $dr,$sr */
+  {
+    M32R_INSN_SATB, "satb", "satb", 32,
+    { 0, { (1<<MACH_M32RX), PIPE_NONE } }
+  },
+/* sath $dr,$sr */
+  {
+    M32R_INSN_SATH, "sath", "sath", 32,
+    { 0, { (1<<MACH_M32RX), PIPE_NONE } }
+  },
+/* sat $dr,$sr */
+  {
+    M32R_INSN_SAT, "sat", "sat", 32,
+    { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_NONE } }
+  },
+/* pcmpbz $src2 */
+  {
+    M32R_INSN_PCMPBZ, "pcmpbz", "pcmpbz", 16,
+    { 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_OS } }
+  },
+/* sadd */
+  {
+    M32R_INSN_SADD, "sadd", "sadd", 16,
+    { 0, { (1<<MACH_M32RX), PIPE_S } }
+  },
+/* macwu1 $src1,$src2 */
+  {
+    M32R_INSN_MACWU1, "macwu1", "macwu1", 16,
+    { 0, { (1<<MACH_M32RX), PIPE_S } }
+  },
+/* msblo $src1,$src2 */
+  {
+    M32R_INSN_MSBLO, "msblo", "msblo", 16,
+    { 0, { (1<<MACH_M32RX), PIPE_S } }
+  },
+/* mulwu1 $src1,$src2 */
+  {
+    M32R_INSN_MULWU1, "mulwu1", "mulwu1", 16,
+    { 0, { (1<<MACH_M32RX), PIPE_S } }
+  },
+/* maclh1 $src1,$src2 */
+  {
+    M32R_INSN_MACLH1, "maclh1", "maclh1", 16,
+    { 0, { (1<<MACH_M32RX), PIPE_S } }
+  },
+/* sc */
+  {
+    M32R_INSN_SC, "sc", "sc", 16,
+    { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } }
+  },
+/* snc */
+  {
+    M32R_INSN_SNC, "snc", "snc", 16,
+    { 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } }
   },
 };
 
-#undef A
-#undef MNEM
 #undef OP
+#undef A
 
 /* Initialize anything needed to be done once, before any cpu_open call.  */
+static void init_tables PARAMS ((void));
 
 static void
 init_tables ()
 {
 }
 
+static const CGEN_MACH * lookup_mach_via_bfd_name
+  PARAMS ((const CGEN_MACH *, const char *));
+static void build_hw_table  PARAMS ((CGEN_CPU_TABLE *));
+static void build_ifield_table  PARAMS ((CGEN_CPU_TABLE *));
+static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
+static void build_insn_table    PARAMS ((CGEN_CPU_TABLE *));
+static void m32r_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
+
 /* Subroutine of m32r_cgen_cpu_open to look up a mach via its bfd name.  */
 
 static const CGEN_MACH *
@@ -953,7 +1242,7 @@ static void
 m32r_cgen_rebuild_tables (cd)
      CGEN_CPU_TABLE *cd;
 {
-  int i,n_isas,n_machs;
+  int i;
   unsigned int isas = cd->isas;
   unsigned int machs = cd->machs;
 
@@ -970,8 +1259,8 @@ m32r_cgen_rebuild_tables (cd)
       {
 	const CGEN_ISA *isa = & m32r_cgen_isa_table[i];
 
-	/* Default insn sizes of all selected isas must be equal or we set
-	   the result to 0, meaning "unknown".  */
+	/* Default insn sizes of all selected isas must be
+	   equal or we set the result to 0, meaning "unknown".  */
 	if (cd->default_insn_bitsize == UNSET)
 	  cd->default_insn_bitsize = isa->default_insn_bitsize;
 	else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
@@ -979,8 +1268,8 @@ m32r_cgen_rebuild_tables (cd)
 	else
 	  cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
 
-	/* Base insn sizes of all selected isas must be equal or we set
-	   the result to 0, meaning "unknown".  */
+	/* Base insn sizes of all selected isas must be equal
+	   or we set the result to 0, meaning "unknown".  */
 	if (cd->base_insn_bitsize == UNSET)
 	  cd->base_insn_bitsize = isa->base_insn_bitsize;
 	else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
@@ -993,8 +1282,6 @@ m32r_cgen_rebuild_tables (cd)
 	  cd->min_insn_bitsize = isa->min_insn_bitsize;
 	if (isa->max_insn_bitsize > cd->max_insn_bitsize)
 	  cd->max_insn_bitsize = isa->max_insn_bitsize;
-
-	++n_isas;
       }
 
   /* Data derived from the mach spec.  */
@@ -1003,7 +1290,17 @@ m32r_cgen_rebuild_tables (cd)
       {
 	const CGEN_MACH *mach = & m32r_cgen_mach_table[i];
 
-	++n_machs;
+	if (mach->insn_chunk_bitsize != 0)
+	{
+	  if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
+	    {
+	      fprintf (stderr, "m32r_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
+		       cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
+	      abort ();
+	    }
+
+ 	  cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
+	}
       }
 
   /* Determine which hw elements are used by MACH.  */
@@ -1073,7 +1370,7 @@ m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
 	    const CGEN_MACH *mach =
 	      lookup_mach_via_bfd_name (m32r_cgen_mach_table, name);
 
-	    machs |= mach->num << 1;
+	    machs |= 1 << mach->num;
 	    break;
 	  }
 	case CGEN_CPU_OPEN_ENDIAN :
@@ -1116,6 +1413,9 @@ m32r_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
   cd->rebuild_tables = m32r_cgen_rebuild_tables;
   m32r_cgen_rebuild_tables (cd);
 
+  /* Default to not allowing signed overflow.  */
+  cd->signed_overflow_ok_p = 0;
+  
   return (CGEN_CPU_DESC) cd;
 }