X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Fm32r-desc.h;h=e502f4b0cab480e838714ca86855c76151c7e183;hb=1ad12f975f8a2a0ce45569ea3f550ef25705ad37;hp=13de8897b76e9d88cf9d6170255ef5f7d4344305;hpb=b3466c39bc29323e1912f5fa17c70e63af56e001;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/m32r-desc.h b/opcodes/m32r-desc.h index 13de8897b7..e502f4b0ca 100644 --- a/opcodes/m32r-desc.h +++ b/opcodes/m32r-desc.h @@ -2,7 +2,7 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. +Copyright 1996-2005 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. @@ -38,6 +38,7 @@ with this program; if not, write to the Free Software Foundation, Inc., /* Selected cpu families. */ #define HAVE_CPU_M32RBF #define HAVE_CPU_M32RXF +#define HAVE_CPU_M32R2F #define CGEN_INSN_LSB0_P 0 @@ -90,18 +91,19 @@ typedef enum gr_names { /* Enum declaration for . */ typedef enum cr_names { H_CR_PSW = 0, H_CR_CBR = 1, H_CR_SPI = 2, H_CR_SPU = 3 - , H_CR_BPC = 6, H_CR_BBPSW = 8, H_CR_BBPC = 14, H_CR_CR0 = 0 - , H_CR_CR1 = 1, H_CR_CR2 = 2, H_CR_CR3 = 3, H_CR_CR4 = 4 - , H_CR_CR5 = 5, H_CR_CR6 = 6, H_CR_CR7 = 7, H_CR_CR8 = 8 - , H_CR_CR9 = 9, H_CR_CR10 = 10, H_CR_CR11 = 11, H_CR_CR12 = 12 - , H_CR_CR13 = 13, H_CR_CR14 = 14, H_CR_CR15 = 15 + , H_CR_BPC = 6, H_CR_BBPSW = 8, H_CR_BBPC = 14, H_CR_EVB = 5 + , H_CR_CR0 = 0, H_CR_CR1 = 1, H_CR_CR2 = 2, H_CR_CR3 = 3 + , H_CR_CR4 = 4, H_CR_CR5 = 5, H_CR_CR6 = 6, H_CR_CR7 = 7 + , H_CR_CR8 = 8, H_CR_CR9 = 9, H_CR_CR10 = 10, H_CR_CR11 = 11 + , H_CR_CR12 = 12, H_CR_CR13 = 13, H_CR_CR14 = 14, H_CR_CR15 = 15 } CR_NAMES; /* Attributes. */ /* Enum declaration for machine type selection. */ typedef enum mach_attr { - MACH_BASE, MACH_M32R, MACH_M32RX, MACH_MAX + MACH_BASE, MACH_M32R, MACH_M32RX, MACH_M32R2 + , MACH_MAX } MACH_ATTR; /* Enum declaration for instruction set selection. */ @@ -112,6 +114,7 @@ typedef enum isa_attr { /* Enum declaration for parallel execution pipeline selection. */ typedef enum pipe_attr { PIPE_NONE, PIPE_O, PIPE_S, PIPE_OS + , PIPE_O_OS } PIPE_ATTR; /* Number of architecture variants. */ @@ -120,8 +123,6 @@ typedef enum pipe_attr { /* Ifield support. */ -extern const struct cgen_ifld m32r_cgen_ifld_table[]; - /* Ifield attribute indices. */ /* Enum declaration for cgen_ifld attrs. */ @@ -138,11 +139,12 @@ typedef enum cgen_ifld_attr { typedef enum ifield_type { M32R_F_NIL, M32R_F_ANYOF, M32R_F_OP1, M32R_F_OP2 , M32R_F_COND, M32R_F_R1, M32R_F_R2, M32R_F_SIMM8 - , M32R_F_SIMM16, M32R_F_SHIFT_OP2, M32R_F_UIMM4, M32R_F_UIMM5 - , M32R_F_UIMM16, M32R_F_UIMM24, M32R_F_HI16, M32R_F_DISP8 - , M32R_F_DISP16, M32R_F_DISP24, M32R_F_OP23, M32R_F_OP3 - , M32R_F_ACC, M32R_F_ACCS, M32R_F_ACCD, M32R_F_BITS67 - , M32R_F_BIT14, M32R_F_IMM1, M32R_F_MAX + , M32R_F_SIMM16, M32R_F_SHIFT_OP2, M32R_F_UIMM3, M32R_F_UIMM4 + , M32R_F_UIMM5, M32R_F_UIMM8, M32R_F_UIMM16, M32R_F_UIMM24 + , M32R_F_HI16, M32R_F_DISP8, M32R_F_DISP16, M32R_F_DISP24 + , M32R_F_OP23, M32R_F_OP3, M32R_F_ACC, M32R_F_ACCS + , M32R_F_ACCD, M32R_F_BITS67, M32R_F_BIT4, M32R_F_BIT14 + , M32R_F_IMM1, M32R_F_MAX } IFIELD_TYPE; #define MAX_IFLD ((int) M32R_F_MAX) @@ -186,15 +188,16 @@ typedef enum cgen_operand_attr { typedef enum cgen_operand_type { M32R_OPERAND_PC, M32R_OPERAND_SR, M32R_OPERAND_DR, M32R_OPERAND_SRC1 , M32R_OPERAND_SRC2, M32R_OPERAND_SCR, M32R_OPERAND_DCR, M32R_OPERAND_SIMM8 - , M32R_OPERAND_SIMM16, M32R_OPERAND_UIMM4, M32R_OPERAND_UIMM5, M32R_OPERAND_UIMM16 - , M32R_OPERAND_IMM1, M32R_OPERAND_ACCD, M32R_OPERAND_ACCS, M32R_OPERAND_ACC - , M32R_OPERAND_HASH, M32R_OPERAND_HI16, M32R_OPERAND_SLO16, M32R_OPERAND_ULO16 - , M32R_OPERAND_UIMM24, M32R_OPERAND_DISP8, M32R_OPERAND_DISP16, M32R_OPERAND_DISP24 - , M32R_OPERAND_CONDBIT, M32R_OPERAND_ACCUM, M32R_OPERAND_MAX + , M32R_OPERAND_SIMM16, M32R_OPERAND_UIMM3, M32R_OPERAND_UIMM4, M32R_OPERAND_UIMM5 + , M32R_OPERAND_UIMM8, M32R_OPERAND_UIMM16, M32R_OPERAND_IMM1, M32R_OPERAND_ACCD + , M32R_OPERAND_ACCS, M32R_OPERAND_ACC, M32R_OPERAND_HASH, M32R_OPERAND_HI16 + , M32R_OPERAND_SLO16, M32R_OPERAND_ULO16, M32R_OPERAND_UIMM24, M32R_OPERAND_DISP8 + , M32R_OPERAND_DISP16, M32R_OPERAND_DISP24, M32R_OPERAND_CONDBIT, M32R_OPERAND_ACCUM + , M32R_OPERAND_MAX } CGEN_OPERAND_TYPE; /* Number of operands types. */ -#define MAX_OPERANDS 26 +#define MAX_OPERANDS 28 /* Maximum number of operands referenced by any insn. */ #define MAX_OPERAND_INSTANCES 11 @@ -204,10 +207,10 @@ typedef enum cgen_operand_type { /* Enum declaration for cgen_insn attrs. */ typedef enum cgen_insn_attr { CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI - , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX + , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_FILL_SLOT, CGEN_INSN_SPECIAL - , CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_PIPE - , CGEN_INSN_END_NBOOLS + , CGEN_INSN_SPECIAL_M32R, CGEN_INSN_SPECIAL_FLOAT, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31 + , CGEN_INSN_MACH, CGEN_INSN_PIPE, CGEN_INSN_END_NBOOLS } CGEN_INSN_ATTR; /* Number of non-boolean elements in cgen_insn_attr. */ @@ -216,6 +219,8 @@ typedef enum cgen_insn_attr { /* cgen.h uses things we just defined. */ #include "opcode/cgen.h" +extern const struct cgen_ifld m32r_cgen_ifld_table[]; + /* Attributes. */ extern const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table[]; extern const CGEN_ATTR_TABLE m32r_cgen_ifield_attr_table[]; @@ -228,6 +233,7 @@ extern CGEN_KEYWORD m32r_cgen_opval_gr_names; extern CGEN_KEYWORD m32r_cgen_opval_cr_names; extern CGEN_KEYWORD m32r_cgen_opval_h_accums; +extern const CGEN_HW_ENTRY m32r_cgen_hw_table[];