X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Fm68k-dis.c;h=ec896433f27076718c7f5e5d5c8b725592119303;hb=1ce22eebea40573551c2db2e7c83951154d14c81;hp=265c113c3cc6f7c13e60bb7583f1d0e316092400;hpb=05545edc03d841f44b1a7aef9f53471681c433e5;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/m68k-dis.c b/opcodes/m68k-dis.c index 265c113c3c..ec896433f2 100644 --- a/opcodes/m68k-dis.c +++ b/opcodes/m68k-dis.c @@ -1,147 +1,197 @@ /* Print Motorola 68k instructions. - Copyright 1986, 1987, 1989, 1991, 1992, 1993 Free Software Foundation, Inc. - -This file is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ - -#include "dis-asm.h" -#include "ieee-float.h" - -extern CONST struct ext_format ext_format_68881; - -/* Opcode/m68k.h is a massive table. As a kludge, break it up into - two pieces. This makes nonportable C -- FIXME -- it assumes that - two data items declared near each other will be contiguous in - memory. This kludge can be removed, FIXME, when GCC is fixed to not - be a hog about initializers. */ - -#ifdef __GNUC__ -#define BREAK_UP_BIG_DECL }; \ - struct m68k_opcode m68k_opcodes_2[] = { -#define AND_OTHER_PART sizeof (m68k_opcodes_2) -#endif - + Copyright (C) 1986-2020 Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "sysdep.h" +#include "disassemble.h" +#include "floatformat.h" +#include "libiberty.h" +#include "opintl.h" +#include "cpu-m68k.h" #include "opcode/m68k.h" +/* Local function prototypes. */ -/* Local function prototypes */ - -static int -fetch_arg PARAMS ((unsigned char *, int, int, disassemble_info *)); - -static void -print_base PARAMS ((int, int, disassemble_info*)); +const char * const fpcr_names[] = +{ + "", "%fpiar", "%fpsr", "%fpiar/%fpsr", "%fpcr", + "%fpiar/%fpcr", "%fpsr/%fpcr", "%fpiar/%fpsr/%fpcr" +}; -static unsigned char * -print_indexed PARAMS ((int, unsigned char *, bfd_vma, disassemble_info *)); +static char *const reg_names[] = +{ + "%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7", + "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%fp", "%sp", + "%ps", "%pc" +}; -static unsigned char * -print_insn_arg PARAMS ((char *, unsigned char *, unsigned char *, bfd_vma, - disassemble_info *)); +/* Name of register halves for MAC/EMAC. + Seperate from reg_names since 'spu', 'fpl' look weird. */ +static char *const reg_half_names[] = +{ + "%d0", "%d1", "%d2", "%d3", "%d4", "%d5", "%d6", "%d7", + "%a0", "%a1", "%a2", "%a3", "%a4", "%a5", "%a6", "%a7", + "%ps", "%pc" +}; -/* Sign-extend an (unsigned char). */ +/* Sign-extend an (unsigned char). */ #if __STDC__ == 1 -#define COERCE_SIGNED_CHAR(ch) ((signed char)(ch)) +#define COERCE_SIGNED_CHAR(ch) ((signed char) (ch)) #else -#define COERCE_SIGNED_CHAR(ch) ((int)(((ch) ^ 0x80) & 0xFF) - 128) +#define COERCE_SIGNED_CHAR(ch) ((int) (((ch) ^ 0x80) & 0xFF) - 128) #endif -CONST char * CONST fpcr_names[] = { - "", "fpiar", "fpsr", "fpiar/fpsr", "fpcr", - "fpiar/fpcr", "fpsr/fpcr", "fpiar/fpsr/fpcr"}; - -static char *reg_names[] = { - "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "a0", - "a1", "a2", "a3", "a4", "a5", "fp", "sp", "ps", "pc"}; - -/* Define accessors for 68K's 1, 2, and 4-byte signed quantities. - The _SHIFT values move the quantity to the high order end of an - `int' value, so it will sign-extend. Probably a few more casts - are needed to make it compile without warnings on finicky systems. */ -#define BITS_PER_BYTE 8 -#define WORD_SHIFT (BITS_PER_BYTE * ((sizeof (int)) - 2)) -#define LONG_SHIFT (BITS_PER_BYTE * ((sizeof (int)) - 4)) - -#define NEXTBYTE(p) (p += 2, FETCH_DATA (info, p), COERCE_SIGNED_CHAR(p[-1])) - -#define NEXTWORD(p) \ - (p += 2, FETCH_DATA (info, p), \ - (((int)((p[-2] << 8) + p[-1])) << WORD_SHIFT) >> WORD_SHIFT) - -#define NEXTLONG(p) \ - (p += 4, FETCH_DATA (info, p), \ - (((int)((((((p[-4] << 8) + p[-3]) << 8) + p[-2]) << 8) + p[-1])) \ - << LONG_SHIFT) >> LONG_SHIFT) - -/* NEXTSINGLE and NEXTDOUBLE handle alignment problems, but not - * byte-swapping or other float format differences. FIXME! */ - -union number { - double d; - float f; - char c[10]; -}; - -#define NEXTSINGLE(val, p) \ - { int i; union number u;\ - FETCH_DATA (info, p + sizeof (float));\ - for (i = 0; i < sizeof(float); i++) u.c[i] = *p++; \ - val = u.f; } - -#define NEXTDOUBLE(val, p) \ - { int i; union number u;\ - FETCH_DATA (info, p + sizeof (double));\ - for (i = 0; i < sizeof(double); i++) u.c[i] = *p++; \ - val = u.d; } - -/* Need a function to convert from extended to double precision... */ -#define NEXTEXTEND(p) \ - (p += 12, FETCH_DATA (info, p), 0.0) +/* Error code of print_insn_arg's return value. */ + +enum print_insn_arg_error + { + /* An invalid operand is found. */ + PRINT_INSN_ARG_INVALID_OPERAND = -1, + + /* An opcode table error. */ + PRINT_INSN_ARG_INVALID_OP_TABLE = -2, + + /* A memory error. */ + PRINT_INSN_ARG_MEMORY_ERROR = -3, + }; + +/* Get a 1 byte signed integer. */ +#define NEXTBYTE(p, val) \ + do \ + { \ + p += 2; \ + if (!FETCH_DATA (info, p)) \ + return PRINT_INSN_ARG_MEMORY_ERROR; \ + val = COERCE_SIGNED_CHAR (p[-1]); \ + } \ + while (0) + +/* Get a 2 byte signed integer. */ +#define COERCE16(x) ((int) (((x) ^ 0x8000) - 0x8000)) + +#define NEXTWORD(p, val, ret_val) \ + do \ + { \ + p += 2; \ + if (!FETCH_DATA (info, p)) \ + return ret_val; \ + val = COERCE16 ((p[-2] << 8) + p[-1]); \ + } \ + while (0) + +/* Get a 4 byte signed integer. */ +#define COERCE32(x) (((bfd_vma) (x) ^ 0x80000000) - 0x80000000) + +#define NEXTLONG(p, val, ret_val) \ + do \ + { \ + p += 4; \ + if (!FETCH_DATA (info, p)) \ + return ret_val; \ + val = COERCE32 (((((((unsigned) p[-4] << 8) + p[-3]) << 8) \ + + p[-2]) << 8) + p[-1]); \ + } \ + while (0) + +/* Get a 4 byte unsigned integer. */ +#define NEXTULONG(p, val) \ + do \ + { \ + p += 4; \ + if (!FETCH_DATA (info, p)) \ + return PRINT_INSN_ARG_MEMORY_ERROR; \ + val = (((((((unsigned) p[-4] << 8) + p[-3]) << 8) \ + + p[-2]) << 8) + p[-1]); \ + } \ + while (0) + +/* Get a single precision float. */ +#define NEXTSINGLE(val, p) \ + do \ + { \ + p += 4; \ + if (!FETCH_DATA (info, p)) \ + return PRINT_INSN_ARG_MEMORY_ERROR; \ + floatformat_to_double (& floatformat_ieee_single_big, \ + (char *) p - 4, & val); \ + } \ + while (0) + +/* Get a double precision float. */ +#define NEXTDOUBLE(val, p) \ + do \ + { \ + p += 8; \ + if (!FETCH_DATA (info, p)) \ + return PRINT_INSN_ARG_MEMORY_ERROR; \ + floatformat_to_double (& floatformat_ieee_double_big, \ + (char *) p - 8, & val); \ + } \ + while (0) + +/* Get an extended precision float. */ +#define NEXTEXTEND(val, p) \ + do \ + { \ + p += 12; \ + if (!FETCH_DATA (info, p)) \ + return PRINT_INSN_ARG_MEMORY_ERROR; \ + floatformat_to_double (& floatformat_m68881_ext, \ + (char *) p - 12, & val); \ + } \ + while (0) /* Need a function to convert from packed to double precision. Actually, it's easier to print a packed number than a double anyway, so maybe there should be a special case to handle this... */ -#define NEXTPACKED(p) \ - (p += 12, FETCH_DATA (info, p), 0.0) +#define NEXTPACKED(p, val) \ + do \ + { \ + p += 12; \ + if (!FETCH_DATA (info, p)) \ + return PRINT_INSN_ARG_MEMORY_ERROR; \ + val = 0.0; \ + } \ + while (0) /* Maximum length of an instruction. */ #define MAXLEN 22 -#include - struct private { /* Points to first byte not fetched. */ bfd_byte *max_fetched; bfd_byte the_buffer[MAXLEN]; bfd_vma insn_start; - jmp_buf bailout; }; /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) - to ADDR (exclusive) are valid. Returns 1 for success, longjmps - on error. */ + to ADDR (exclusive) are valid. Returns 1 for success, 0 on memory + error. */ #define FETCH_DATA(info, addr) \ - ((addr) <= ((struct private *)(info->private_data))->max_fetched \ + ((addr) <= ((struct private *) (info->private_data))->max_fetched \ ? 1 : fetch_data ((info), (addr))) static int -fetch_data (info, addr) - struct disassemble_info *info; - bfd_byte *addr; +fetch_data (struct disassemble_info *info, bfd_byte *addr) { int status; struct private *priv = (struct private *)info->private_data; @@ -154,371 +204,783 @@ fetch_data (info, addr) if (status != 0) { (*info->memory_error_func) (status, start, info); - longjmp (priv->bailout, 1); + return 0; } else priv->max_fetched = addr; return 1; } +/* This function is used to print to the bit-bucket. */ +static int +dummy_printer (FILE *file ATTRIBUTE_UNUSED, + const char *format ATTRIBUTE_UNUSED, + ...) +{ + return 0; +} + static void -m68k_opcode_error(info, code, place) - struct disassemble_info *info; - int code, place; +dummy_print_address (bfd_vma vma ATTRIBUTE_UNUSED, + struct disassemble_info *info ATTRIBUTE_UNUSED) { - (*info->fprintf_func)(info->stream, - "", - code, place); } -/* Print the m68k instruction at address MEMADDR in debugged memory, - on STREAM. Returns length of the instruction, in bytes. */ +/* Fetch BITS bits from a position in the instruction specified by CODE. + CODE is a "place to put an argument", or 'x' for a destination + that is a general address (mode and register). + BUFFER contains the instruction. + Returns -1 on failure. */ -int -print_insn_m68k (memaddr, info) - bfd_vma memaddr; - disassemble_info *info; +static int +fetch_arg (unsigned char *buffer, + int code, + int bits, + disassemble_info *info) { - register int i; - register unsigned char *p; - register char *d; - register unsigned long bestmask; - int best; - struct private priv; - bfd_byte *buffer = priv.the_buffer; + int val = 0; - info->private_data = (PTR) &priv; - priv.max_fetched = priv.the_buffer; - priv.insn_start = memaddr; - if (setjmp (priv.bailout) != 0) - /* Error return. */ - return -1; + switch (code) + { + case '/': /* MAC/EMAC mask bit. */ + val = buffer[3] >> 5; + break; + + case 'G': /* EMAC ACC load. */ + val = ((buffer[3] >> 3) & 0x2) | ((~buffer[1] >> 7) & 0x1); + break; + + case 'H': /* EMAC ACC !load. */ + val = ((buffer[3] >> 3) & 0x2) | ((buffer[1] >> 7) & 0x1); + break; + + case ']': /* EMAC ACCEXT bit. */ + val = buffer[0] >> 2; + break; + + case 'I': /* MAC/EMAC scale factor. */ + val = buffer[2] >> 1; + break; + + case 'F': /* EMAC ACCx. */ + val = buffer[0] >> 1; + break; + + case 'f': + val = buffer[1]; + break; + + case 's': + val = buffer[1]; + break; + + case 'd': /* Destination, for register or quick. */ + val = (buffer[0] << 8) + buffer[1]; + val >>= 9; + break; + + case 'x': /* Destination, for general arg. */ + val = (buffer[0] << 8) + buffer[1]; + val >>= 6; + break; + + case 'k': + if (! FETCH_DATA (info, buffer + 3)) + return -1; + val = (buffer[3] >> 4); + break; + + case 'C': + if (! FETCH_DATA (info, buffer + 3)) + return -1; + val = buffer[3]; + break; + + case '1': + if (! FETCH_DATA (info, buffer + 3)) + return -1; + val = (buffer[2] << 8) + buffer[3]; + val >>= 12; + break; + + case '2': + if (! FETCH_DATA (info, buffer + 3)) + return -1; + val = (buffer[2] << 8) + buffer[3]; + val >>= 6; + break; + + case '3': + case 'j': + if (! FETCH_DATA (info, buffer + 3)) + return -1; + val = (buffer[2] << 8) + buffer[3]; + break; + + case '4': + if (! FETCH_DATA (info, buffer + 5)) + return -1; + val = (buffer[4] << 8) + buffer[5]; + val >>= 12; + break; + + case '5': + if (! FETCH_DATA (info, buffer + 5)) + return -1; + val = (buffer[4] << 8) + buffer[5]; + val >>= 6; + break; + + case '6': + if (! FETCH_DATA (info, buffer + 5)) + return -1; + val = (buffer[4] << 8) + buffer[5]; + break; + + case '7': + if (! FETCH_DATA (info, buffer + 3)) + return -1; + val = (buffer[2] << 8) + buffer[3]; + val >>= 7; + break; + + case '8': + if (! FETCH_DATA (info, buffer + 3)) + return -1; + val = (buffer[2] << 8) + buffer[3]; + val >>= 10; + break; + + case '9': + if (! FETCH_DATA (info, buffer + 3)) + return -1; + val = (buffer[2] << 8) + buffer[3]; + val >>= 5; + break; + + case 'e': + val = (buffer[1] >> 6); + break; + + case 'E': + if (! FETCH_DATA (info, buffer + 3)) + return -1; + val = (buffer[2] >> 1); + break; + + case 'm': + val = (buffer[1] & 0x40 ? 0x8 : 0) + | ((buffer[0] >> 1) & 0x7) + | (buffer[3] & 0x80 ? 0x10 : 0); + break; + + case 'n': + val = (buffer[1] & 0x40 ? 0x8 : 0) | ((buffer[0] >> 1) & 0x7); + break; + + case 'o': + val = (buffer[2] >> 4) | (buffer[3] & 0x80 ? 0x10 : 0); + break; + + case 'M': + val = (buffer[1] & 0xf) | (buffer[3] & 0x40 ? 0x10 : 0); + break; + + case 'N': + val = (buffer[3] & 0xf) | (buffer[3] & 0x40 ? 0x10 : 0); + break; + + case 'h': + val = buffer[2] >> 2; + break; + + default: + abort (); + } - bestmask = 0; - best = -1; - FETCH_DATA (info, buffer + 2); - for (i = 0; i < numopcodes; i++) + /* bits is never too big. */ + return val & ((1 << bits) - 1); +} + +/* Check if an EA is valid for a particular code. This is required + for the EMAC instructions since the type of source address determines + if it is a EMAC-load instruciton if the EA is mode 2-5, otherwise it + is a non-load EMAC instruction and the bits mean register Ry. + A similar case exists for the movem instructions where the register + mask is interpreted differently for different EAs. */ + +static bfd_boolean +m68k_valid_ea (char code, int val) +{ + int mode, mask; +#define M(n0,n1,n2,n3,n4,n5,n6,n70,n71,n72,n73,n74) \ + (n0 | n1 << 1 | n2 << 2 | n3 << 3 | n4 << 4 | n5 << 5 | n6 << 6 \ + | n70 << 7 | n71 << 8 | n72 << 9 | n73 << 10 | n74 << 11) + + switch (code) { - register unsigned long opcode = m68k_opcodes[i].opcode; - register unsigned long match = m68k_opcodes[i].match; - if (((0xff & buffer[0] & (match >> 24)) == (0xff & (opcode >> 24))) - && ((0xff & buffer[1] & (match >> 16)) == (0xff & (opcode >> 16))) - /* Only fetch the next two bytes if we need to. */ - && (((0xffff & match) == 0) - || - (FETCH_DATA (info, buffer + 4) - && ((0xff & buffer[2] & (match >> 8)) == (0xff & (opcode >> 8))) - && ((0xff & buffer[3] & match) == (0xff & opcode))) - )) - { - /* Don't use for printout the variants of divul and divsl - that have the same register number in two places. - The more general variants will match instead. */ - for (d = m68k_opcodes[i].args; *d; d += 2) - if (d[1] == 'D') - break; + case '*': + mask = M (1,1,1,1,1,1,1,1,1,1,1,1); + break; + case '~': + mask = M (0,0,1,1,1,1,1,1,1,0,0,0); + break; + case '%': + mask = M (1,1,1,1,1,1,1,1,1,0,0,0); + break; + case ';': + mask = M (1,0,1,1,1,1,1,1,1,1,1,1); + break; + case '@': + mask = M (1,0,1,1,1,1,1,1,1,1,1,0); + break; + case '!': + mask = M (0,0,1,0,0,1,1,1,1,1,1,0); + break; + case '&': + mask = M (0,0,1,0,0,1,1,1,1,0,0,0); + break; + case '$': + mask = M (1,0,1,1,1,1,1,1,1,0,0,0); + break; + case '?': + mask = M (1,0,1,0,0,1,1,1,1,0,0,0); + break; + case '/': + mask = M (1,0,1,0,0,1,1,1,1,1,1,0); + break; + case '|': + mask = M (0,0,1,0,0,1,1,1,1,1,1,0); + break; + case '>': + mask = M (0,0,1,0,1,1,1,1,1,0,0,0); + break; + case '<': + mask = M (0,0,1,1,0,1,1,1,1,1,1,0); + break; + case 'm': + mask = M (1,1,1,1,1,0,0,0,0,0,0,0); + break; + case 'n': + mask = M (0,0,0,0,0,1,0,0,0,1,0,0); + break; + case 'o': + mask = M (0,0,0,0,0,0,1,1,1,0,1,1); + break; + case 'p': + mask = M (1,1,1,1,1,1,0,0,0,0,0,0); + break; + case 'q': + mask = M (1,0,1,1,1,1,0,0,0,0,0,0); + break; + case 'v': + mask = M (1,0,1,1,1,1,0,1,1,0,0,0); + break; + case 'b': + mask = M (1,0,1,1,1,1,0,0,0,1,0,0); + break; + case 'w': + mask = M (0,0,1,1,1,1,0,0,0,1,0,0); + break; + case 'y': + mask = M (0,0,1,0,0,1,0,0,0,0,0,0); + break; + case 'z': + mask = M (0,0,1,0,0,1,0,0,0,1,0,0); + break; + case '4': + mask = M (0,0,1,1,1,1,0,0,0,0,0,0); + break; + default: + abort (); + } +#undef M - /* Don't use for printout the variants of most floating - point coprocessor instructions which use the same - register number in two places, as above. */ - if (*d == 0) - for (d = m68k_opcodes[i].args; *d; d += 2) - if (d[1] == 't') - break; + mode = (val >> 3) & 7; + if (mode == 7) + mode += val & 7; + return (mask & (1 << mode)) != 0; +} - if (*d == 0 && match > bestmask) - { - best = i; - bestmask = match; - } - } +/* Print a base register REGNO and displacement DISP, on INFO->STREAM. + REGNO = -1 for pc, -2 for none (suppressed). */ + +static void +print_base (int regno, bfd_vma disp, disassemble_info *info) +{ + if (regno == -1) + { + (*info->fprintf_func) (info->stream, "%%pc@("); + (*info->print_address_func) (disp, info); + } + else + { + char buf[50]; + + if (regno == -2) + (*info->fprintf_func) (info->stream, "@("); + else if (regno == -3) + (*info->fprintf_func) (info->stream, "%%zpc@("); + else + (*info->fprintf_func) (info->stream, "%s@(", reg_names[regno]); + + sprintf_vma (buf, disp); + (*info->fprintf_func) (info->stream, "%s", buf); } +} + +/* Print an indexed argument. The base register is BASEREG (-1 for pc). + P points to extension word, in buffer. + ADDR is the nominal core address of that extension word. + Returns NULL upon error. */ - /* Handle undefined instructions. */ - if (best < 0) +static unsigned char * +print_indexed (int basereg, + unsigned char *p, + bfd_vma addr, + disassemble_info *info) +{ + int word; + static char *const scales[] = { "", ":2", ":4", ":8" }; + bfd_vma base_disp; + bfd_vma outer_disp; + char buf[40]; + char vmabuf[50]; + + NEXTWORD (p, word, NULL); + + /* Generate the text for the index register. + Where this will be output is not yet determined. */ + sprintf (buf, "%s:%c%s", + reg_names[(word >> 12) & 0xf], + (word & 0x800) ? 'l' : 'w', + scales[(word >> 9) & 3]); + + /* Handle the 68000 style of indexing. */ + + if ((word & 0x100) == 0) { - (*info->fprintf_func) (info->stream, "0%o", - (buffer[0] << 8) + buffer[1]); - return 2; + base_disp = word & 0xff; + if ((base_disp & 0x80) != 0) + base_disp -= 0x100; + if (basereg == -1) + base_disp += addr; + print_base (basereg, base_disp, info); + (*info->fprintf_func) (info->stream, ",%s)", buf); + return p; } - (*info->fprintf_func) (info->stream, "%s", m68k_opcodes[best].name); + /* Handle the generalized kind. */ + /* First, compute the displacement to add to the base register. */ + if (word & 0200) + { + if (basereg == -1) + basereg = -3; + else + basereg = -2; + } + if (word & 0100) + buf[0] = '\0'; + base_disp = 0; + switch ((word >> 4) & 3) + { + case 2: + NEXTWORD (p, base_disp, NULL); + break; + case 3: + NEXTLONG (p, base_disp, NULL); + } + if (basereg == -1) + base_disp += addr; - /* Point at first word of argument data, - and at descriptor for first argument. */ - p = buffer + 2; - - /* Why do this this way? -MelloN */ - for (d = m68k_opcodes[best].args; *d; d += 2) + /* Handle single-level case (not indirect). */ + if ((word & 7) == 0) { - if (d[0] == '#') - { - if (d[1] == 'l' && p - buffer < 6) - p = buffer + 6; - else if (p - buffer < 4 && d[1] != 'C' && d[1] != '8' ) - p = buffer + 4; - } - if (d[1] >= '1' && d[1] <= '3' && p - buffer < 4) - p = buffer + 4; - if (d[1] >= '4' && d[1] <= '6' && p - buffer < 6) - p = buffer + 6; - if ((d[0] == 'L' || d[0] == 'l') && d[1] == 'w' && p - buffer < 4) - p = buffer + 4; + print_base (basereg, base_disp, info); + if (buf[0] != '\0') + (*info->fprintf_func) (info->stream, ",%s", buf); + (*info->fprintf_func) (info->stream, ")"); + return p; } - - FETCH_DATA (info, p); - - d = m68k_opcodes[best].args; - if (*d) - (*info->fprintf_func) (info->stream, " "); + /* Two level. Compute displacement to add after indirection. */ + outer_disp = 0; + switch (word & 3) + { + case 2: + NEXTWORD (p, outer_disp, NULL); + break; + case 3: + NEXTLONG (p, outer_disp, NULL); + } - while (*d) + print_base (basereg, base_disp, info); + if ((word & 4) == 0 && buf[0] != '\0') { - p = print_insn_arg (d, buffer, p, memaddr + p - buffer, info); - d += 2; - if (*d && *(d - 2) != 'I' && *d != 'k') - (*info->fprintf_func) (info->stream, ","); + (*info->fprintf_func) (info->stream, ",%s", buf); + buf[0] = '\0'; } - return p - buffer; + sprintf_vma (vmabuf, outer_disp); + (*info->fprintf_func) (info->stream, ")@(%s", vmabuf); + if (buf[0] != '\0') + (*info->fprintf_func) (info->stream, ",%s", buf); + (*info->fprintf_func) (info->stream, ")"); + + return p; } -static unsigned char * -print_insn_arg (d, buffer, p, addr, info) - char *d; - unsigned char *buffer; - register unsigned char *p; - bfd_vma addr; /* PC for this arg to be relative to */ - disassemble_info *info; +#define FETCH_ARG(size, val) \ + do \ + { \ + val = fetch_arg (buffer, place, size, info); \ + if (val < 0) \ + return PRINT_INSN_ARG_MEMORY_ERROR; \ + } \ + while (0) + +/* Returns number of bytes "eaten" by the operand, or + return enum print_insn_arg_error. ADDR is the pc for this arg to be + relative to. */ + +static int +print_insn_arg (const char *d, + unsigned char *buffer, + unsigned char *p0, + bfd_vma addr, + disassemble_info *info) { - register int val = 0; - register int place = d[1]; + int val = 0; + int place = d[1]; + unsigned char *p = p0; int regno; - register CONST char *regname; - register unsigned char *p1; + const char *regname; + unsigned char *p1; double flval; int flt_p; + bfd_signed_vma disp; + unsigned int uval; switch (*d) { - case 'c': /* cache identifier */ + case 'c': /* Cache identifier. */ { - static char *cacheFieldName[] = { "NOP", "dc", "ic", "bc" }; - val = fetch_arg (buffer, place, 2, info); - (*info->fprintf_func) (info->stream, cacheFieldName[val]); + static char *const cacheFieldName[] = { "nc", "dc", "ic", "bc" }; + FETCH_ARG (2, val); + (*info->fprintf_func) (info->stream, "%s", cacheFieldName[val]); break; } - case 'a': /* address register indirect only. Cf. case '+'. */ + case 'a': /* Address register indirect only. Cf. case '+'. */ { - (*info->fprintf_func) - (info->stream, - "%s@", - reg_names [fetch_arg (buffer, place, 3, info) + 8]); + FETCH_ARG (3, val); + (*info->fprintf_func) (info->stream, "%s@", reg_names[val + 8]); break; } - case '_': /* 32-bit absolute address for move16. */ + case '_': /* 32-bit absolute address for move16. */ { - val = NEXTLONG (p); - (*info->fprintf_func) (info->stream, "@#"); - print_address (val, info->stream); + NEXTULONG (p, uval); + (*info->print_address_func) (uval, info); break; } case 'C': - (*info->fprintf_func) (info->stream, "ccr"); + (*info->fprintf_func) (info->stream, "%%ccr"); break; case 'S': - (*info->fprintf_func) (info->stream, "sr"); + (*info->fprintf_func) (info->stream, "%%sr"); break; case 'U': - (*info->fprintf_func) (info->stream, "usp"); + (*info->fprintf_func) (info->stream, "%%usp"); + break; + + case 'E': + (*info->fprintf_func) (info->stream, "%%acc"); + break; + + case 'G': + (*info->fprintf_func) (info->stream, "%%macsr"); + break; + + case 'H': + (*info->fprintf_func) (info->stream, "%%mask"); break; case 'J': { - static struct { char *name; int value; } names[] - = {{"sfc", 0x000}, {"dfc", 0x001}, {"cacr", 0x002}, - {"tc", 0x003}, {"itt0",0x004}, {"itt1", 0x005}, - {"dtt0",0x006}, {"dtt1",0x007}, - {"usp", 0x800}, {"vbr", 0x801}, {"caar", 0x802}, - {"msp", 0x803}, {"isp", 0x804}, {"mmusr",0x805}, - {"urp", 0x806}, {"srp", 0x807}}; - - val = fetch_arg (buffer, place, 12, info); - for (regno = sizeof names / sizeof names[0] - 1; regno >= 0; regno--) + /* FIXME: There's a problem here, different m68k processors call the + same address different names. The tables below try to get it right + using info->mach, but only for v4e. */ + struct regname { char * name; int value; }; + static const struct regname names[] = + { + {"%sfc", 0x000}, {"%dfc", 0x001}, {"%cacr", 0x002}, + {"%tc", 0x003}, {"%itt0",0x004}, {"%itt1", 0x005}, + {"%dtt0",0x006}, {"%dtt1",0x007}, {"%buscr",0x008}, + {"%rgpiobar", 0x009}, {"%acr4",0x00c}, + {"%acr5",0x00d}, {"%acr6",0x00e}, {"%acr7", 0x00f}, + {"%usp", 0x800}, {"%vbr", 0x801}, {"%caar", 0x802}, + {"%msp", 0x803}, {"%isp", 0x804}, + {"%pc", 0x80f}, + /* Reg c04 is sometimes called flashbar or rambar. + Reg c05 is also sometimes called rambar. */ + {"%rambar0", 0xc04}, {"%rambar1", 0xc05}, + + /* reg c0e is sometimes called mbar2 or secmbar. + reg c0f is sometimes called mbar. */ + {"%mbar0", 0xc0e}, {"%mbar1", 0xc0f}, + + /* Should we be calling this psr like we do in case 'Y'? */ + {"%mmusr",0x805}, + + {"%urp", 0x806}, {"%srp", 0x807}, {"%pcr", 0x808}, + + /* Fido added these. */ + {"%cac", 0xffe}, {"%mbo", 0xfff} + }; + /* Alternate names for v4e (MCF5407/5445x/MCF547x/MCF548x), at least. */ + static const struct regname names_v4e[] = + { + {"%asid",0x003}, {"%acr0",0x004}, {"%acr1",0x005}, + {"%acr2",0x006}, {"%acr3",0x007}, {"%mmubar",0x008}, + }; + unsigned int arch_mask; + + arch_mask = bfd_m68k_mach_to_features (info->mach); + FETCH_ARG (12, val); + if (arch_mask & (mcfisa_b | mcfisa_c)) + { + for (regno = ARRAY_SIZE (names_v4e); --regno >= 0;) + if (names_v4e[regno].value == val) + { + (*info->fprintf_func) (info->stream, "%s", names_v4e[regno].name); + break; + } + if (regno >= 0) + break; + } + for (regno = ARRAY_SIZE (names) - 1; regno >= 0; regno--) if (names[regno].value == val) { - (*info->fprintf_func) (info->stream, names[regno].name); + (*info->fprintf_func) (info->stream, "%s", names[regno].name); break; } if (regno < 0) - (*info->fprintf_func) (info->stream, "%d", val); + (*info->fprintf_func) (info->stream, "0x%x", val); } break; case 'Q': - val = fetch_arg (buffer, place, 3, info); + FETCH_ARG (3, val); /* 0 means 8, except for the bkpt instruction... */ if (val == 0 && d[1] != 's') val = 8; (*info->fprintf_func) (info->stream, "#%d", val); break; - case 'M': - val = fetch_arg (buffer, place, 8, info); - if (val & 0x80) - val = val - 0x100; + case 'x': + FETCH_ARG (3, val); + /* 0 means -1. */ + if (val == 0) + val = -1; (*info->fprintf_func) (info->stream, "#%d", val); break; + case 'j': + FETCH_ARG (3, val); + (*info->fprintf_func) (info->stream, "#%d", val+1); + break; + + case 'K': + FETCH_ARG (9, val); + (*info->fprintf_func) (info->stream, "#%d", val); + break; + + case 'M': + if (place == 'h') + { + static char *const scalefactor_name[] = { "<<", ">>" }; + + FETCH_ARG (1, val); + (*info->fprintf_func) (info->stream, "%s", scalefactor_name[val]); + } + else + { + FETCH_ARG (8, val); + if (val & 0x80) + val = val - 0x100; + (*info->fprintf_func) (info->stream, "#%d", val); + } + break; + case 'T': - val = fetch_arg (buffer, place, 4, info); + FETCH_ARG (4, val); (*info->fprintf_func) (info->stream, "#%d", val); break; case 'D': - (*info->fprintf_func) (info->stream, "%s", - reg_names[fetch_arg (buffer, place, 3, info)]); + FETCH_ARG (3, val); + (*info->fprintf_func) (info->stream, "%s", reg_names[val]); break; case 'A': - (*info->fprintf_func) - (info->stream, "%s", - reg_names[fetch_arg (buffer, place, 3, info) + 010]); + FETCH_ARG (3, val); + (*info->fprintf_func) (info->stream, "%s", reg_names[val + 010]); break; case 'R': - (*info->fprintf_func) - (info->stream, "%s", - reg_names[fetch_arg (buffer, place, 4, info)]); + FETCH_ARG (4, val); + (*info->fprintf_func) (info->stream, "%s", reg_names[val]); break; case 'r': - (*info->fprintf_func) - (info->stream, "%s@", - reg_names[fetch_arg (buffer, place, 4, info)]); + FETCH_ARG (4, regno); + if (regno > 7) + (*info->fprintf_func) (info->stream, "%s@", reg_names[regno]); + else + (*info->fprintf_func) (info->stream, "@(%s)", reg_names[regno]); break; case 'F': - (*info->fprintf_func) - (info->stream, "fp%d", - fetch_arg (buffer, place, 3, info)); + FETCH_ARG (3, val); + (*info->fprintf_func) (info->stream, "%%fp%d", val); break; case 'O': - val = fetch_arg (buffer, place, 6, info); + FETCH_ARG (6, val); if (val & 0x20) - (*info->fprintf_func) (info->stream, "%s", reg_names [val & 7]); + (*info->fprintf_func) (info->stream, "%s", reg_names[val & 7]); else (*info->fprintf_func) (info->stream, "%d", val); break; case '+': - (*info->fprintf_func) - (info->stream, "%s@+", - reg_names[fetch_arg (buffer, place, 3, info) + 8]); + FETCH_ARG (3, val); + (*info->fprintf_func) (info->stream, "%s@+", reg_names[val + 8]); break; case '-': - (*info->fprintf_func) - (info->stream, "%s@-", - reg_names[fetch_arg (buffer, place, 3, info) + 8]); + FETCH_ARG (3, val); + (*info->fprintf_func) (info->stream, "%s@-", reg_names[val + 8]); break; case 'k': if (place == 'k') - (*info->fprintf_func) - (info->stream, "{%s}", - reg_names[fetch_arg (buffer, place, 3, info)]); + { + FETCH_ARG (3, val); + (*info->fprintf_func) (info->stream, "{%s}", reg_names[val]); + } else if (place == 'C') { - val = fetch_arg (buffer, place, 7, info); - if ( val > 63 ) /* This is a signed constant. */ + FETCH_ARG (7, val); + if (val > 63) /* This is a signed constant. */ val -= 128; (*info->fprintf_func) (info->stream, "{#%d}", val); } else - m68k_opcode_error (info, *d, place); + return PRINT_INSN_ARG_INVALID_OPERAND; break; case '#': case '^': p1 = buffer + (*d == '#' ? 2 : 4); if (place == 's') - val = fetch_arg (buffer, place, 4, info); + FETCH_ARG (4, val); else if (place == 'C') - val = fetch_arg (buffer, place, 7, info); + FETCH_ARG (7, val); else if (place == '8') - val = fetch_arg (buffer, place, 3, info); + FETCH_ARG (3, val); else if (place == '3') - val = fetch_arg (buffer, place, 8, info); + FETCH_ARG (8, val); else if (place == 'b') - val = NEXTBYTE (p1); - else if (place == 'w') - val = NEXTWORD (p1); + NEXTBYTE (p1, val); + else if (place == 'w' || place == 'W') + NEXTWORD (p1, val, PRINT_INSN_ARG_MEMORY_ERROR); else if (place == 'l') - val = NEXTLONG (p1); + NEXTLONG (p1, val, PRINT_INSN_ARG_MEMORY_ERROR); else - m68k_opcode_error (info, *d, place); + return PRINT_INSN_ARG_INVALID_OP_TABLE; + (*info->fprintf_func) (info->stream, "#%d", val); break; case 'B': if (place == 'b') - val = NEXTBYTE (p); + NEXTBYTE (p, disp); else if (place == 'B') - val = COERCE_SIGNED_CHAR(buffer[1]); + disp = COERCE_SIGNED_CHAR (buffer[1]); else if (place == 'w' || place == 'W') - val = NEXTWORD (p); - else if (place == 'l' || place == 'L') - val = NEXTLONG (p); + NEXTWORD (p, disp, PRINT_INSN_ARG_MEMORY_ERROR); + else if (place == 'l' || place == 'L' || place == 'C') + NEXTLONG (p, disp, PRINT_INSN_ARG_MEMORY_ERROR); else if (place == 'g') { - val = NEXTBYTE (buffer); - if (val == 0) - val = NEXTWORD (p); - else if (val == -1) - val = NEXTLONG (p); + NEXTBYTE (buffer, disp); + if (disp == 0) + NEXTWORD (p, disp, PRINT_INSN_ARG_MEMORY_ERROR); + else if (disp == -1) + NEXTLONG (p, disp, PRINT_INSN_ARG_MEMORY_ERROR); } else if (place == 'c') { - if (buffer[1] & 0x40) /* If bit six is one, long offset */ - val = NEXTLONG (p); + if (buffer[1] & 0x40) /* If bit six is one, long offset. */ + NEXTLONG (p, disp, PRINT_INSN_ARG_MEMORY_ERROR); else - val = NEXTWORD (p); + NEXTWORD (p, disp, PRINT_INSN_ARG_MEMORY_ERROR); } else - m68k_opcode_error (info, *d, place); + return PRINT_INSN_ARG_INVALID_OP_TABLE; - print_address (addr + val, info->stream); + (*info->print_address_func) (addr + disp, info); break; case 'd': - val = NEXTWORD (p); - (*info->fprintf_func) - (info->stream, "%s@(%d)", - reg_names[fetch_arg (buffer, place, 3, info)], val); - break; + { + int val1; + + NEXTWORD (p, val, PRINT_INSN_ARG_MEMORY_ERROR); + FETCH_ARG (3, val1); + (*info->fprintf_func) (info->stream, "%s@(%d)", reg_names[val1 + 8], val); + break; + } case 's': - (*info->fprintf_func) (info->stream, "%s", - fpcr_names[fetch_arg (buffer, place, 3, info)]); + FETCH_ARG (3, val); + (*info->fprintf_func) (info->stream, "%s", fpcr_names[val]); + break; + + case 'e': + FETCH_ARG (2, val); + (*info->fprintf_func) (info->stream, "%%acc%d", val); + break; + + case 'g': + FETCH_ARG (1, val); + (*info->fprintf_func) (info->stream, "%%accext%s", val == 0 ? "01" : "23"); + break; + + case 'i': + FETCH_ARG (2, val); + if (val == 1) + (*info->fprintf_func) (info->stream, "<<"); + else if (val == 3) + (*info->fprintf_func) (info->stream, ">>"); + else + return PRINT_INSN_ARG_INVALID_OPERAND; break; case 'I': /* Get coprocessor ID... */ val = fetch_arg (buffer, 'd', 3, info); - - if (val != 1) /* Unusual coprocessor ID? */ + if (val < 0) + return PRINT_INSN_ARG_MEMORY_ERROR; + if (val != 1) /* Unusual coprocessor ID? */ (*info->fprintf_func) (info->stream, "(cpid=%d) ", val); - if (place == 'i') - p += 2; /* Skip coprocessor extended operands */ break; + case '4': case '*': case '~': case '%': @@ -529,15 +991,36 @@ print_insn_arg (d, buffer, p, addr, info) case '?': case '/': case '&': - case '`': - + case '|': + case '<': + case '>': + case 'm': + case 'n': + case 'o': + case 'p': + case 'q': + case 'v': + case 'b': + case 'w': + case 'y': + case 'z': if (place == 'd') { val = fetch_arg (buffer, 'x', 6, info); + if (val < 0) + return PRINT_INSN_ARG_MEMORY_ERROR; val = ((val & 7) << 3) + ((val >> 3) & 7); } else - val = fetch_arg (buffer, 's', 6, info); + { + val = fetch_arg (buffer, 's', 6, info); + if (val < 0) + return PRINT_INSN_ARG_MEMORY_ERROR; + } + + /* If the is invalid for *d, then reject this match. */ + if (!m68k_valid_ea (*d, val)) + return PRINT_INSN_ARG_INVALID_OPERAND; /* Get register number assuming address register. */ regno = (val & 7) + 8; @@ -565,90 +1048,100 @@ print_insn_arg (d, buffer, p, addr, info) break; case 5: - val = NEXTWORD (p); + NEXTWORD (p, val, PRINT_INSN_ARG_MEMORY_ERROR); (*info->fprintf_func) (info->stream, "%s@(%d)", regname, val); break; case 6: p = print_indexed (regno, p, addr, info); + if (p == NULL) + return PRINT_INSN_ARG_MEMORY_ERROR; break; case 7: switch (val & 7) { case 0: - val = NEXTWORD (p); - (*info->fprintf_func) (info->stream, "@#"); - print_address (val, info->stream); + NEXTWORD (p, val, PRINT_INSN_ARG_MEMORY_ERROR); + (*info->print_address_func) (val, info); break; case 1: - val = NEXTLONG (p); - (*info->fprintf_func) (info->stream, "@#"); - print_address (val, info->stream); + NEXTULONG (p, uval); + (*info->print_address_func) (uval, info); break; case 2: - val = NEXTWORD (p); - print_address (addr + val, info->stream); + NEXTWORD (p, val, PRINT_INSN_ARG_MEMORY_ERROR); + (*info->fprintf_func) (info->stream, "%%pc@("); + (*info->print_address_func) (addr + val, info); + (*info->fprintf_func) (info->stream, ")"); break; case 3: p = print_indexed (-1, p, addr, info); + if (p == NULL) + return PRINT_INSN_ARG_MEMORY_ERROR; break; case 4: flt_p = 1; /* Assume it's a float... */ - switch( place ) + switch (place) { case 'b': - val = NEXTBYTE (p); + NEXTBYTE (p, val); flt_p = 0; break; case 'w': - val = NEXTWORD (p); + NEXTWORD (p, val, PRINT_INSN_ARG_MEMORY_ERROR); flt_p = 0; break; case 'l': - val = NEXTLONG (p); + NEXTLONG (p, val, PRINT_INSN_ARG_MEMORY_ERROR); flt_p = 0; break; case 'f': - NEXTSINGLE(flval, p); + NEXTSINGLE (flval, p); break; case 'F': - NEXTDOUBLE(flval, p); + NEXTDOUBLE (flval, p); break; case 'x': - ieee_extended_to_double (&ext_format_68881, - (char *)p, &flval); - p += 12; + NEXTEXTEND (flval, p); break; case 'p': - flval = NEXTPACKED(p); + NEXTPACKED (p, flval); break; default: - m68k_opcode_error (info, *d, place); + return PRINT_INSN_ARG_INVALID_OPERAND; } - if ( flt_p ) /* Print a float? */ - (*info->fprintf_func) (info->stream, "#%g", flval); + if (flt_p) /* Print a float? */ + (*info->fprintf_func) (info->stream, "#0e%g", flval); else (*info->fprintf_func) (info->stream, "#%d", val); break; default: - (*info->fprintf_func) (info->stream, - "", - (unsigned) val); + return PRINT_INSN_ARG_INVALID_OPERAND; } } + + /* If place is '/', then this is the case of the mask bit for + mac/emac loads. Now that the arg has been printed, grab the + mask bit and if set, add a '&' to the arg. */ + if (place == '/') + { + FETCH_ARG (1, val); + if (val) + info->fprintf_func (info->stream, "&"); + } break; case 'L': @@ -657,7 +1150,7 @@ print_insn_arg (d, buffer, p, addr, info) { char doneany; p1 = buffer + 2; - val = NEXTWORD (p1); + NEXTWORD (p1, val, PRINT_INSN_ARG_MEMORY_ERROR); /* Move the pointer ahead if this point is farther ahead than the last. */ p = p1 > p ? p1 : p; @@ -668,7 +1161,8 @@ print_insn_arg (d, buffer, p, addr, info) } if (*d == 'l') { - register int newval = 0; + int newval = 0; + for (regno = 0; regno < 16; ++regno) if (val & (0x8000 >> regno)) newval |= 1 << regno; @@ -680,6 +1174,7 @@ print_insn_arg (d, buffer, p, addr, info) if (val & (1 << regno)) { int first_regno; + if (doneany) (*info->fprintf_func) (info->stream, "/"); doneany = 1; @@ -696,7 +1191,8 @@ print_insn_arg (d, buffer, p, addr, info) { /* `fmovem' insn. */ char doneany; - val = fetch_arg (buffer, place, 8, info); + + FETCH_ARG (8, val); if (val == 0) { (*info->fprintf_func) (info->stream, "#0"); @@ -704,7 +1200,8 @@ print_insn_arg (d, buffer, p, addr, info) } if (*d == 'l') { - register int newval = 0; + int newval = 0; + for (regno = 0; regno < 8; ++regno) if (val & (0x80 >> regno)) newval |= 1 << regno; @@ -719,252 +1216,436 @@ print_insn_arg (d, buffer, p, addr, info) if (doneany) (*info->fprintf_func) (info->stream, "/"); doneany = 1; - (*info->fprintf_func) (info->stream, "fp%d", regno); + (*info->fprintf_func) (info->stream, "%%fp%d", regno); first_regno = regno; while (val & (1 << (regno + 1))) ++regno; if (regno > first_regno) - (*info->fprintf_func) (info->stream, "-fp%d", regno); + (*info->fprintf_func) (info->stream, "-%%fp%d", regno); } } + else if (place == '8') + { + FETCH_ARG (3, val); + /* fmoveml for FP status registers. */ + (*info->fprintf_func) (info->stream, "%s", fpcr_names[val]); + } else - goto de_fault; + return PRINT_INSN_ARG_INVALID_OP_TABLE; break; - default: de_fault: - m68k_opcode_error (info, *d, ' '); - } - - return (unsigned char *) p; -} + case 'X': + place = '8'; + /* Fall through. */ + case 'Y': + case 'Z': + case 'W': + case '0': + case '1': + case '2': + case '3': + { + char *name = 0; -/* Fetch BITS bits from a position in the instruction specified by CODE. - CODE is a "place to put an argument", or 'x' for a destination - that is a general address (mode and register). - BUFFER contains the instruction. */ + FETCH_ARG (5, val); + switch (val) + { + case 2: name = "%tt0"; break; + case 3: name = "%tt1"; break; + case 0x10: name = "%tc"; break; + case 0x11: name = "%drp"; break; + case 0x12: name = "%srp"; break; + case 0x13: name = "%crp"; break; + case 0x14: name = "%cal"; break; + case 0x15: name = "%val"; break; + case 0x16: name = "%scc"; break; + case 0x17: name = "%ac"; break; + case 0x18: name = "%psr"; break; + case 0x19: name = "%pcsr"; break; + case 0x1c: + case 0x1d: + { + int break_reg = ((buffer[3] >> 2) & 7); -static int -fetch_arg (buffer, code, bits, info) - unsigned char *buffer; - int code; - int bits; - disassemble_info *info; -{ - register int val = 0; - switch (code) - { - case 's': - val = buffer[1]; + (*info->fprintf_func) + (info->stream, val == 0x1c ? "%%bad%d" : "%%bac%d", + break_reg); + } + break; + default: + (*info->fprintf_func) (info->stream, "", val); + } + if (name) + (*info->fprintf_func) (info->stream, "%s", name); + } break; - case 'd': /* Destination, for register or quick. */ - val = (buffer[0] << 8) + buffer[1]; - val >>= 9; - break; + case 'f': + { + int fc; - case 'x': /* Destination, for general arg */ - val = (buffer[0] << 8) + buffer[1]; - val >>= 6; + FETCH_ARG (5, fc); + if (fc == 1) + (*info->fprintf_func) (info->stream, "%%dfc"); + else if (fc == 0) + (*info->fprintf_func) (info->stream, "%%sfc"); + else + /* xgettext:c-format */ + (*info->fprintf_func) (info->stream, _(""), fc); + } break; - case 'k': - FETCH_DATA (info, buffer + 3); - val = (buffer[3] >> 4); + case 'V': + (*info->fprintf_func) (info->stream, "%%val"); break; - case 'C': - FETCH_DATA (info, buffer + 3); - val = buffer[3]; - break; + case 't': + { + int level; - case '1': - FETCH_DATA (info, buffer + 3); - val = (buffer[2] << 8) + buffer[3]; - val >>= 12; + FETCH_ARG (3, level); + (*info->fprintf_func) (info->stream, "%d", level); + } break; - case '2': - FETCH_DATA (info, buffer + 3); - val = (buffer[2] << 8) + buffer[3]; - val >>= 6; - break; + case 'u': + { + short is_upper = 0; + int reg; - case '3': - case 'j': - FETCH_DATA (info, buffer + 3); - val = (buffer[2] << 8) + buffer[3]; + FETCH_ARG (5, reg); + if (reg & 0x10) + { + is_upper = 1; + reg &= 0xf; + } + (*info->fprintf_func) (info->stream, "%s%s", + reg_half_names[reg], + is_upper ? "u" : "l"); + } break; - case '4': - FETCH_DATA (info, buffer + 5); - val = (buffer[4] << 8) + buffer[5]; - val >>= 12; - break; + default: + return PRINT_INSN_ARG_INVALID_OP_TABLE; + } - case '5': - FETCH_DATA (info, buffer + 5); - val = (buffer[4] << 8) + buffer[5]; - val >>= 6; - break; + return p - p0; +} - case '6': - FETCH_DATA (info, buffer + 5); - val = (buffer[4] << 8) + buffer[5]; - break; +/* Try to match the current instruction to best and if so, return the + number of bytes consumed from the instruction stream, else zero. + Return -1 on memory error. */ - case '7': - FETCH_DATA (info, buffer + 3); - val = (buffer[2] << 8) + buffer[3]; - val >>= 7; - break; - - case '8': - FETCH_DATA (info, buffer + 3); - val = (buffer[2] << 8) + buffer[3]; - val >>= 10; - break; +static int +match_insn_m68k (bfd_vma memaddr, + disassemble_info * info, + const struct m68k_opcode * best) +{ + unsigned char *save_p; + unsigned char *p; + const char *d; + const char *args = best->args; - case '9': - FETCH_DATA (info, buffer + 3); - val = (buffer[2] << 8) + buffer[3]; - val >>= 5; - break; + struct private *priv = (struct private *) info->private_data; + bfd_byte *buffer = priv->the_buffer; + fprintf_ftype save_printer = info->fprintf_func; + void (* save_print_address) (bfd_vma, struct disassemble_info *) + = info->print_address_func; - case 'e': - val = (buffer[1] >> 6); - break; + if (*args == '.') + args++; - default: - abort (); - } + /* Point at first word of argument data, + and at descriptor for first argument. */ + p = buffer + 2; - switch (bits) + /* Figure out how long the fixed-size portion of the instruction is. + The only place this is stored in the opcode table is + in the arguments--look for arguments which specify fields in the 2nd + or 3rd words of the instruction. */ + for (d = args; *d; d += 2) { - case 2: - return val & 3; - case 3: - return val & 7; - case 4: - return val & 017; - case 5: - return val & 037; - case 6: - return val & 077; - case 7: - return val & 0177; - case 8: - return val & 0377; - case 12: - return val & 07777; - default: - abort (); - } -} + /* I don't think it is necessary to be checking d[0] here; + I suspect all this could be moved to the case statement below. */ + if (d[0] == '#') + { + if (d[1] == 'l' && p - buffer < 6) + p = buffer + 6; + else if (p - buffer < 4 && d[1] != 'C' && d[1] != '8') + p = buffer + 4; + } -/* Print an indexed argument. The base register is BASEREG (-1 for pc). - P points to extension word, in buffer. - ADDR is the nominal core address of that extension word. */ + if ((d[0] == 'L' || d[0] == 'l') && d[1] == 'w' && p - buffer < 4) + p = buffer + 4; -static unsigned char * -print_indexed (basereg, p, addr, info) - int basereg; - unsigned char *p; - bfd_vma addr; - disassemble_info *info; -{ - register int word; - static char *scales[] = {"", "*2", "*4", "*8"}; - register int base_disp; - register int outer_disp; - char buf[40]; + switch (d[1]) + { + case '1': + case '2': + case '3': + case '7': + case '8': + case '9': + case 'i': + if (p - buffer < 4) + p = buffer + 4; + break; + case '4': + case '5': + case '6': + if (p - buffer < 6) + p = buffer + 6; + break; + default: + break; + } + } - word = NEXTWORD (p); + /* pflusha is an exceptions. It takes no arguments but is two words + long. Recognize it by looking at the lower 16 bits of the mask. */ + if (p - buffer < 4 && (best->match & 0xFFFF) != 0) + p = buffer + 4; + + /* lpstop is another exception. It takes a one word argument but is + three words long. */ + if (p - buffer < 6 + && (best->match & 0xffff) == 0xffff + && args[0] == '#' + && args[1] == 'w') + { + /* Copy the one word argument into the usual location for a one + word argument, to simplify printing it. We can get away with + this because we know exactly what the second word is, and we + aren't going to print anything based on it. */ + p = buffer + 6; + if (!FETCH_DATA (info, p)) + return -1; + buffer[2] = buffer[4]; + buffer[3] = buffer[5]; + } - /* Generate the text for the index register. - Where this will be output is not yet determined. */ - sprintf (buf, "[%s.%c%s]", - reg_names[(word >> 12) & 0xf], - (word & 0x800) ? 'l' : 'w', - scales[(word >> 9) & 3]); + if (!FETCH_DATA (info, p)) + return -1; - /* Handle the 68000 style of indexing. */ + save_p = p; + info->print_address_func = dummy_print_address; + info->fprintf_func = (fprintf_ftype) dummy_printer; - if ((word & 0x100) == 0) + /* We scan the operands twice. The first time we don't print anything, + but look for errors. */ + for (d = args; *d; d += 2) { - print_base (basereg, - ((word & 0x80) ? word | 0xff00 : word & 0xff) - + ((basereg == -1) ? addr : 0), - info); - (*info->fprintf_func) (info->stream, "%s", buf); - return p; + int eaten = print_insn_arg (d, buffer, p, memaddr + (p - buffer), info); + + if (eaten >= 0) + p += eaten; + else if (eaten == PRINT_INSN_ARG_INVALID_OPERAND + || eaten == PRINT_INSN_ARG_MEMORY_ERROR) + { + info->fprintf_func = save_printer; + info->print_address_func = save_print_address; + return eaten == PRINT_INSN_ARG_MEMORY_ERROR ? -1 : 0; + } + else + { + /* We must restore the print functions before trying to print the + error message. */ + info->fprintf_func = save_printer; + info->print_address_func = save_print_address; + info->fprintf_func (info->stream, + /* xgettext:c-format */ + _("\n"), + best->name, best->args); + return 2; + } } - /* Handle the generalized kind. */ - /* First, compute the displacement to add to the base register. */ + p = save_p; + info->fprintf_func = save_printer; + info->print_address_func = save_print_address; - if (word & 0200) - basereg = -2; - if (word & 0100) - buf[0] = 0; - base_disp = 0; - switch ((word >> 4) & 3) + d = args; + + info->fprintf_func (info->stream, "%s", best->name); + + if (*d) + info->fprintf_func (info->stream, " "); + + while (*d) { - case 2: - base_disp = NEXTWORD (p); - break; - case 3: - base_disp = NEXTLONG (p); + p += print_insn_arg (d, buffer, p, memaddr + (p - buffer), info); + d += 2; + + if (*d && *(d - 2) != 'I' && *d != 'k') + info->fprintf_func (info->stream, ","); } - if (basereg == -1) - base_disp += addr; - /* Handle single-level case (not indirect) */ + return p - buffer; +} + +/* Try to interpret the instruction at address MEMADDR as one that + can execute on a processor with the features given by ARCH_MASK. + If successful, print the instruction to INFO->STREAM and return + its length in bytes. Return 0 otherwise. Return -1 on memory + error. */ - if ((word & 7) == 0) +static int +m68k_scan_mask (bfd_vma memaddr, disassemble_info *info, + unsigned int arch_mask) +{ + int i; + const char *d; + static const struct m68k_opcode **opcodes[16]; + static int numopcodes[16]; + int val; + int major_opcode; + + struct private *priv = (struct private *) info->private_data; + bfd_byte *buffer = priv->the_buffer; + + if (!opcodes[0]) { - print_base (basereg, base_disp, info); - (*info->fprintf_func) (info->stream, "%s", buf); - return p; + /* Speed up the matching by sorting the opcode + table on the upper four bits of the opcode. */ + const struct m68k_opcode **opc_pointer[16]; + + /* First count how many opcodes are in each of the sixteen buckets. */ + for (i = 0; i < m68k_numopcodes; i++) + numopcodes[(m68k_opcodes[i].opcode >> 28) & 15]++; + + /* Then create a sorted table of pointers + that point into the unsorted table. */ + opc_pointer[0] = xmalloc (sizeof (struct m68k_opcode *) + * m68k_numopcodes); + opcodes[0] = opc_pointer[0]; + + for (i = 1; i < 16; i++) + { + opc_pointer[i] = opc_pointer[i - 1] + numopcodes[i - 1]; + opcodes[i] = opc_pointer[i]; + } + + for (i = 0; i < m68k_numopcodes; i++) + *opc_pointer[(m68k_opcodes[i].opcode >> 28) & 15]++ = &m68k_opcodes[i]; } - /* Two level. Compute displacement to add after indirection. */ + if (!FETCH_DATA (info, buffer + 2)) + return -1; + major_opcode = (buffer[0] >> 4) & 15; - outer_disp = 0; - switch (word & 3) + for (i = 0; i < numopcodes[major_opcode]; i++) { - case 2: - outer_disp = NEXTWORD (p); - break; - case 3: - outer_disp = NEXTLONG (p); - } + const struct m68k_opcode *opc = opcodes[major_opcode][i]; + unsigned long opcode = opc->opcode; + unsigned long match = opc->match; + const char *args = opc->args; - (*info->fprintf_func) (info->stream, "%d(", outer_disp); - print_base (basereg, base_disp, info); + if (*args == '.') + args++; - /* If postindexed, print the closeparen before the index. */ - if (word & 4) - (*info->fprintf_func) (info->stream, ")%s", buf); - /* If preindexed, print the closeparen after the index. */ - else - (*info->fprintf_func) (info->stream, "%s)", buf); + if (((0xff & buffer[0] & (match >> 24)) == (0xff & (opcode >> 24))) + && ((0xff & buffer[1] & (match >> 16)) == (0xff & (opcode >> 16))) + /* Only fetch the next two bytes if we need to. */ + && (((0xffff & match) == 0) + || + (FETCH_DATA (info, buffer + 4) + && ((0xff & buffer[2] & (match >> 8)) == (0xff & (opcode >> 8))) + && ((0xff & buffer[3] & match) == (0xff & opcode))) + ) + && (opc->arch & arch_mask) != 0) + { + /* Don't use for printout the variants of divul and divsl + that have the same register number in two places. + The more general variants will match instead. */ + for (d = args; *d; d += 2) + if (d[1] == 'D') + break; - return p; + /* Don't use for printout the variants of most floating + point coprocessor instructions which use the same + register number in two places, as above. */ + if (*d == '\0') + for (d = args; *d; d += 2) + if (d[1] == 't') + break; + + /* Don't match fmovel with more than one register; + wait for fmoveml. */ + if (*d == '\0') + { + for (d = args; *d; d += 2) + { + if (d[0] == 's' && d[1] == '8') + { + val = fetch_arg (buffer, d[1], 3, info); + if (val < 0) + return 0; + if ((val & (val - 1)) != 0) + break; + } + } + } + + /* Don't match FPU insns with non-default coprocessor ID. */ + if (*d == '\0') + { + for (d = args; *d; d += 2) + { + if (d[0] == 'I') + { + val = fetch_arg (buffer, 'd', 3, info); + if (val != 1) + break; + } + } + } + + if (*d == '\0') + if ((val = match_insn_m68k (memaddr, info, opc))) + return val; + } + } + return 0; } -/* Print a base register REGNO and displacement DISP, on INFO->STREAM. - REGNO = -1 for pc, -2 for none (suppressed). */ +/* Print the m68k instruction at address MEMADDR in debugged memory, + on INFO->STREAM. Returns length of the instruction, in bytes. */ -static void -print_base (regno, disp, info) - int regno; - int disp; - disassemble_info *info; +int +print_insn_m68k (bfd_vma memaddr, disassemble_info *info) { - if (regno == -2) - (*info->fprintf_func) (info->stream, "%d", disp); - else if (regno == -1) - (*info->fprintf_func) (info->stream, "0x%x", (unsigned) disp); + unsigned int arch_mask; + struct private priv; + int val; + + bfd_byte *buffer = priv.the_buffer; + + info->private_data = & priv; + /* Tell objdump to use two bytes per chunk + and six bytes per line for displaying raw data. */ + info->bytes_per_chunk = 2; + info->bytes_per_line = 6; + info->display_endian = BFD_ENDIAN_BIG; + priv.max_fetched = priv.the_buffer; + priv.insn_start = memaddr; + + arch_mask = bfd_m68k_mach_to_features (info->mach); + if (!arch_mask) + { + /* First try printing an m680x0 instruction. Try printing a Coldfire + one if that fails. */ + val = m68k_scan_mask (memaddr, info, m68k_mask); + if (val <= 0) + val = m68k_scan_mask (memaddr, info, mcf_mask); + } else - (*info->fprintf_func) (info->stream, "%d(%s)", disp, reg_names[regno]); + { + val = m68k_scan_mask (memaddr, info, arch_mask); + } + + if (val == 0) + /* Handle undefined instructions. */ + info->fprintf_func (info->stream, ".short 0x%04x", (buffer[0] << 8) + buffer[1]); + + return val ? val : 2; }