X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Fm68k-opc.c;h=f635c6c230edea35d39db0b57d916260090942fb;hb=d87a1542821ef7fe70da4ad1331c628c75836c4e;hp=3b488501e4939e13279f3b505af7337845345996;hpb=0dd19a8f36c712e5ce780ad0cfafdec1c456baa6;p=deliverable%2Fbinutils-gdb.git

diff --git a/opcodes/m68k-opc.c b/opcodes/m68k-opc.c
index 3b488501e4..f635c6c230 100644
--- a/opcodes/m68k-opc.c
+++ b/opcodes/m68k-opc.c
@@ -1,5 +1,5 @@
-/* Opcode table for m680[01234]0/m6888[12]/m68851.
-   Copyright 1989, 91, 92, 93, 94, 95, 1996 Free Software Foundation.
+/* Opcode table for m680[012346]0/m6888[12]/m68851/mcf5200.
+   Copyright 1989, 91, 92, 93, 94, 95, 96, 1997 Free Software Foundation.
 
 This file is part of GDB, GAS, and the GNU binutils.
 
@@ -256,7 +256,6 @@ const struct m68k_opcode m68k_opcodes[] =
 {"cmpib",	one(0006000),	one(0177700), "#b;s", m68000up },
 {"cmpiw",	one(0006100),	one(0177700), "#w;s", m68000up },
 {"cmpil",	one(0006200),	one(0177700), "#l;s", m68000up },
-{"cmpil",	one(0006200),	one(0177700), "#l;s", m68000up },
 {"cmpil",	one(0006200),	one(0177700), "#lDs", mcf5200 },
 
 {"cmpmb",	one(0130410),	one(0170770), "+s+d", m68000up },
@@ -886,11 +885,9 @@ const struct m68k_opcode m68k_opcodes[] =
 {"fremx",	two(0xF000, 0x0025), two(0xF1C0, 0xE07F), "IiF8F7", mfloat },
 {"fremx",	two(0xF000, 0x4825), two(0xF1C0, 0xFC7F), "Ii;xF7", mfloat },
 
-{"frestore",	one(0xF140),		one(0xF1C0), "Id&s", mfloat },
-{"frestore",	one(0xF158),		one(0xF1F8), "Id+s", mfloat },
+{"frestore",	one(0xF140),		one(0xF1C0), "Id<s", mfloat },
 
-{"fsave",	one(0xF100),		one(0xF1C0), "Id&s", mfloat },
-{"fsave",	one(0xF120),		one(0xF1F8), "Id-s", mfloat },
+{"fsave",	one(0xF100),		one(0xF1C0), "Id>s", mfloat },
 
 {"fscaleb",	two(0xF000, 0x5826), two(0xF1C0, 0xFC7F), "Ii;bF7", mfloat },
 {"fscaled",	two(0xF000, 0x5426), two(0xF1C0, 0xFC7F), "Ii;FF7", mfloat },
@@ -1233,6 +1230,23 @@ const struct m68k_opcode m68k_opcodes[] =
 {"lsrl",	one(0160210),	one(0170770), "QdDs", m68000up | mcf5200 },
 {"lsrl",	one(0160250),	one(0170770), "DdDs", m68000up | mcf5200 },
 
+/* NOTE: The mcf5200 family programmer's reference manual does not 
+   indicate the byte form of the movea instruction is invalid (as it
+   is on 68000 family cpus).  However, experiments on the 5202 yeild
+   unexpected results.  The value is copied, but it is not sign extended
+   (as is done with movea.w) and the top three bytes in the address 
+   register are not disturbed.  I don't know if this is the intended
+   behavior --- it could be a hole in instruction decoding (Motorola
+   decided not to trap all invalid instructions for performance reasons)
+   --- but I suspect that it is not.   
+
+   I reported this to Motorola ISD Technical Communications Support, 
+   which replied that other coldfire assemblers reject movea.b.  For 
+   this reason I've decided to not allow moveab. 
+
+	jtc@cygnus.com - 97/01/24
+ */
+
 {"moveal",	one(0020100),	one(0170700), "*lAd", m68000up | mcf5200 },
 {"moveaw",	one(0030100),	one(0170700), "*wAd", m68000up | mcf5200 },
 
@@ -1243,20 +1257,23 @@ const struct m68k_opcode m68k_opcodes[] =
 
 {"movemw",	one(0044200),	one(0177700), "Lw&s", m68000up },
 {"movemw",	one(0044240),	one(0177770), "lw-s", m68000up },
-{"movemw",	one(0046200),	one(0177700), "!sLw", m68000up },
-{"movemw",	one(0046230),	one(0177770), "+sLw", m68000up },
-{"movemw",	one(0044200),	one(0177700), "#w&s", m68000up },
-{"movemw",	one(0044240),	one(0177770), "#w-s", m68000up },
-{"movemw",	one(0046200),	one(0177700), "!s#w", m68000up },
-{"movemw",	one(0046230),	one(0177770), "+s#w", m68000up },
-{"moveml",	one(0044300),	one(0177700), "Lw&s", m68000up | mcf5200 },
-{"moveml",	one(0044340),	one(0177770), "lw-s", m68000up | mcf5200 },
-{"moveml",	one(0046300),	one(0177700), "!sLw", m68000up | mcf5200 },
-{"moveml",	one(0046330),	one(0177770), "+sLw", m68000up | mcf5200 },
-{"moveml",	one(0044300),	one(0177700), "#w&s", m68000up | mcf5200 },
-{"moveml",	one(0044340),	one(0177770), "#w-s", m68000up | mcf5200 },
-{"moveml",	one(0046300),	one(0177700), "!s#w", m68000up | mcf5200 },
-{"moveml",	one(0046330),	one(0177770), "+s#w", m68000up | mcf5200 },
+{"movemw",	one(0044200),	one(0177700), "#w>s", m68000up },
+{"movemw",	one(0046200),	one(0177700), "<sLw", m68000up },
+{"movemw",	one(0046200),	one(0177700), "<s#w", m68000up },
+{"moveml",	one(0044300),	one(0177700), "Lw&s", m68000up },
+{"moveml",	one(0044340),	one(0177770), "lw-s", m68000up },
+{"moveml",	one(0044300),	one(0177700), "#w>s", m68000up },
+{"moveml",	one(0046300),	one(0177700), "<sLw", m68000up },
+{"moveml",	one(0046300),	one(0177700), "<s#w", m68000up },
+/* FIXME: need specifier for mode 2 and 5 to simplify below insn patterns */
+{"moveml",	one(0044320),	one(0177770), "Lwas", mcf5200 },
+{"moveml",	one(0044320),	one(0177770), "#was", mcf5200 },
+{"moveml",	one(0044350),	one(0177770), "Lwds", mcf5200 },
+{"moveml",	one(0044350),	one(0177770), "#wds", mcf5200 },
+{"moveml",	one(0046320),	one(0177770), "asLw", mcf5200 },
+{"moveml",	one(0046320),	one(0177770), "as#w", mcf5200 },
+{"moveml",	one(0046350),	one(0177770), "dsLw", mcf5200 },
+{"moveml",	one(0046350),	one(0177770), "ds#w", mcf5200 },
 
 {"movepw",	one(0000410),	one(0170770), "dsDd", m68000up },
 {"movepw",	one(0000610),	one(0170770), "Ddds", m68000up },
@@ -1264,11 +1281,18 @@ const struct m68k_opcode m68k_opcodes[] =
 {"movepl",	one(0000710),	one(0170770), "Ddds", m68000up },
 
 {"moveq",	one(0070000),	one(0170400), "MsDd", m68000up | mcf5200 },
+{"moveq",	one(0070000),	one(0170400), "#BDd", m68000up | mcf5200 },
 
 /* The move opcode can generate the movea and moveq instructions.  */
 {"moveb",	one(0010000),	one(0170000), ";b$d", m68000up },
-
-{"movew",	one(0030000),	one(0170000), "*w%d", m68000up | mcf5200 },
+{"moveb",	one(0010000),	one(0170000), "ms$d", mcf5200 },
+{"moveb",	one(0010000),	one(0170000), "nspd", mcf5200 },
+{"moveb",	one(0010000),	one(0170000), "obmd", mcf5200 },
+
+{"movew",	one(0030000),	one(0170000), "*w%d", m68000up },
+{"movew",	one(0030000),	one(0170000), "ms%d", mcf5200 },
+{"movew",	one(0030000),	one(0170000), "nspd", mcf5200 },
+{"movew",	one(0030000),	one(0170000), "owmd", mcf5200 },
 {"movew",	one(0040300),	one(0177700), "Ss$s", m68000up },
 {"movew",	one(0040300),	one(0177770), "SsDs", mcf5200 },
 {"movew",	one(0041300),	one(0177700), "Cs$s", m68010up },
@@ -1281,11 +1305,17 @@ const struct m68k_opcode m68k_opcodes[] =
 {"movew",	one(0043300),	one(0177700), "#wSd", mcf5200 },
 
 {"movel",	one(0070000),	one(0170400), "MsDd", m68000up | mcf5200 },
-{"movel",	one(0020000),	one(0170000), "*l%d", m68000up | mcf5200 },
+{"movel",	one(0020000),	one(0170000), "*l%d", m68000up },
+{"movel",	one(0020000),	one(0170000), "ms%d", mcf5200 },
+{"movel",	one(0020000),	one(0170000), "nspd", mcf5200 },
+{"movel",	one(0020000),	one(0170000), "olmd", mcf5200 },
 {"movel",	one(0047140),	one(0177770), "AsUd", m68000up },
 {"movel",	one(0047150),	one(0177770), "UdAs", m68000up },
 
-{"move",	one(0030000),	one(0170000), "*w%d", m68000up | mcf5200 },
+{"move",	one(0030000),	one(0170000), "*w%d", m68000up },
+{"move",	one(0030000),	one(0170000), "ms%d", mcf5200 },
+{"move",	one(0030000),	one(0170000), "nspd", mcf5200 },
+{"move",	one(0030000),	one(0170000), "owmd", mcf5200 },
 {"move",	one(0040300),	one(0177700), "Ss$s", m68000up },
 {"move",	one(0040300),	one(0177770), "SsDs", mcf5200 },
 {"move",	one(0041300),	one(0177700), "Cs$s", m68010up },
@@ -1314,11 +1344,21 @@ const struct m68k_opcode m68k_opcodes[] =
 {"move16",	one(0xf618),		one(0xfff8), "_Las", m68040up },
 
 {"mulsw",	one(0140700),		one(0170700), ";wDd", m68000up|mcf5200 },
-{"mulsl",	two(0046000,004000), two(0177700,0107770), ";lD1", m68020up|cpu32|mcf5200 },
+{"mulsl",	two(0046000,004000), two(0177700,0107770), ";lD1", m68020up|cpu32 },
+{"mulsl",	two(0046000,004000), two(0177700,0107770), "DsD1", mcf5200 },
+{"mulsl",	two(0046000,004000), two(0177700,0107770), "asD1", mcf5200 },
+{"mulsl",	two(0046000,004000), two(0177700,0107770), "+sD1", mcf5200 },
+{"mulsl",	two(0046000,004000), two(0177700,0107770), "-sD1", mcf5200 },
+{"mulsl",	two(0046000,004000), two(0177700,0107770), "dsD1", mcf5200 },
 {"mulsl",	two(0046000,006000), two(0177700,0107770), ";lD3D1",m68020up|cpu32 },
 
 {"muluw",	one(0140300),		one(0170700), ";wDd", m68000up|mcf5200 },
-{"mulul",	two(0046000,000000), two(0177700,0107770), ";lD1", m68020up|cpu32|mcf5200 },
+{"mulul",	two(0046000,000000), two(0177700,0107770), ";lD1", m68020up|cpu32 },
+{"mulul",	two(0046000,000000), two(0177700,0107770), "DsD1", mcf5200 },
+{"mulul",	two(0046000,000000), two(0177700,0107770), "asD1", mcf5200 },
+{"mulul",	two(0046000,000000), two(0177700,0107770), "+sD1", mcf5200 },
+{"mulul",	two(0046000,000000), two(0177700,0107770), "-sD1", mcf5200 },
+{"mulul",	two(0046000,000000), two(0177700,0107770), "dsD1", mcf5200 },
 {"mulul",	two(0046000,002000), two(0177700,0107770), ";lD3D1",m68020up|cpu32 },
 
 {"nbcd",	one(0044000),	one(0177700), "$s", m68000up },
@@ -1479,11 +1519,9 @@ const struct m68k_opcode m68k_opcodes[] =
 {"pmovefd",	two(0xf000, 0x4100),	two(0xffc0, 0xe3ff), "|sW8", m68030 },
 {"pmovefd",	two(0xf000, 0x0900),	two(0xffc0, 0xfbff), "*l38", m68030 },
 
-{"prestore",	one(0xf140),		one(0xffc0), "&s", m68851 },
-{"prestore",	one(0xf158),		one(0xfff8), "+s", m68851 },
+{"prestore",	one(0xf140),		one(0xffc0), "<s", m68851 },
 
-{"psave",	one(0xf100),		one(0xffc0), "&s", m68851 },
-{"psave",	one(0xf120),		one(0xfff8), "-s", m68851 },
+{"psave",	one(0xf100),		one(0xffc0), ">s", m68851 },
 
 {"psac",	two(0xf040, 0x0007),	two(0xffc0, 0xffff), "$s", m68851 },
 {"psas",	two(0xf040, 0x0006),	two(0xffc0, 0xffff), "$s", m68851 },
@@ -1615,9 +1653,9 @@ const struct m68k_opcode m68k_opcodes[] =
 
 {"roxrb",	one(0160020),		one(0170770), "QdDs", m68000up },
 {"roxrb",	one(0160060),		one(0170770), "DdDs", m68000up },
-{"roxrw",	one(0160120),		one(0170770),"QdDs", m68000up },
+{"roxrw",	one(0160120),		one(0170770), "QdDs", m68000up },
 {"roxrw",	one(0160160),		one(0170770), "DdDs", m68000up },
-{"roxrw",	one(0162300),		one(0177700),"~s",   m68000up },
+{"roxrw",	one(0162300),		one(0177700), "~s",   m68000up },
 {"roxrl",	one(0160220),		one(0170770), "QdDs", m68000up },
 {"roxrl",	one(0160260),		one(0170770), "DdDs", m68000up },
 
@@ -1708,6 +1746,15 @@ const struct m68k_opcode m68k_opcodes[] =
 
 {"swap",	one(0044100),	one(0177770), "Ds", m68000up | mcf5200 },
 
+/* swbeg and swbegl are magic constants used on sysV68.  The compiler
+   generates them before a switch table.  They tell the debugger and
+   disassembler that a switch table follows.  The parameter is the
+   number of elements in the table.  swbeg means that the entries in
+   the table are word (2 byte) sized, and swbegl means that the
+   entries in the table are longword (4 byte) sized.  */
+{"swbeg",	one(0045374),	one(0177777), "#w",   m68000up | mcf5200 },
+{"swbegl",	one(0045375),	one(0177777), "#l",   m68000up | mcf5200 },
+
 {"tas",		one(0045300),		one(0177700), "$s", m68000up },
 
 #define TBL1(name,signed,round,size)					\
@@ -1777,9 +1824,12 @@ TBL("tblunb", "tblunw", "tblunl", 0, 0),
 
 {"trapv",	one(0047166),	one(0177777), "", m68000up },
 
-{"tstb",	one(0045000),	one(0177700), ";b", m68000up | mcf5200 },
-{"tstw",	one(0045100),	one(0177700), "*w", m68000up | mcf5200 },
-{"tstl",	one(0045200),	one(0177700), "*l", m68000up | mcf5200 },
+{"tstb",	one(0045000),	one(0177700), ";b", m68020up | mcf5200 },
+{"tstb",	one(0045000),	one(0177700), "@b", m68000up },
+{"tstw",	one(0045100),	one(0177700), "*w", m68020up | mcf5200 },
+{"tstw",	one(0045100),	one(0177700), "@w", m68000up },
+{"tstl",	one(0045200),	one(0177700), "*l", m68020up | mcf5200 },
+{"tstl",	one(0045200),	one(0177700), "@l", m68000up },
 
 {"unlk",	one(0047130),	one(0177770), "As", m68000up | mcf5200 },