X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Fmcore-dis.c;h=24bbff4c5c1ec6b181ecb6bc0157646fa03d9a19;hb=dea757d1a3f627b4ffda137db2b4a2195d5e46e9;hp=096cec9aec06a90e80a00c5f5c7dd382f83db3e6;hpb=72ec28b8afa357cdde70c612b4e0e9f37a34f8e4;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/mcore-dis.c b/opcodes/mcore-dis.c index 096cec9aec..24bbff4c5c 100644 --- a/opcodes/mcore-dis.c +++ b/opcodes/mcore-dis.c @@ -1,5 +1,5 @@ /* Disassemble Motorola M*Core instructions. - Copyright (C) 1993, 1999, 2000 Free Software Foundation, Inc. + Copyright 1993, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -13,8 +13,9 @@ GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ +#include "sysdep.h" #include #define STATIC_TABLE #define DEFINE_TABLE @@ -23,17 +24,16 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "dis-asm.h" /* Mask for each mcore_opclass: */ -static const unsigned short imsk[] = -{ +static const unsigned short imsk[] = { /* O0 */ 0xFFFF, /* OT */ 0xFFFC, /* O1 */ 0xFFF0, - /* OC */ 0xFFE0, + /* OC */ 0xFE00, /* O2 */ 0xFF00, /* X1 */ 0xFFF0, /* OI */ 0xFE00, /* OB */ 0xFE00, - + /* OMa */ 0xFFF0, /* SI */ 0xFE00, /* I7 */ 0xF800, @@ -42,7 +42,7 @@ static const unsigned short imsk[] = /* BL */ 0xFF00, /* LR */ 0xF000, /* LJ */ 0xFF00, - + /* RM */ 0xFFF0, /* RQ */ 0xFFF0, /* JSR */ 0xFFF0, @@ -51,33 +51,31 @@ static const unsigned short imsk[] = /* OBRb*/ 0xFF80, /* OBRc*/ 0xFF00, /* OBR2*/ 0xFE00, - + /* O1R1*/ 0xFFF0, /* OMb */ 0xFF80, /* OMc */ 0xFF00, /* SIa */ 0xFE00, - /* MULSH */ 0xFF00, + /* MULSH */ 0xFF00, /* OPSR */ 0xFFF8, /* psrset/psrclr */ - + /* JC */ 0, /* JC,JU,JL don't appear in object */ /* JU */ 0, /* JL */ 0, /* RSI */ 0, /* DO21*/ 0, - /* OB2 */ 0 /* OB2 won't appear in object. */ + /* OB2 */ 0 /* OB2 won't appear in object. */ }; -static const char * grname[] = -{ +static const char *grname[] = { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" }; static const char X[] = "??"; -static const char * crname[] = -{ +static const char *crname[] = { "psr", "vbr", "epsr", "fpsr", "epc", "fpc", "ss0", "ss1", "ss2", "ss3", "ss4", "gcr", "gsr", X, X, X, X, X, X, X, X, X, X, X, @@ -86,23 +84,23 @@ static const char * crname[] = static const unsigned isiz[] = { 2, 0, 1, 0 }; -int +int print_insn_mcore (memaddr, info) bfd_vma memaddr; - struct disassemble_info * info; + struct disassemble_info *info; { - unsigned char ibytes[4]; - fprintf_ftype fprintf = info->fprintf_func; - void * stream = info->stream; - unsigned short inst; - mcore_opcode_info * op; - int status; + unsigned char ibytes[4]; + fprintf_ftype fprintf = info->fprintf_func; + void *stream = info->stream; + unsigned short inst; + const mcore_opcode_info *op; + int status; info->bytes_per_chunk = 2; status = info->read_memory_func (memaddr, ibytes, 2, info); - if (status != 0) + if (status != 0) { info->memory_error_func (status, memaddr, info); return -1; @@ -116,7 +114,7 @@ print_insn_mcore (memaddr, info) abort (); /* Just a linear search of the table. */ - for (op = mcore_table; op->name != 0; op ++) + for (op = mcore_table; op->name != 0; op++) if (op->inst == (inst & imsk[op->opclass])) break; @@ -124,25 +122,54 @@ print_insn_mcore (memaddr, info) fprintf (stream, ".short 0x%04x", inst); else { - const char * name = grname[inst & 0x0F]; - + const char *name = grname[inst & 0x0F]; + fprintf (stream, "%s", op->name); - + switch (op->opclass) { - case O0: break; - case OT: fprintf (stream, "\t%d", inst & 0x3); break; + case O0: + break; + + case OT: + fprintf (stream, "\t%d", inst & 0x3); + break; + case O1: case JMP: - case JSR: fprintf (stream, "\t%s", name); break; - case OC: fprintf (stream, "\t%s, %s", name, crname[(inst >> 4) & 0x1F]); break; - case O1R1: fprintf (stream, "\t%s, r1", name); break; + case JSR: + fprintf (stream, "\t%s", name); + break; + + case OC: + fprintf (stream, "\t%s, %s", name, crname[(inst >> 4) & 0x1F]); + break; + + case O1R1: + fprintf (stream, "\t%s, r1", name); + break; + case MULSH: - case O2: fprintf (stream, "\t%s, %s", name, grname[(inst >> 4) & 0xF]); break; - case X1: fprintf (stream, "\tr1, %s", name); break; - case OI: fprintf (stream, "\t%s, %d", name, ((inst >> 4) & 0x1F) + 1); break; - case RM: fprintf (stream, "\t%s-r15, (r0)", name); break; - case RQ: fprintf (stream, "\tr4-r7, (%s)", name); break; + case O2: + fprintf (stream, "\t%s, %s", name, grname[(inst >> 4) & 0xF]); + break; + + case X1: + fprintf (stream, "\tr1, %s", name); + break; + + case OI: + fprintf (stream, "\t%s, %d", name, ((inst >> 4) & 0x1F) + 1); + break; + + case RM: + fprintf (stream, "\t%s-r15, (r0)", name); + break; + + case RQ: + fprintf (stream, "\tr4-r7, (%s)", name); + break; + case OB: case OBRa: case OBRb: @@ -151,26 +178,33 @@ print_insn_mcore (memaddr, info) case SIa: case OMa: case OMb: - case OMc: fprintf (stream, "\t%s, %d", name, (inst >> 4) & 0x1F); break; - case I7: fprintf (stream, "\t%s, %d", name, (inst >> 4) & 0x7F); break; - case LS: fprintf (stream, "\t%s, (%s, %d)", grname[(inst >> 8) & 0xF], - name, ((inst >> 4) & 0xF) << isiz[(inst >> 13) & 3]); + case OMc: + fprintf (stream, "\t%s, %d", name, (inst >> 4) & 0x1F); + break; + + case I7: + fprintf (stream, "\t%s, %d", name, (inst >> 4) & 0x7F); + break; + + case LS: + fprintf (stream, "\t%s, (%s, %d)", grname[(inst >> 8) & 0xF], + name, ((inst >> 4) & 0xF) << isiz[(inst >> 13) & 3]); break; - + case BR: { long val = inst & 0x3FF; - + if (inst & 0x400) val |= 0xFFFFFC00; - - fprintf (stream, "\t0x%x", memaddr + 2 + (val<<1)); - + + fprintf (stream, "\t0x%lx", (long)(memaddr + 2 + (val << 1))); + if (strcmp (op->name, "bsr") == 0) { - /* for bsr, we'll try to get a symbol for the target */ + /* For bsr, we'll try to get a symbol for the target. */ val = memaddr + 2 + (val << 1); - + if (info->print_address_func && val != 0) { fprintf (stream, "\t// "); @@ -179,53 +213,53 @@ print_insn_mcore (memaddr, info) } } break; - + case BL: { long val; val = (inst & 0x000F); - fprintf (stream, "\t%s, 0x%x", - grname[(inst >> 4) & 0xF], memaddr - (val << 1)); + fprintf (stream, "\t%s, 0x%lx", + grname[(inst >> 4) & 0xF], (long)(memaddr - (val << 1))); } break; - + case LR: { unsigned long val; - + val = (memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC; - + status = info->read_memory_func (val, ibytes, 4, info); - if (status != 0) + if (status != 0) { info->memory_error_func (status, memaddr, info); break; } - + if (info->endian == BFD_ENDIAN_LITTLE) val = (ibytes[3] << 24) | (ibytes[2] << 16) | (ibytes[1] << 8) | (ibytes[0]); else val = (ibytes[0] << 24) | (ibytes[1] << 16) | (ibytes[2] << 8) | (ibytes[3]); - + /* Removed [] around literal value to match ABI syntax 12/95. */ - fprintf (stream, "\t%s, 0x%X", grname[(inst >> 8) & 0xF], val); + fprintf (stream, "\t%s, 0x%lX", grname[(inst >> 8) & 0xF], val); if (val == 0) - fprintf (stream, "\t// from address pool at 0x%x", - (memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC); + fprintf (stream, "\t// from address pool at 0x%lx", + (long)(memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC); } break; - + case LJ: { unsigned long val; - + val = (memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC; - + status = info->read_memory_func (val, ibytes, 4, info); - if (status != 0) + if (status != 0) { info->memory_error_func (status, memaddr, info); break; @@ -237,9 +271,9 @@ print_insn_mcore (memaddr, info) else val = (ibytes[0] << 24) | (ibytes[1] << 16) | (ibytes[2] << 8) | (ibytes[3]); - + /* Removed [] around literal value to match ABI syntax 12/95. */ - fprintf (stream, "\t0x%X", val); + fprintf (stream, "\t0x%lX", val); /* For jmpi/jsri, we'll try to get a symbol for the target. */ if (info->print_address_func && val != 0) { @@ -248,31 +282,30 @@ print_insn_mcore (memaddr, info) } else { - fprintf (stream, "\t// from address pool at 0x%x", - (memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC); + fprintf (stream, "\t// from address pool at 0x%lx", + (long)(memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC); } } break; - + case OPSR: { - static char * fields[] = - { - "af", "ie", "fe", "fe,ie", + static char *fields[] = { + "af", "ie", "fe", "fe,ie", "ee", "ee,ie", "ee,fe", "ee,fe,ie" }; - + fprintf (stream, "\t%s", fields[inst & 0x7]); } break; - + default: - /* if the disassembler lags the instruction set */ + /* If the disassembler lags the instruction set. */ fprintf (stream, "\tundecoded operands, inst is 0x%04x", inst); break; } } - - /* Say how many bytes we consumed? */ + + /* Say how many bytes we consumed. */ return 2; }