X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Fmcore-opc.h;h=b8f0cce50a7cf514091fa3d3a1bd12851949217b;hb=4713453b1e6866c908ee95678a44c371cc6cf208;hp=856f78b617c7c2f154475e4dc9583ff204e8b89c;hpb=3f230321daaad517b4203d19e90ebc3b63b43a42;p=deliverable%2Fbinutils-gdb.git

diff --git a/opcodes/mcore-opc.h b/opcodes/mcore-opc.h
index 856f78b617..b8f0cce50a 100644
--- a/opcodes/mcore-opc.h
+++ b/opcodes/mcore-opc.h
@@ -1,5 +1,5 @@
-/* Assembler instructions for Motorolla's Mcore processor
-   Copyright (C) 1999 Free Software Foundation, Inc.
+/* Assembler instructions for Motorola's Mcore processor
+   Copyright 1999, 2000, 2002 Free Software Foundation, Inc.
 
    
 This program is free software; you can redistribute it and/or modify
@@ -14,7 +14,7 @@ GNU General Public License for more details.
 
 You should have received a copy of the GNU General Public License
 along with this program; if not, write to the Free Software
-Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
 
 #include "ansidecl.h"
 
@@ -24,9 +24,7 @@ typedef enum
   OMa,   SI,   I7,   LS,   BR,    BL,    LR,    LJ,
   RM,    RQ,   JSR,  JMP,  OBRa,  OBRb,  OBRc,  OBR2,
   O1R1,  OMb,  OMc,  SIa,
-  /* start-sanitize-m340 */  
-  MULSH,
-  /* end-sanitize-m340 */  
+  MULSH, OPSR,
   JC,    JU,   JL,   RSI,  DO21,  OB2
 }
 mcore_opclass;
@@ -41,7 +39,7 @@ typedef struct inst
 mcore_opcode_info;
 
 #ifdef DEFINE_TABLE
-mcore_opcode_info mcore_table[] =
+const mcore_opcode_info mcore_table[] =
 {
   { "bkpt",	O0,	0,	0x0000 },
   { "sync",	O0,	0,	0x0001 },
@@ -51,9 +49,7 @@ mcore_opcode_info mcore_table[] =
   { "stop",	O0,	0,	0x0004 },
   { "wait",	O0,	0,	0x0005 },
   { "doze",	O0,	0,	0x0006 },
-  /* start-sanitize-m340 */
   { "idly4",    O0,     0,      0x0007 },
-  /* end-sanitize-m340 */
   { "trap",	OT,	0,	0x0008 },
 /* SPACE:                       0x000C - 0x000F */
 /* SPACE:                       0x0010 - 0x001F */
@@ -105,6 +101,8 @@ mcore_opcode_info mcore_table[] =
   { "tst",	O2,	0,	0x0E00 },
   { "cmpne",	O2,	0,	0x0F00 },
   { "mfcr",	OC,	0,	0x1000 },
+  { "psrclr",	OPSR,	0,	0x11F0 },
+  { "psrset",	OPSR,	0,	0x11F8 },
   { "mov",	O2,	0,	0x1200 },
   { "bgenr",	O2,	0,	0x1300 },
   { "rsub",	O2,	0,	0x1400 },
@@ -115,6 +113,7 @@ mcore_opcode_info mcore_table[] =
   { "asr",	O2,	0,	0x1A00 },
   { "lsl",	O2,	0,	0x1B00 },
   { "addu",	O2,	0,	0x1C00 },
+  { "add",	O2,	0,	0x1C00 }, /* Official alias.  */
   { "ixh",	O2,	0,	0x1D00 },
   { "or",	O2,	0,	0x1E00 },
   { "andn",	O2,	0,	0x1F00 },
@@ -152,10 +151,8 @@ mcore_opcode_info mcore_table[] =
   { "movi",	I7,	0,	0x6000 },
 #define MCORE_INST_BMASKI_ALT	0x6000
 #define MCORE_INST_BGENI_ALT	0x6000
-/* start-sanitize-m340 */
   { "mulsh",    MULSH,  0,      0x6800 },
   { "muls.h",   MULSH,  0,      0x6800 },
-/* end-sanitize-m340 */
 /* SPACE:                       0x6900 - 0x6FFF */
   { "jmpi",	LJ,	1,	0x7000 },
   { "jsri",	LJ,	0,	0x7F00 },