X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Fmep-opc.c;h=612d722f4b1af4e28d7d052c6abbf0a146698845;hb=50d036364fb2a71b3ac9a0b0cdbe58296832a1b2;hp=bd298cb38cbcca54344b08c19eedece100f98e9e;hpb=40493983ad5cdac9625b3f2a1f92e41e094fde4c;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/mep-opc.c b/opcodes/mep-opc.c index bd298cb38c..612d722f4b 100644 --- a/opcodes/mep-opc.c +++ b/opcodes/mep-opc.c @@ -1,8 +1,9 @@ +/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */ /* Instruction opcode table for mep. THIS FILE IS MACHINE GENERATED WITH CGEN. -Copyright 1996-2007 Free Software Foundation, Inc. +Copyright (C) 1996-2020 Free Software Foundation, Inc. This file is part of the GNU Binutils and/or GDB, the GNU debugger. @@ -57,6 +58,10 @@ init_mep_all_cop_isas_mask (void) return; cgen_bitset_init (& mep_all_cop_isas_mask, ISA_MAX); /* begin-all-cop-isas */ + cgen_bitset_add (& mep_all_cop_isas_mask, ISA_EXT_COP1_16); + cgen_bitset_add (& mep_all_cop_isas_mask, ISA_EXT_COP1_32); + cgen_bitset_add (& mep_all_cop_isas_mask, ISA_EXT_COP1_48); + cgen_bitset_add (& mep_all_cop_isas_mask, ISA_EXT_COP1_64); /* end-all-cop-isas */ } @@ -87,10 +92,12 @@ mep_insn_supported_by_isa (const CGEN_INSN *insn, CGEN_ATTR_VALUE_BITSET_TYPE *i mep_config_map_struct mep_config_map[] = { /* config-map-start */ - /* Default entry: mep core only, all options enabled. */ - { "", 0, EF_MEP_CPU_C5, 1, 0, {1,"\x0"}, {1,"\x0"}, {1,"\x0"}, {1,"\x0"}, {1,"\x0"}, {1,"\x80"}, OPTION_MASK }, - { "default", CONFIG_DEFAULT, EF_MEP_CPU_C5, 0, 0, { 1, "\x0" }, { 1, "\x0" }, { 1, "\x0" }, { 1, "\x0" }, { 1, "\x0" }, { 1, "\xc0" }, + /* Default entry: first module, with all options enabled. */ + { "", 0, EF_MEP_COP_IVC2 | EF_MEP_CPU_C5,0, 64, { 1, "\x20" }, { 1, "\x10" }, { 1, "\x8" }, { 1, "\x4" }, { 1, "\x3c" }, { 1, "\xc0" }, OPTION_MASK | (1 << CGEN_INSN_OPTIONAL_DSP_INSN) | (1 << CGEN_INSN_OPTIONAL_UCI_INSN) }, + { "default", CONFIG_DEFAULT, EF_MEP_COP_IVC2 | EF_MEP_CPU_C5, 0, 64, { 1, "\x20" }, { 1, "\x10" }, { 1, "\x8" }, { 1, "\x4" }, { 1, "\x3c" }, { 1, "\xc0" }, 0 + | (1 << CGEN_INSN_OPTIONAL_CP_INSN) + | (1 << CGEN_INSN_OPTIONAL_CP64_INSN) | (1 << CGEN_INSN_OPTIONAL_MUL_INSN) | (1 << CGEN_INSN_OPTIONAL_DIV_INSN) | (1 << CGEN_INSN_OPTIONAL_BIT_INSN) @@ -111,7 +118,7 @@ check_configured_mach (int machs) { /* All base insns are supported. */ int mach = 1 << MACH_BASE; - switch (MEP_CPU) + switch (MEP_CPU & EF_MEP_CPU_MASK) { case EF_MEP_CPU_C2: case EF_MEP_CPU_C3: @@ -142,7 +149,7 @@ mep_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn) /* If the insn has an option bit set that we don't want, reject it. */ - if (CGEN_INSN_ATTRS (insn)->bool & OPTION_MASK & ~MEP_OMASK) + if (CGEN_INSN_ATTRS (insn)->bool_ & OPTION_MASK & ~MEP_OMASK) return 0; /* If attributes are absent, assume no restriction. */ @@ -157,6 +164,20 @@ mep_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn) return (ok1 && ok2 && ok3); } + +int +mep_cgen_insn_supported_asm (CGEN_CPU_DESC cd, const CGEN_INSN *insn) +{ +#ifdef MEP_IVC2_SUPPORTED + /* If we're assembling VLIW packets, ignore the 12-bit BSR as we + can't relax that. The 24-bit BSR is matched instead. */ + if (insn->base->num == MEP_INSN_BSR12 + && cgen_bitset_contains (cd->isas, ISA_EXT_COP1_64)) + return 0; +#endif + + return mep_cgen_insn_supported (cd, insn); +} /* The hash functions are recorded here to help keep assembler code out of the disassembler and vice versa. */ @@ -167,11 +188,7 @@ static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT); /* Instruction formats. */ -#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) #define F(f) & mep_cgen_ifld_table[MEP_##f] -#else -#define F(f) & mep_cgen_ifld_table[MEP_/**/f] -#endif static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = { 0, 0, 0x0, { { 0 } } }; @@ -212,6 +229,14 @@ static const CGEN_IFMT ifmt_dsp ATTRIBUTE_UNUSED = { 32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16U16) }, { 0 } } }; +static const CGEN_IFMT ifmt_dsp0 ATTRIBUTE_UNUSED = { + 32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_C5_RNMUIMM24) }, { F (F_SUB4) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_dsp1 ATTRIBUTE_UNUSED = { + 32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_C5_RMUIMM20) }, { F (F_SUB4) }, { 0 } } +}; + static const CGEN_IFMT ifmt_sb ATTRIBUTE_UNUSED = { 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } }; @@ -420,18 +445,146 @@ static const CGEN_IFMT ifmt_sim_syscall ATTRIBUTE_UNUSED = { 16, 16, 0xf8ef, { { F (F_MAJOR) }, { F (F_4) }, { F (F_CALLNUM) }, { F (F_8) }, { F (F_9) }, { F (F_10) }, { F (F_SUB4) }, { 0 } } }; +static const CGEN_IFMT ifmt_cmov_crn_rm ATTRIBUTE_UNUSED = { + 32, 32, 0xf00ffff7, { { F (F_MAJOR) }, { F (F_CRNX) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_IVC2_4U16) }, { F (F_IVC2_4U20) }, { F (F_IVC2_4U24) }, { F (F_29) }, { F (F_30) }, { F (F_31) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmovc_ccrn_rm ATTRIBUTE_UNUSED = { + 32, 32, 0xf00ffff3, { { F (F_MAJOR) }, { F (F_IVC2_CCRN_C3) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_IVC2_4U16) }, { F (F_IVC2_4U20) }, { F (F_IVC2_4U24) }, { F (F_30) }, { F (F_31) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmov_crn_rm_p0 ATTRIBUTE_UNUSED = { + 32, 32, 0xfff7ff, { { F (F_IVC2_CRNX) }, { F (F_IVC2_CRM) }, { F (F_IVC2_CMOV1) }, { F (F_21) }, { F (F_IVC2_CMOV2) }, { F (F_IVC2_CMOV3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cmovc_ccrn_rm_p0 ATTRIBUTE_UNUSED = { + 32, 32, 0xfff3ff, { { F (F_IVC2_CCRN) }, { F (F_IVC2_CRM) }, { F (F_IVC2_CMOV1) }, { F (F_IVC2_CMOV2) }, { F (F_IVC2_CMOV3) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpadd3_b_C3 ATTRIBUTE_UNUSED = { + 32, 32, 0xfe0ff801, { { F (F_MAJOR) }, { F (F_IVC2_3U4) }, { F (F_IVC2_5U7) }, { F (F_SUB4) }, { F (F_IVC2_5U16) }, { F (F_IVC2_5U21) }, { F (F_IVC2_5U26) }, { F (F_IVC2_1U31) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpfsftbi_C3 ATTRIBUTE_UNUSED = { + 32, 32, 0xf00ff801, { { F (F_MAJOR) }, { F (F_IVC2_3U4) }, { F (F_IVC2_5U7) }, { F (F_SUB4) }, { F (F_IVC2_5U16) }, { F (F_IVC2_5U21) }, { F (F_IVC2_5U26) }, { F (F_IVC2_1U31) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpmovfrcsar0_C3 ATTRIBUTE_UNUSED = { + 32, 32, 0xfe0fffff, { { F (F_MAJOR) }, { F (F_IVC2_3U4) }, { F (F_IVC2_5U7) }, { F (F_SUB4) }, { F (F_IVC2_5U16) }, { F (F_IVC2_5U21) }, { F (F_IVC2_5U26) }, { F (F_IVC2_1U31) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpmovtocsar0_C3 ATTRIBUTE_UNUSED = { + 32, 32, 0xfffff83f, { { F (F_MAJOR) }, { F (F_IVC2_3U4) }, { F (F_IVC2_5U7) }, { F (F_SUB4) }, { F (F_IVC2_5U16) }, { F (F_IVC2_5U21) }, { F (F_IVC2_5U26) }, { F (F_IVC2_1U31) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpmov_C3 ATTRIBUTE_UNUSED = { + 32, 32, 0xfe0ff83f, { { F (F_MAJOR) }, { F (F_IVC2_3U4) }, { F (F_IVC2_5U7) }, { F (F_SUB4) }, { F (F_IVC2_5U16) }, { F (F_IVC2_5U21) }, { F (F_IVC2_5U26) }, { F (F_IVC2_1U31) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpcmpeqz_b_C3 ATTRIBUTE_UNUSED = { + 32, 32, 0xfffff801, { { F (F_MAJOR) }, { F (F_IVC2_3U4) }, { F (F_IVC2_5U7) }, { F (F_SUB4) }, { F (F_IVC2_5U16) }, { F (F_IVC2_5U21) }, { F (F_IVC2_5U26) }, { F (F_IVC2_1U31) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpsrli3_b_C3 ATTRIBUTE_UNUSED = { + 32, 32, 0xfc0ff801, { { F (F_MAJOR) }, { F (F_IVC2_2U4) }, { F (F_IVC2_3U6) }, { F (F_IVC2_3U9) }, { F (F_SUB4) }, { F (F_IVC2_5U16) }, { F (F_IVC2_5U21) }, { F (F_IVC2_5U26) }, { F (F_IVC2_1U31) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpsrli3_h_C3 ATTRIBUTE_UNUSED = { + 32, 32, 0xfc0ff801, { { F (F_MAJOR) }, { F (F_IVC2_2U4) }, { F (F_IVC2_2U6) }, { F (F_IVC2_4U8) }, { F (F_SUB4) }, { F (F_IVC2_5U16) }, { F (F_IVC2_5U21) }, { F (F_IVC2_5U26) }, { F (F_IVC2_1U31) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpsrli3_w_C3 ATTRIBUTE_UNUSED = { + 32, 32, 0xfc0ff801, { { F (F_MAJOR) }, { F (F_IVC2_2U4) }, { F (F_IVC2_1U6) }, { F (F_IVC2_5U7) }, { F (F_SUB4) }, { F (F_IVC2_5U16) }, { F (F_IVC2_5U21) }, { F (F_IVC2_5U26) }, { F (F_IVC2_1U31) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cdsrli3_C3 ATTRIBUTE_UNUSED = { + 32, 32, 0xfc0ff801, { { F (F_MAJOR) }, { F (F_IVC2_2U4) }, { F (F_IVC2_6U6) }, { F (F_SUB4) }, { F (F_IVC2_5U16) }, { F (F_IVC2_5U21) }, { F (F_IVC2_5U26) }, { F (F_IVC2_1U31) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpmovi_b_C3 ATTRIBUTE_UNUSED = { + 32, 32, 0xf00ff83f, { { F (F_MAJOR) }, { F (F_IVC2_8S4) }, { F (F_SUB4) }, { F (F_IVC2_5U16) }, { F (F_IVC2_5U21) }, { F (F_IVC2_5U26) }, { F (F_IVC2_1U31) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpmoviu_h_C3 ATTRIBUTE_UNUSED = { + 32, 32, 0xf00ff83f, { { F (F_MAJOR) }, { F (F_IVC2_8U4) }, { F (F_SUB4) }, { F (F_IVC2_5U16) }, { F (F_IVC2_5U21) }, { F (F_IVC2_5U26) }, { F (F_IVC2_1U31) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpsrlia1_P1 ATTRIBUTE_UNUSED = { + 32, 32, 0xfc0fffff, { { F (F_MAJOR) }, { F (F_IVC2_2U4) }, { F (F_IVC2_1U6) }, { F (F_IVC2_5U7) }, { F (F_SUB4) }, { F (F_IVC2_5U16) }, { F (F_IVC2_5U21) }, { F (F_IVC2_5U26) }, { F (F_IVC2_1U31) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_c0nop_P0_P0S ATTRIBUTE_UNUSED = { + 32, 32, 0xffffffff, { { F (F_IVC2_8U0) }, { F (F_IVC2_5U8) }, { F (F_IVC2_5U13) }, { F (F_IVC2_5U18) }, { F (F_IVC2_5U23) }, { F (F_IVC2_4U28) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpadd3_b_P0S_P1 ATTRIBUTE_UNUSED = { + 32, 32, 0xfff8000f, { { F (F_IVC2_8U0) }, { F (F_IVC2_5U8) }, { F (F_IVC2_5U13) }, { F (F_IVC2_5U18) }, { F (F_IVC2_5U23) }, { F (F_IVC2_4U28) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpmov_P0S_P1 ATTRIBUTE_UNUSED = { + 32, 32, 0xfff83e0f, { { F (F_IVC2_8U0) }, { F (F_IVC2_5U8) }, { F (F_IVC2_5U13) }, { F (F_IVC2_5U18) }, { F (F_IVC2_5U23) }, { F (F_IVC2_4U28) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpccadd_b_P0S_P1 ATTRIBUTE_UNUSED = { + 32, 32, 0xfff83fff, { { F (F_IVC2_8U0) }, { F (F_IVC2_5U8) }, { F (F_IVC2_5U13) }, { F (F_IVC2_5U18) }, { F (F_IVC2_5U23) }, { F (F_IVC2_4U28) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpmovfrcsar0_P0S_P1 ATTRIBUTE_UNUSED = { + 32, 32, 0xfffffe0f, { { F (F_IVC2_8U0) }, { F (F_IVC2_5U8) }, { F (F_IVC2_5U13) }, { F (F_IVC2_5U18) }, { F (F_IVC2_5U23) }, { F (F_IVC2_4U28) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpcmpeqz_b_P0S_P1 ATTRIBUTE_UNUSED = { + 32, 32, 0xfff801ff, { { F (F_IVC2_8U0) }, { F (F_IVC2_5U8) }, { F (F_IVC2_5U13) }, { F (F_IVC2_5U18) }, { F (F_IVC2_5U23) }, { F (F_IVC2_4U28) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpsrlia0_P0S ATTRIBUTE_UNUSED = { + 32, 32, 0xfffffe0f, { { F (F_IVC2_8U0) }, { F (F_IVC2_5U8) }, { F (F_IVC2_5U13) }, { F (F_IVC2_5U18) }, { F (F_IVC2_5U23) }, { F (F_IVC2_4U28) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpfsftbi_P0_P1 ATTRIBUTE_UNUSED = { + 32, 32, 0xf8000f, { { F (F_IVC2_5U0) }, { F (F_IVC2_3U5) }, { F (F_IVC2_5U8) }, { F (F_IVC2_5U13) }, { F (F_IVC2_5U18) }, { F (F_IVC2_5U23) }, { F (F_IVC2_4U28) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpsrli3_b_P0_P1 ATTRIBUTE_UNUSED = { + 32, 32, 0xf83e0f, { { F (F_IVC2_5U0) }, { F (F_IVC2_3U5) }, { F (F_IVC2_5U8) }, { F (F_IVC2_5U13) }, { F (F_IVC2_5U18) }, { F (F_IVC2_5U23) }, { F (F_IVC2_4U28) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpsrli3_h_P0_P1 ATTRIBUTE_UNUSED = { + 32, 32, 0xf83e0f, { { F (F_IVC2_4U0) }, { F (F_IVC2_4U4) }, { F (F_IVC2_5U8) }, { F (F_IVC2_5U13) }, { F (F_IVC2_5U18) }, { F (F_IVC2_5U23) }, { F (F_IVC2_4U28) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpsrli3_w_P0_P1 ATTRIBUTE_UNUSED = { + 32, 32, 0xf83e0f, { { F (F_IVC2_3U0) }, { F (F_IVC2_5U3) }, { F (F_IVC2_5U8) }, { F (F_IVC2_5U13) }, { F (F_IVC2_5U18) }, { F (F_IVC2_5U23) }, { F (F_IVC2_4U28) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cdsrli3_P0_P1 ATTRIBUTE_UNUSED = { + 32, 32, 0xf83e0f, { { F (F_IVC2_2U0) }, { F (F_IVC2_6U2) }, { F (F_IVC2_5U8) }, { F (F_IVC2_5U13) }, { F (F_IVC2_5U18) }, { F (F_IVC2_5U23) }, { F (F_IVC2_4U28) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpmovi_h_P0_P1 ATTRIBUTE_UNUSED = { + 32, 32, 0xf8300f, { { F (F_IVC2_SIMM16P0) }, { F (F_IVC2_5U8) }, { F (F_IVC2_5U13) }, { F (F_IVC2_2U18) }, { F (F_IVC2_4U28) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpmoviu_w_P0_P1 ATTRIBUTE_UNUSED = { + 32, 32, 0xf8300f, { { F (F_IVC2_IMM16P0) }, { F (F_IVC2_5U8) }, { F (F_IVC2_5U13) }, { F (F_IVC2_2U18) }, { F (F_IVC2_4U28) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpmovi_b_P0S_P1 ATTRIBUTE_UNUSED = { + 32, 32, 0xfff8300f, { { F (F_IVC2_8U0) }, { F (F_IVC2_5U8) }, { F (F_IVC2_5U13) }, { F (F_IVC2_2U18) }, { F (F_IVC2_8U20) }, { F (F_IVC2_4U28) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpfmulia1s0u_b_P1 ATTRIBUTE_UNUSED = { + 32, 32, 0xf801ff, { { F (F_IVC2_8S0) }, { F (F_IVC2_5U8) }, { F (F_IVC2_5U13) }, { F (F_IVC2_5U18) }, { F (F_IVC2_5U23) }, { F (F_IVC2_4U28) }, { 0 } } +}; + +static const CGEN_IFMT ifmt_cpfmulia1u_b_P1 ATTRIBUTE_UNUSED = { + 32, 32, 0xf8018f, { { F (F_IVC2_8S0) }, { F (F_IVC2_5U8) }, { F (F_IVC2_5U13) }, { F (F_IVC2_5U18) }, { F (F_IVC2_2U23) }, { F (F_IVC2_3U25) }, { F (F_IVC2_4U28) }, { 0 } } +}; + #undef F -#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) #define A(a) (1 << CGEN_INSN_##a) -#else -#define A(a) (1 << CGEN_INSN_/**/a) -#endif -#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) #define OPERAND(op) MEP_OPERAND_##op -#else -#define OPERAND(op) MEP_OPERAND_/**/op -#endif #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) @@ -569,6 +722,18 @@ static const CGEN_OPCODE mep_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, ' ', OP (RN), ',', OP (RM), ',', OP (UIMM16), 0 } }, & ifmt_dsp, { 0xf0000000 } }, +/* dsp0 $c5rnmuimm24 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (C5RNMUIMM24), 0 } }, + & ifmt_dsp0, { 0xf0000000 } + }, +/* dsp1 $rn,$c5rmuimm20 */ + { + { 0, 0, 0, 0 }, + { { MNEM, ' ', OP (RN), ',', OP (C5RMUIMM20), 0 } }, + & ifmt_dsp1, { 0xf0000000 } + }, /* sb $rnc,($rma) */ { { 0, 0, 0, 0 }, @@ -1643,7 +1808,7 @@ static const CGEN_OPCODE mep_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, ' ', OP (PCREL24A2), 0 } }, & ifmt_bsr24, { 0xd80b0000 } }, -/* --unused-- */ +/* --syscall-- */ { { 0, 0, 0, 0 }, { { MNEM, 0 } }, @@ -1781,194 +1946,4280 @@ static const CGEN_OPCODE mep_cgen_insn_opcode_table[MAX_INSNS] = { { MNEM, 0 } }, & ifmt_mov, { 0xf008 } }, -}; - -#undef A -#undef OPERAND -#undef MNEM -#undef OP - -/* Formats for ALIAS macro-insns. */ - -#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) -#define F(f) & mep_cgen_ifld_table[MEP_##f] -#else -#define F(f) & mep_cgen_ifld_table[MEP_/**/f] -#endif -static const CGEN_IFMT ifmt_dsp0 ATTRIBUTE_UNUSED = { - 32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16U16) }, { 0 } } -}; - -static const CGEN_IFMT ifmt_dsp1 ATTRIBUTE_UNUSED = { - 32, 32, 0xf00f0000, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { F (F_16U16) }, { 0 } } -}; - -static const CGEN_IFMT ifmt_nop ATTRIBUTE_UNUSED = { - 16, 16, 0xffff, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } -}; - -static const CGEN_IFMT ifmt_sb16_0 ATTRIBUTE_UNUSED = { - 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } -}; - -static const CGEN_IFMT ifmt_sh16_0 ATTRIBUTE_UNUSED = { - 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } -}; - -static const CGEN_IFMT ifmt_sw16_0 ATTRIBUTE_UNUSED = { - 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } -}; - -static const CGEN_IFMT ifmt_lb16_0 ATTRIBUTE_UNUSED = { - 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } -}; - -static const CGEN_IFMT ifmt_lh16_0 ATTRIBUTE_UNUSED = { - 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } -}; - -static const CGEN_IFMT ifmt_lw16_0 ATTRIBUTE_UNUSED = { - 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } -}; - -static const CGEN_IFMT ifmt_lbu16_0 ATTRIBUTE_UNUSED = { - 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } -}; - -static const CGEN_IFMT ifmt_lhu16_0 ATTRIBUTE_UNUSED = { - 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_RN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } -}; - -static const CGEN_IFMT ifmt_swcp16_0 ATTRIBUTE_UNUSED = { - 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } -}; - -static const CGEN_IFMT ifmt_lwcp16_0 ATTRIBUTE_UNUSED = { - 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } -}; - -static const CGEN_IFMT ifmt_smcp16_0 ATTRIBUTE_UNUSED = { - 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } -}; - -static const CGEN_IFMT ifmt_lmcp16_0 ATTRIBUTE_UNUSED = { - 16, 16, 0xf00f, { { F (F_MAJOR) }, { F (F_CRN) }, { F (F_RM) }, { F (F_SUB4) }, { 0 } } -}; - -#undef F - -/* Each non-simple macro entry points to an array of expansion possibilities. */ - -#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) -#define A(a) (1 << CGEN_INSN_##a) -#else -#define A(a) (1 << CGEN_INSN_/**/a) -#endif -#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) -#define OPERAND(op) MEP_OPERAND_##op -#else -#define OPERAND(op) MEP_OPERAND_/**/op -#endif -#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ -#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) - -/* The macro instruction table. */ - -static const CGEN_IBASE mep_cgen_macro_insn_table[] = -{ -/* dsp0 $c5rnmuimm24 */ +/* cmov $crnx64,$rm */ { - -1, "dsp0", "dsp0", 32, - { 0|A(VOLATILE)|A(NO_DIS)|A(ALIAS), { { { (1<