X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Fmips-dis.c;h=35a51191525903913eef8c9b7b1212d16ac79106;hb=bd2e25575ca4a83f509c2d6ea3c55d93eada210c;hp=644eac7addef0b60e48dbcd2d6ffd6aa49ebd07e;hpb=fd25c5a9db0e51c42cde14f2b6f64bd8f4764adf;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c index 644eac7add..35a5119152 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c @@ -1,20 +1,20 @@ /* Print mips instructions for GDB, the GNU debugger, or for objdump. Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, - 2000, 2001, 2002, 2003, 2005 + 2000, 2001, 2002, 2003, 2005, 2007, 2008 Free Software Foundation, Inc. Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp). - This file is part of GDB, GAS, and the GNU binutils. + This file is part of the GNU opcodes library. - This program is free software; you can redistribute it and/or modify + This library is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. + the Free Software Foundation; either version 3, or (at your option) + any later version. - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software @@ -51,12 +51,15 @@ struct mips_cp0sel_name const char * const name; }; -/* The mips16 register names. */ -static const char * const mips16_reg_names[] = +/* The mips16 registers. */ +static const unsigned int mips16_to_32_reg_map[] = { - "s0", "s1", "v0", "v1", "a0", "a1", "a2", "a3" + 16, 17, 2, 3, 4, 5, 6, 7 }; +#define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]] + + static const char * const mips_gpr_names_numeric[32] = { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", @@ -121,6 +124,30 @@ static const char * const mips_cp0_names_numeric[32] = "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" }; +static const char * const mips_cp0_names_r3000[32] = +{ + "c0_index", "c0_random", "c0_entrylo", "$3", + "c0_context", "$5", "$6", "$7", + "c0_badvaddr", "$9", "c0_entryhi", "$11", + "c0_sr", "c0_cause", "c0_epc", "c0_prid", + "$16", "$17", "$18", "$19", + "$20", "$21", "$22", "$23", + "$24", "$25", "$26", "$27", + "$28", "$29", "$30", "$31", +}; + +static const char * const mips_cp0_names_r4000[32] = +{ + "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", + "c0_context", "c0_pagemask", "c0_wired", "$7", + "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", + "c0_sr", "c0_cause", "c0_epc", "c0_prid", + "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", + "c0_xcontext", "$21", "$22", "$23", + "$24", "$25", "c0_ecc", "c0_cacheerr", + "c0_taglo", "c0_taghi", "c0_errorepc", "$31", +}; + static const char * const mips_cp0_names_mips3264[32] = { "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", @@ -181,7 +208,28 @@ static const char * const mips_cp0_names_mips3264r2[32] = static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] = { { 4, 1, "c0_contextconfig" }, + { 0, 1, "c0_mvpcontrol" }, + { 0, 2, "c0_mvpconf0" }, + { 0, 3, "c0_mvpconf1" }, + { 1, 1, "c0_vpecontrol" }, + { 1, 2, "c0_vpeconf0" }, + { 1, 3, "c0_vpeconf1" }, + { 1, 4, "c0_yqmask" }, + { 1, 5, "c0_vpeschedule" }, + { 1, 6, "c0_vpeschefback" }, + { 2, 1, "c0_tcstatus" }, + { 2, 2, "c0_tcbind" }, + { 2, 3, "c0_tcrestart" }, + { 2, 4, "c0_tchalt" }, + { 2, 5, "c0_tccontext" }, + { 2, 6, "c0_tcschedule" }, + { 2, 7, "c0_tcschefback" }, { 5, 1, "c0_pagegrain" }, + { 6, 1, "c0_srsconf0" }, + { 6, 2, "c0_srsconf1" }, + { 6, 3, "c0_srsconf2" }, + { 6, 4, "c0_srsconf3" }, + { 6, 5, "c0_srsconf4" }, { 12, 1, "c0_intctl" }, { 12, 2, "c0_srsctl" }, { 12, 3, "c0_srsmap" }, @@ -322,11 +370,11 @@ const struct mips_arch_choice mips_arch_choices[] = mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_r3000, NULL, 0, mips_hwr_names_numeric }, { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1, mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric }, { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2, mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3, @@ -338,7 +386,7 @@ const struct mips_arch_choice mips_arch_choices[] = { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3, mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3, - mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, + mips_cp0_names_r4000, NULL, 0, mips_hwr_names_numeric }, { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3, mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric }, { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3, @@ -370,26 +418,28 @@ const struct mips_arch_choice mips_arch_choices[] = MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95), page 1. */ { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32, - ISA_MIPS32 | INSN_MIPS16 | INSN_DSP, + ISA_MIPS32 | INSN_MIPS16 | INSN_SMARTMIPS, mips_cp0_names_mips3264, mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), mips_hwr_names_numeric }, { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2, - ISA_MIPS32R2 | INSN_MIPS16 | INSN_DSP, + (ISA_MIPS32R2 | INSN_MIPS16 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2 + | INSN_MIPS3D | INSN_MT), mips_cp0_names_mips3264r2, mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), mips_hwr_names_mips3264r2 }, /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */ { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64, - ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX | INSN_DSP, + ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX, mips_cp0_names_mips3264, mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264), mips_hwr_names_numeric }, { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2, - ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX | INSN_DSP, + (ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2 + | INSN_DSP64 | INSN_MT | INSN_MDMX), mips_cp0_names_mips3264r2, mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), mips_hwr_names_mips3264r2 }, @@ -400,6 +450,18 @@ const struct mips_arch_choice mips_arch_choices[] = mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1), mips_hwr_names_numeric }, + { "loongson2e", 1, bfd_mach_mips_loongson_2e, CPU_LOONGSON_2E, + ISA_MIPS3 | INSN_LOONGSON_2E, mips_cp0_names_numeric, + NULL, 0, mips_hwr_names_numeric }, + + { "loongson2f", 1, bfd_mach_mips_loongson_2f, CPU_LOONGSON_2F, + ISA_MIPS3 | INSN_LOONGSON_2F, mips_cp0_names_numeric, + NULL, 0, mips_hwr_names_numeric }, + + { "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON, + ISA_MIPS64R2 | INSN_OCTEON, mips_cp0_names_numeric, NULL, 0, + mips_hwr_names_numeric }, + /* This entry, mips16, is here only for ISA/processor selection; do not print its name. */ { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16, @@ -549,7 +611,7 @@ parse_mips_dis_option (const char *option, unsigned int len) const struct mips_arch_choice *chosen_arch; /* Try to match options that are simple flags */ - if (strncmp (option, "no-aliases", 10) == 0) + if (CONST_STRNEQ (option, "no-aliases")) { no_aliases = 1; return; @@ -688,7 +750,8 @@ static void print_insn_args (const char *d, register unsigned long int l, bfd_vma pc, - struct disassemble_info *info) + struct disassemble_info *info, + const struct mips_opcode *opp) { int op, delta; unsigned int lsb, msb, msbd; @@ -728,6 +791,26 @@ print_insn_args (const char *d, (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1); break; + case '1': + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_UDI1) & OP_MASK_UDI1); + break; + + case '2': + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_UDI2) & OP_MASK_UDI2); + break; + + case '3': + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_UDI3) & OP_MASK_UDI3); + break; + + case '4': + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_UDI4) & OP_MASK_UDI4); + break; + case 'C': case 'H': msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD; @@ -771,6 +854,61 @@ print_insn_args (const char *d, (*info->fprintf_func) (info->stream, "0x%x", msbd + 1); break; + case 't': /* Coprocessor 0 reg name */ + (*info->fprintf_func) (info->stream, "%s", + mips_cp0_names[(l >> OP_SH_RT) & + OP_MASK_RT]); + break; + + case 'T': /* Coprocessor 0 reg name */ + { + const struct mips_cp0sel_name *n; + unsigned int cp0reg, sel; + + cp0reg = (l >> OP_SH_RT) & OP_MASK_RT; + sel = (l >> OP_SH_SEL) & OP_MASK_SEL; + + /* CP0 register including 'sel' code for mftc0, to be + printed textually if known. If not known, print both + CP0 register name and sel numerically since CP0 register + with sel 0 may have a name unrelated to register being + printed. */ + n = lookup_mips_cp0sel_name(mips_cp0sel_names, + mips_cp0sel_names_len, cp0reg, sel); + if (n != NULL) + (*info->fprintf_func) (info->stream, "%s", n->name); + else + (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel); + break; + } + + case 'x': /* bbit bit index */ + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_BBITIND) & OP_MASK_BBITIND); + break; + + case 'p': /* cins, cins32, exts and exts32 position */ + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_CINSPOS) & OP_MASK_CINSPOS); + break; + + case 's': /* cins and exts length-minus-one */ + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_CINSLM1) & OP_MASK_CINSLM1); + break; + + case 'S': /* cins32 and exts32 length-minus-one field */ + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_CINSLM1) & OP_MASK_CINSLM1); + break; + + case 'Q': /* seqi/snei immediate field */ + op = (l >> OP_SH_SEQI) & OP_MASK_SEQI; + /* Sign-extend it. */ + op = (op ^ 512) - 512; + (*info->fprintf_func) (info->stream, "%d", op); + break; + default: /* xgettext:c-format */ (*info->fprintf_func) (info->stream, @@ -780,6 +918,11 @@ print_insn_args (const char *d, } break; + case '2': + (*info->fprintf_func) (info->stream, "0x%lx", + (l >> OP_SH_BP) & OP_MASK_BP); + break; + case '3': (*info->fprintf_func) (info->stream, "0x%lx", (l >> OP_SH_SA3) & OP_MASK_SA3); @@ -841,6 +984,32 @@ print_insn_args (const char *d, (*info->fprintf_func) (info->stream, "%d", delta); break; + case '!': + (*info->fprintf_func) (info->stream, "%ld", + (l >> OP_SH_MT_U) & OP_MASK_MT_U); + break; + + case '$': + (*info->fprintf_func) (info->stream, "%ld", + (l >> OP_SH_MT_H) & OP_MASK_MT_H); + break; + + case '*': + (*info->fprintf_func) (info->stream, "$ac%ld", + (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T); + break; + + case '&': + (*info->fprintf_func) (info->stream, "$ac%ld", + (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D); + break; + + case 'g': + /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */ + (*info->fprintf_func) (info->stream, "$%ld", + (l >> OP_SH_RD) & OP_MASK_RD); + break; + case 's': case 'b': case 'r': @@ -885,6 +1054,10 @@ print_insn_args (const char *d, case 'a': info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff) | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2)); + /* For gdb disassembler, force odd address on jalx. */ + if (info->flavour == bfd_target_unknown_flavour + && strcmp (opp->name, "jalx") == 0) + info->target |= 1; (*info->print_address_func) (info->target, info); break; @@ -1015,7 +1188,9 @@ print_insn_args (const char *d, break; case 'N': - (*info->fprintf_func) (info->stream, "$fcc%ld", + (*info->fprintf_func) (info->stream, + ((opp->pinfo & (FP_D | FP_S)) != 0 + ? "$fcc%ld" : "$cc%ld"), (l >> OP_SH_BCC) & OP_MASK_BCC); break; @@ -1096,7 +1271,7 @@ print_insn_args (const char *d, default: /* xgettext:c-format */ (*info->fprintf_func) (info->stream, - _("# internal error, undefined modifier(%c)"), + _("# internal error, undefined modifier (%c)"), *d); return; } @@ -1193,7 +1368,7 @@ print_insn_mips (bfd_vma memaddr, if (d != NULL && *d != '\0') { (*info->fprintf_func) (info->stream, "\t"); - print_insn_args (d, word, memaddr, info); + print_insn_args (d, word, memaddr, info, op); } return INSNLEN; @@ -1229,27 +1404,27 @@ print_mips16_insn_arg (char type, case 'y': case 'w': (*info->fprintf_func) (info->stream, "%s", - mips16_reg_names[((l >> MIPS16OP_SH_RY) - & MIPS16OP_MASK_RY)]); + mips16_reg_names(((l >> MIPS16OP_SH_RY) + & MIPS16OP_MASK_RY))); break; case 'x': case 'v': (*info->fprintf_func) (info->stream, "%s", - mips16_reg_names[((l >> MIPS16OP_SH_RX) - & MIPS16OP_MASK_RX)]); + mips16_reg_names(((l >> MIPS16OP_SH_RX) + & MIPS16OP_MASK_RX))); break; case 'z': (*info->fprintf_func) (info->stream, "%s", - mips16_reg_names[((l >> MIPS16OP_SH_RZ) - & MIPS16OP_MASK_RZ)]); + mips16_reg_names(((l >> MIPS16OP_SH_RZ) + & MIPS16OP_MASK_RZ))); break; case 'Z': (*info->fprintf_func) (info->stream, "%s", - mips16_reg_names[((l >> MIPS16OP_SH_MOVE32Z) - & MIPS16OP_MASK_MOVE32Z)]); + mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z) + & MIPS16OP_MASK_MOVE32Z))); break; case '0': @@ -1531,15 +1706,26 @@ print_mips16_insn_arg (char type, } } info->target = (baseaddr & ~((1 << shift) - 1)) + immed; + if (pcrel && branch + && info->flavour == bfd_target_unknown_flavour) + /* For gdb disassembler, maintain odd address. */ + info->target |= 1; (*info->print_address_func) (info->target, info); } } break; case 'a': - if (! use_extend) - extend = 0; - l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2); + { + int jalx = l & 0x400; + + if (! use_extend) + extend = 0; + l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2); + if (!jalx && info->flavour == bfd_target_unknown_flavour) + /* For gdb disassembler, maintain odd address. */ + l |= 1; + } info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l; (*info->print_address_func) (info->target, info); info->insn_type = dis_jsr; @@ -1602,6 +1788,92 @@ print_mips16_insn_arg (char type, } break; + case 'm': + case 'M': + /* MIPS16e save/restore. */ + { + int need_comma = 0; + int amask, args, statics; + int nsreg, smask; + int framesz; + int i, j; + + l = l & 0x7f; + if (use_extend) + l |= extend << 16; + + amask = (l >> 16) & 0xf; + if (amask == MIPS16_ALL_ARGS) + { + args = 4; + statics = 0; + } + else if (amask == MIPS16_ALL_STATICS) + { + args = 0; + statics = 4; + } + else + { + args = amask >> 2; + statics = amask & 3; + } + + if (args > 0) { + (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]); + if (args > 1) + (*info->fprintf_func) (info->stream, "-%s", + mips_gpr_names[4 + args - 1]); + need_comma = 1; + } + + framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8; + if (framesz == 0 && !use_extend) + framesz = 128; + + (*info->fprintf_func) (info->stream, "%s%d", + need_comma ? "," : "", + framesz); + + if (l & 0x40) /* $ra */ + (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]); + + nsreg = (l >> 24) & 0x7; + smask = 0; + if (l & 0x20) /* $s0 */ + smask |= 1 << 0; + if (l & 0x10) /* $s1 */ + smask |= 1 << 1; + if (nsreg > 0) /* $s2-$s8 */ + smask |= ((1 << nsreg) - 1) << 2; + + /* Find first set static reg bit. */ + for (i = 0; i < 9; i++) + { + if (smask & (1 << i)) + { + (*info->fprintf_func) (info->stream, ",%s", + mips_gpr_names[i == 8 ? 30 : (16 + i)]); + /* Skip over string of set bits. */ + for (j = i; smask & (2 << j); j++) + continue; + if (j > i) + (*info->fprintf_func) (info->stream, "-%s", + mips_gpr_names[j == 8 ? 30 : (16 + j)]); + i = j + 1; + } + } + + /* Statics $ax - $a3. */ + if (statics == 1) + (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]); + else if (statics > 0) + (*info->fprintf_func) (info->stream, ",%s-%s", + mips_gpr_names[7 - statics + 1], + mips_gpr_names[7]); + } + break; + default: /* xgettext:c-format */ (*info->fprintf_func) @@ -1794,8 +2066,8 @@ _print_insn_mips (bfd_vma memaddr, #if SYMTAB_AVAILABLE if (info->mach == bfd_mach_mips16 - || (info->flavour == bfd_target_elf_flavour - && info->symbols != NULL + || (info->symbols != NULL + && bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other == STO_MIPS16))) return print_insn_mips16 (memaddr, info);