X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Fmips-dis.c;h=3f874e72f5e3443b7b88eb3da79d321bdef359bc;hb=ecf64ec654afe916099f0fe482c2dae417913905;hp=12bb7b99b940be3a45e97e50006dd5c7b501c7ee;hpb=4ba154f579d9ac01829343ed7538727c0b2e87d8;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c index 12bb7b99b9..3f874e72f5 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c @@ -1,7 +1,5 @@ /* Print mips instructions for GDB, the GNU debugger, or for objdump. - Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, - 2000, 2001, 2002, 2003, 2005, 2006, 2007, 2008, 2009, 2012 - Free Software Foundation, Inc. + Copyright (C) 1989-2016 Free Software Foundation, Inc. Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp). This file is part of the GNU opcodes library. @@ -159,18 +157,6 @@ static const char * const mips_cp0_names_r5900[32] = "c0_taglo", "c0_taghi", "c0_errorepc", "$31" }; -static const struct mips_cp0sel_name mips_cp0sel_names_mipsr5900[] = -{ - { 24, 2, "c0_iab" }, - { 24, 3, "c0_iabm" }, - { 24, 4, "c0_dab" }, - { 24, 5, "c0_dabm" }, - { 24, 6, "c0_dvb" }, - { 24, 7, "c0_dvbm" }, - { 25, 1, "c0_perfcnt,1" }, - { 25, 2, "c0_perfcnt,2" } -}; - static const char * const mips_cp0_names_mips3264[32] = { "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", @@ -553,7 +539,31 @@ const struct mips_arch_choice mips_arch_choices[] = { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2, ISA_MIPS32R2, (ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_EVA | ASE_MIPS3D - | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA), + | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA | ASE_XPA), + mips_cp0_names_mips3264r2, + mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), + mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, + + { "mips32r3", 1, bfd_mach_mipsisa32r3, CPU_MIPS32R3, + ISA_MIPS32R3, + (ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_EVA | ASE_MIPS3D + | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA | ASE_XPA), + mips_cp0_names_mips3264r2, + mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), + mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, + + { "mips32r5", 1, bfd_mach_mipsisa32r5, CPU_MIPS32R5, + ISA_MIPS32R5, + (ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_EVA | ASE_MIPS3D + | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA | ASE_XPA), + mips_cp0_names_mips3264r2, + mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), + mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, + + { "mips32r6", 1, bfd_mach_mipsisa32r6, CPU_MIPS32R6, + ISA_MIPS32R6, + (ASE_EVA | ASE_MSA | ASE_VIRT | ASE_XPA | ASE_MCU | ASE_MT | ASE_DSP + | ASE_DSPR2 | ASE_DSPR3), mips_cp0_names_mips3264r2, mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, @@ -568,7 +578,31 @@ const struct mips_arch_choice mips_arch_choices[] = { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2, ISA_MIPS64R2, (ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_EVA | ASE_MT - | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64), + | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64 | ASE_XPA), + mips_cp0_names_mips3264r2, + mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), + mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, + + { "mips64r3", 1, bfd_mach_mipsisa64r3, CPU_MIPS64R3, + ISA_MIPS64R3, + (ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_EVA | ASE_MT + | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64 | ASE_XPA), + mips_cp0_names_mips3264r2, + mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), + mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, + + { "mips64r5", 1, bfd_mach_mipsisa64r5, CPU_MIPS64R5, + ISA_MIPS64R5, + (ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_EVA | ASE_MT + | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64 | ASE_XPA), + mips_cp0_names_mips3264r2, + mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), + mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, + + { "mips64r6", 1, bfd_mach_mipsisa64r6, CPU_MIPS64R6, + ISA_MIPS64R6, + (ASE_EVA | ASE_MSA | ASE_MSA64 | ASE_XPA | ASE_VIRT | ASE_VIRT64 + | ASE_MCU | ASE_MT | ASE_DSP | ASE_DSPR2 | ASE_DSPR3), mips_cp0_names_mips3264r2, mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, @@ -603,6 +637,11 @@ const struct mips_arch_choice mips_arch_choices[] = ISA_MIPS64R2 | INSN_OCTEON2, 0, mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric }, + { "octeon3", 1, bfd_mach_mips_octeon3, CPU_OCTEON3, + ISA_MIPS64R5 | INSN_OCTEON3, ASE_VIRT | ASE_VIRT64, + mips_cp0_names_numeric, + NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric }, + { "xlr", 1, bfd_mach_mips_xlr, CPU_XLR, ISA_MIPS64 | INSN_XLR, 0, mips_cp0_names_xlr, @@ -800,7 +839,10 @@ parse_mips_dis_option (const char *option, unsigned int len) if (CONST_STRNEQ (option, "msa")) { mips_ase |= ASE_MSA; - if ((mips_isa & INSN_ISA_MASK) == ISA_MIPS64R2) + if ((mips_isa & INSN_ISA_MASK) == ISA_MIPS64R2 + || (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R3 + || (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R5 + || (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R6) mips_ase |= ASE_MSA64; return; } @@ -808,11 +850,21 @@ parse_mips_dis_option (const char *option, unsigned int len) if (CONST_STRNEQ (option, "virt")) { mips_ase |= ASE_VIRT; - if (mips_isa & ISA_MIPS64R2) + if (mips_isa & ISA_MIPS64R2 + || mips_isa & ISA_MIPS64R3 + || mips_isa & ISA_MIPS64R5 + || mips_isa & ISA_MIPS64R6) mips_ase |= ASE_VIRT64; return; } - + + if (CONST_STRNEQ (option, "xpa")) + { + mips_ase |= ASE_XPA; + return; + } + + /* Look for the = that delimits the end of the option name. */ for (i = 0; i < len; i++) if (option[i] == '=') @@ -1043,6 +1095,8 @@ struct mips_print_arg_state { OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG. */ enum mips_reg_operand_type last_reg_type; unsigned int last_regno; + unsigned int dest_regno; + unsigned int seen_dest; }; /* Initialize STATE for the start of an instruction. */ @@ -1072,6 +1126,23 @@ print_vu0_channel (struct disassemble_info *info, abort (); } +/* Record information about a register operand. */ + +static void +mips_seen_register (struct mips_print_arg_state *state, + unsigned int regno, + enum mips_reg_operand_type reg_type) +{ + state->last_reg_type = reg_type; + state->last_regno = regno; + + if (!state->seen_dest) + { + state->seen_dest = 1; + state->dest_regno = regno; + } +} + /* Print operand OPERAND of OPCODE, using STATE to track inter-operand state. UVAL is the encoding of the operand (shifted into bit 0) and BASE_PC is the base address for OP_PCREL operands. */ @@ -1138,8 +1209,7 @@ print_insn_arg (struct disassemble_info *info, uval = mips_decode_reg_operand (reg_op, uval); print_reg (info, opcode, reg_op->reg_type, uval); - state->last_reg_type = reg_op->reg_type; - state->last_regno = uval; + mips_seen_register (state, uval, reg_op->reg_type); } break; @@ -1205,6 +1275,15 @@ print_insn_arg (struct disassemble_info *info, } break; + case OP_SAME_RS_RT: + case OP_CHECK_PREV: + case OP_NON_ZERO_REG: + { + print_reg (info, opcode, OP_REG_GP, uval & 31); + mips_seen_register (state, uval, OP_REG_GP); + } + break; + case OP_LWM_SWM_LIST: if (operand->size == 2) { @@ -1327,8 +1406,8 @@ print_insn_arg (struct disassemble_info *info, break; case OP_REPEAT_DEST_REG: - /* Should always match OP_REPEAT_PREV_REG first. */ - abort (); + print_reg (info, opcode, state->last_reg_type, state->dest_regno); + break; case OP_PC: infprintf (is, "$pc"); @@ -1351,15 +1430,130 @@ print_insn_arg (struct disassemble_info *info, } } +/* Validate the arguments for INSN, which is described by OPCODE. + Use DECODE_OPERAND to get the encoding of each operand. */ + +static bfd_boolean +validate_insn_args (const struct mips_opcode *opcode, + const struct mips_operand *(*decode_operand) (const char *), + unsigned int insn) +{ + struct mips_print_arg_state state; + const struct mips_operand *operand; + const char *s; + unsigned int uval; + + init_print_arg_state (&state); + for (s = opcode->args; *s; ++s) + { + switch (*s) + { + case ',': + case '(': + case ')': + break; + + case '#': + ++s; + break; + + default: + operand = decode_operand (s); + + if (operand) + { + uval = mips_extract_operand (operand, insn); + switch (operand->type) + { + case OP_REG: + case OP_OPTIONAL_REG: + { + const struct mips_reg_operand *reg_op; + + reg_op = (const struct mips_reg_operand *) operand; + uval = mips_decode_reg_operand (reg_op, uval); + mips_seen_register (&state, uval, reg_op->reg_type); + } + break; + + case OP_SAME_RS_RT: + { + unsigned int reg1, reg2; + + reg1 = uval & 31; + reg2 = uval >> 5; + + if (reg1 != reg2 || reg1 == 0) + return FALSE; + } + break; + + case OP_CHECK_PREV: + { + const struct mips_check_prev_operand *prev_op; + + prev_op = (const struct mips_check_prev_operand *) operand; + + if (!prev_op->zero_ok && uval == 0) + return FALSE; + + if (((prev_op->less_than_ok && uval < state.last_regno) + || (prev_op->greater_than_ok && uval > state.last_regno) + || (prev_op->equal_ok && uval == state.last_regno))) + break; + + return FALSE; + } + + case OP_NON_ZERO_REG: + { + if (uval == 0) + return FALSE; + } + break; + + case OP_INT: + case OP_MAPPED_INT: + case OP_MSB: + case OP_REG_PAIR: + case OP_PCREL: + case OP_PERF_REG: + case OP_ADDIUSP_INT: + case OP_CLO_CLZ_DEST: + case OP_LWM_SWM_LIST: + case OP_ENTRY_EXIT_LIST: + case OP_MDMX_IMM_REG: + case OP_REPEAT_PREV_REG: + case OP_REPEAT_DEST_REG: + case OP_PC: + case OP_VU0_SUFFIX: + case OP_VU0_MATCH_SUFFIX: + case OP_IMM_INDEX: + case OP_REG_INDEX: + break; + + case OP_SAVE_RESTORE_LIST: + /* Should be handled by the caller due to extend behavior. */ + abort (); + } + } + if (*s == 'm' || *s == '+' || *s == '-') + ++s; + } + } + return TRUE; +} + /* Print the arguments for INSN, which is described by OPCODE. Use DECODE_OPERAND to get the encoding of each operand. Use BASE_PC - as the base of OP_PCREL operands. */ + as the base of OP_PCREL operands, adjusting by LENGTH if the OP_PCREL + operand is for a branch or jump. */ static void print_insn_args (struct disassemble_info *info, const struct mips_opcode *opcode, const struct mips_operand *(*decode_operand) (const char *), - unsigned int insn, bfd_vma base_pc) + unsigned int insn, bfd_vma insn_pc, unsigned int length) { const fprintf_ftype infprintf = info->fprintf_func; void *is = info->stream; @@ -1421,9 +1615,27 @@ print_insn_args (struct disassemble_info *info, infprintf (is, "$%d,%d", reg, sel); } else - print_insn_arg (info, &state, opcode, operand, base_pc, - mips_extract_operand (operand, insn)); - if (*s == 'm' || *s == '+') + { + bfd_vma base_pc = insn_pc; + + /* Adjust the PC relative base so that branch/jump insns use + the following PC as the base but genuinely PC relative + operands use the current PC. */ + if (operand->type == OP_PCREL) + { + const struct mips_pcrel_operand *pcrel_op; + + pcrel_op = (const struct mips_pcrel_operand *) operand; + /* The include_isa_bit flag is sufficient to distinguish + branch/jump from other PC relative operands. */ + if (pcrel_op->include_isa_bit) + base_pc += length; + } + + print_insn_arg (info, &state, opcode, operand, base_pc, + mips_extract_operand (operand, insn)); + } + if (*s == 'm' || *s == '+' || *s == '-') ++s; break; } @@ -1485,13 +1697,15 @@ print_insn_mips (bfd_vma memaddr, { for (; op < &mips_opcodes[NUMOPCODES]; op++) { - if (op->pinfo != INSN_MACRO + if (op->pinfo != INSN_MACRO && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) && (word & op->mask) == op->match) { - /* We always allow to disassemble the jalx instruction. */ + /* We always disassemble the jalx instruction, except for MIPS r6. */ if (!opcode_is_member (op, mips_isa, mips_ase, mips_processor) - && strcmp (op->name, "jalx")) + && (strcmp (op->name, "jalx") + || (mips_isa & INSN_ISA_MASK) == ISA_MIPS32R6 + || (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R6)) continue; /* Figure out instruction type and branch delay information. */ @@ -1516,6 +1730,9 @@ print_insn_mips (bfd_vma memaddr, | INSN_LOAD_MEMORY)) != 0) info->insn_type = dis_dref; + if (!validate_insn_args (op, decode_mips_operand, word)) + continue; + infprintf (is, "%s", op->name); if (op->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) { @@ -1530,7 +1747,7 @@ print_insn_mips (bfd_vma memaddr, { infprintf (is, "\t"); print_insn_args (info, op, decode_mips_operand, word, - memaddr + 4); + memaddr, 4); } return INSNLEN; @@ -1677,11 +1894,13 @@ print_mips16_insn_arg (struct disassemble_info *info, { operand = ext_operand; if (operand->size == 16) - uval |= ((extend & 0x1f) << 11) | (extend & 0x7e0); + uval = (((extend & 0x1f) << 11) | (extend & 0x7e0) + | (uval & 0x1f)); else if (operand->size == 15) uval |= ((extend & 0xf) << 11) | (extend & 0x7f0); else - uval = ((extend >> 6) & 0x1f) | (extend & 0x20); + uval = ((((extend >> 6) & 0x1f) | (extend & 0x20)) + & ((1U << operand->size) - 1)); } } } @@ -1968,41 +2187,7 @@ print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info) else insn = bfd_getl16 (buffer); - if ((insn & 0xfc00) == 0x7c00) - { - /* This is a 48-bit microMIPS instruction. */ - higher = insn; - - status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info); - if (status != 0) - { - infprintf (is, "micromips 0x%x", higher); - (*info->memory_error_func) (status, memaddr + 2, info); - return -1; - } - if (info->endian == BFD_ENDIAN_BIG) - insn = bfd_getb16 (buffer); - else - insn = bfd_getl16 (buffer); - higher = (higher << 16) | insn; - - status = (*info->read_memory_func) (memaddr + 4, buffer, 2, info); - if (status != 0) - { - infprintf (is, "micromips 0x%x", higher); - (*info->memory_error_func) (status, memaddr + 4, info); - return -1; - } - if (info->endian == BFD_ENDIAN_BIG) - insn = bfd_getb16 (buffer); - else - insn = bfd_getl16 (buffer); - infprintf (is, "0x%x%04x (48-bit insn)", higher, insn); - - info->insn_type = dis_noninsn; - return 6; - } - else if ((insn & 0x1c00) == 0x0000 || (insn & 0x1000) == 0x1000) + if ((insn & 0x1c00) == 0x0000 || (insn & 0x1000) == 0x1000) { /* This is a 32-bit microMIPS instruction. */ higher = insn; @@ -2036,13 +2221,16 @@ print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info) && ((length == 2 && (op->mask & 0xffff0000) == 0) || (length == 4 && (op->mask & 0xffff0000) != 0))) { + if (!validate_insn_args (op, decode_micromips_operand, insn)) + continue; + infprintf (is, "%s", op->name); if (op->args[0]) { infprintf (is, "\t"); print_insn_args (info, op, decode_micromips_operand, insn, - memaddr + length + 1); + memaddr + 1, length); } /* Figure out instruction type and branch delay information. */ @@ -2080,33 +2268,33 @@ print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info) } /* Return 1 if a symbol associated with the location being disassembled - indicates a compressed (MIPS16 or microMIPS) mode. We iterate over - all the symbols at the address being considered assuming if at least - one of them indicates code compression, then such code has been - genuinely produced here (other symbols could have been derived from - function symbols defined elsewhere or could define data). Otherwise, - return 0. */ + indicates a compressed mode, either MIPS16 or microMIPS, according to + MICROMIPS_P. We iterate over all the symbols at the address being + considered assuming if at least one of them indicates code compression, + then such code has been genuinely produced here (other symbols could + have been derived from function symbols defined elsewhere or could + define data). Otherwise, return 0. */ static bfd_boolean -is_compressed_mode_p (struct disassemble_info *info) +is_compressed_mode_p (struct disassemble_info *info, bfd_boolean micromips_p) { int i; int l; for (i = info->symtab_pos, l = i + info->num_symbols; i < l; i++) if (((info->symtab[i])->flags & BSF_SYNTHETIC) != 0 - && ((!micromips_ase + && ((!micromips_p && ELF_ST_IS_MIPS16 ((*info->symbols)->udata.i)) - || (micromips_ase + || (micromips_p && ELF_ST_IS_MICROMIPS ((*info->symbols)->udata.i)))) return 1; else if (bfd_asymbol_flavour (info->symtab[i]) == bfd_target_elf_flavour && info->symtab[i]->section == info->section) { elf_symbol_type *symbol = (elf_symbol_type *) info->symtab[i]; - if ((!micromips_ase + if ((!micromips_p && ELF_ST_IS_MIPS16 (symbol->internal_elf_sym.st_other)) - || (micromips_ase + || (micromips_p && ELF_ST_IS_MICROMIPS (symbol->internal_elf_sym.st_other))) return 1; } @@ -2125,7 +2313,6 @@ _print_insn_mips (bfd_vma memaddr, struct disassemble_info *info, enum bfd_endian endianness) { - int (*print_insn_compr) (bfd_vma, struct disassemble_info *); bfd_byte buffer[INSNLEN]; int status; @@ -2137,18 +2324,23 @@ _print_insn_mips (bfd_vma memaddr, if (info->mach == bfd_mach_mips_micromips) return print_insn_micromips (memaddr, info); - print_insn_compr = !micromips_ase ? print_insn_mips16 : print_insn_micromips; - #if 1 /* FIXME: If odd address, this is CLEARLY a compressed instruction. */ /* Only a few tools will work this way. */ if (memaddr & 0x01) - return print_insn_compr (memaddr, info); + { + if (micromips_ase) + return print_insn_micromips (memaddr, info); + else + return print_insn_mips16 (memaddr, info); + } #endif #if SYMTAB_AVAILABLE - if (is_compressed_mode_p (info)) - return print_insn_compr (memaddr, info); + if (is_compressed_mode_p (info, TRUE)) + return print_insn_micromips (memaddr, info); + if (is_compressed_mode_p (info, FALSE)) + return print_insn_mips16 (memaddr, info); #endif status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info); @@ -2197,6 +2389,9 @@ with the -M switch (multiple options should be separated by commas):\n")); fprintf (stream, _("\n\ virt Recognize the virtualization ASE instructions.\n")); + fprintf (stream, _("\n\ + xpa Recognize the eXtended Physical Address (XPA) ASE instructions.\n")); + fprintf (stream, _("\n\ gpr-names=ABI Print GPR names according to specified ABI.\n\ Default: based on binary being disassembled.\n"));