X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Fmips-dis.c;h=45195007c1e47f6065e8834e6235c4493882b1b0;hb=9785fc2a4d220322ce6cd1d79e768345ea5234d2;hp=09a2ed1309e7d12b5a7367a35e10e41d6fc34de9;hpb=dc76d75756a47325f5233ff684b05d6c0846e86a;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c index 09a2ed1309..45195007c1 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c @@ -1,7 +1,5 @@ /* Print mips instructions for GDB, the GNU debugger, or for objdump. - Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, - 2000, 2001, 2002, 2003, 2005, 2006, 2007, 2008, 2009, 2012 - Free Software Foundation, Inc. + Copyright (C) 1989-2017 Free Software Foundation, Inc. Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp). This file is part of the GNU opcodes library. @@ -22,7 +20,7 @@ MA 02110-1301, USA. */ #include "sysdep.h" -#include "dis-asm.h" +#include "disassemble.h" #include "libiberty.h" #include "opcode/mips.h" #include "opintl.h" @@ -159,18 +157,6 @@ static const char * const mips_cp0_names_r5900[32] = "c0_taglo", "c0_taghi", "c0_errorepc", "$31" }; -static const struct mips_cp0sel_name mips_cp0sel_names_mipsr5900[] = -{ - { 24, 2, "c0_iab" }, - { 24, 3, "c0_iabm" }, - { 24, 4, "c0_dab" }, - { 24, 5, "c0_dabm" }, - { 24, 6, "c0_dvb" }, - { 24, 7, "c0_dvbm" }, - { 25, 1, "c0_perfcnt,1" }, - { 25, 2, "c0_perfcnt,2" } -}; - static const char * const mips_cp0_names_mips3264[32] = { "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", @@ -553,7 +539,31 @@ const struct mips_arch_choice mips_arch_choices[] = { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2, ISA_MIPS32R2, (ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_EVA | ASE_MIPS3D - | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA), + | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA | ASE_XPA), + mips_cp0_names_mips3264r2, + mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), + mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, + + { "mips32r3", 1, bfd_mach_mipsisa32r3, CPU_MIPS32R3, + ISA_MIPS32R3, + (ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_EVA | ASE_MIPS3D + | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA | ASE_XPA), + mips_cp0_names_mips3264r2, + mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), + mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, + + { "mips32r5", 1, bfd_mach_mipsisa32r5, CPU_MIPS32R5, + ISA_MIPS32R5, + (ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_EVA | ASE_MIPS3D + | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA | ASE_XPA), + mips_cp0_names_mips3264r2, + mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), + mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, + + { "mips32r6", 1, bfd_mach_mipsisa32r6, CPU_MIPS32R6, + ISA_MIPS32R6, + (ASE_EVA | ASE_MSA | ASE_VIRT | ASE_XPA | ASE_MCU | ASE_MT | ASE_DSP + | ASE_DSPR2 | ASE_DSPR3), mips_cp0_names_mips3264r2, mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, @@ -568,7 +578,38 @@ const struct mips_arch_choice mips_arch_choices[] = { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2, ISA_MIPS64R2, (ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_EVA | ASE_MT - | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64), + | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64 | ASE_XPA), + mips_cp0_names_mips3264r2, + mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), + mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, + + { "mips64r3", 1, bfd_mach_mipsisa64r3, CPU_MIPS64R3, + ISA_MIPS64R3, + (ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_EVA | ASE_MT + | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64 | ASE_XPA), + mips_cp0_names_mips3264r2, + mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), + mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, + + { "mips64r5", 1, bfd_mach_mipsisa64r5, CPU_MIPS64R5, + ISA_MIPS64R5, + (ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_EVA | ASE_MT + | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64 | ASE_XPA), + mips_cp0_names_mips3264r2, + mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), + mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, + + { "mips64r6", 1, bfd_mach_mipsisa64r6, CPU_MIPS64R6, + ISA_MIPS64R6, + (ASE_EVA | ASE_MSA | ASE_MSA64 | ASE_XPA | ASE_VIRT | ASE_VIRT64 + | ASE_MCU | ASE_MT | ASE_DSP | ASE_DSPR2 | ASE_DSPR3), + mips_cp0_names_mips3264r2, + mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), + mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, + + { "interaptiv-mr2", 1, bfd_mach_mips_interaptiv_mr2, CPU_INTERAPTIV_MR2, + ISA_MIPS32R3, + ASE_MT | ASE_EVA | ASE_DSP | ASE_DSPR2 | ASE_MIPS16E2 | ASE_MIPS16E2_MT, mips_cp0_names_mips3264r2, mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2), mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 }, @@ -588,7 +629,7 @@ const struct mips_arch_choice mips_arch_choices[] = NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric }, { "loongson3a", 1, bfd_mach_mips_loongson_3a, CPU_LOONGSON_3A, - ISA_MIPS64 | INSN_LOONGSON_3A, 0, mips_cp0_names_numeric, + ISA_MIPS64R2 | INSN_LOONGSON_3A, 0, mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric }, { "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON, @@ -603,6 +644,11 @@ const struct mips_arch_choice mips_arch_choices[] = ISA_MIPS64R2 | INSN_OCTEON2, 0, mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric }, + { "octeon3", 1, bfd_mach_mips_octeon3, CPU_OCTEON3, + ISA_MIPS64R5 | INSN_OCTEON3, ASE_VIRT | ASE_VIRT64, + mips_cp0_names_numeric, + NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric }, + { "xlr", 1, bfd_mach_mips_xlr, CPU_XLR, ISA_MIPS64 | INSN_XLR, 0, mips_cp0_names_xlr, @@ -619,7 +665,8 @@ const struct mips_arch_choice mips_arch_choices[] = /* This entry, mips16, is here only for ISA/processor selection; do not print its name. */ - { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3, 0, + { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS64, + ASE_MIPS16E2 | ASE_MIPS16E2_MT, mips_cp0_names_numeric, NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric }, }; @@ -725,6 +772,56 @@ is_micromips (Elf_Internal_Ehdr *header) return 0; } +/* Convert ASE flags from .MIPS.abiflags to internal values. */ + +static unsigned long +mips_convert_abiflags_ases (unsigned long afl_ases) +{ + unsigned long opcode_ases = 0; + + if (afl_ases & AFL_ASE_DSP) + opcode_ases |= ASE_DSP; + if (afl_ases & AFL_ASE_DSPR2) + opcode_ases |= ASE_DSPR2; + if (afl_ases & AFL_ASE_EVA) + opcode_ases |= ASE_EVA; + if (afl_ases & AFL_ASE_MCU) + opcode_ases |= ASE_MCU; + if (afl_ases & AFL_ASE_MDMX) + opcode_ases |= ASE_MDMX; + if (afl_ases & AFL_ASE_MIPS3D) + opcode_ases |= ASE_MIPS3D; + if (afl_ases & AFL_ASE_MT) + opcode_ases |= ASE_MT; + if (afl_ases & AFL_ASE_SMARTMIPS) + opcode_ases |= ASE_SMARTMIPS; + if (afl_ases & AFL_ASE_VIRT) + opcode_ases |= ASE_VIRT; + if (afl_ases & AFL_ASE_MSA) + opcode_ases |= ASE_MSA; + if (afl_ases & AFL_ASE_XPA) + opcode_ases |= ASE_XPA; + if (afl_ases & AFL_ASE_DSPR3) + opcode_ases |= ASE_DSPR3; + if (afl_ases & AFL_ASE_MIPS16E2) + opcode_ases |= ASE_MIPS16E2; + return opcode_ases; +} + +/* Calculate combination ASE flags from regular ASE flags. */ + +static unsigned long +mips_calculate_combination_ases (unsigned long opcode_ases) +{ + unsigned long combination_ases = 0; + + if ((opcode_ases & (ASE_XPA | ASE_VIRT)) == (ASE_XPA | ASE_VIRT)) + combination_ases |= ASE_XPA_VIRT; + if ((opcode_ases & (ASE_MIPS16E2 | ASE_MT)) == (ASE_MIPS16E2 | ASE_MT)) + combination_ases |= ASE_MIPS16E2_MT; + return combination_ases; +} + static void set_default_mips_dis_options (struct disassemble_info *info) { @@ -746,19 +843,6 @@ set_default_mips_dis_options (struct disassemble_info *info) mips_hwr_names = mips_hwr_names_numeric; no_aliases = 0; - /* Update settings according to the ELF file header flags. */ - if (info->flavour == bfd_target_elf_flavour && info->section != NULL) - { - Elf_Internal_Ehdr *header; - - header = elf_elfheader (info->section->owner); - /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */ - if (is_newabi (header)) - mips_gpr_names = mips_gpr_names_newabi; - /* If a microMIPS binary, then don't use MIPS16 bindings. */ - micromips_ase = is_micromips (header); - } - /* Set ISA, architecture, and cp0 register names as best we can. */ #if ! SYMTAB_AVAILABLE /* This is running out on a target machine, not in a host tool. @@ -779,7 +863,72 @@ set_default_mips_dis_options (struct disassemble_info *info) mips_cp1_names = chosen_arch->cp1_names; mips_hwr_names = chosen_arch->hwr_names; } + + /* Update settings according to the ELF file header flags. */ + if (info->flavour == bfd_target_elf_flavour && info->section != NULL) + { + struct bfd *abfd = info->section->owner; + Elf_Internal_Ehdr *header = elf_elfheader (abfd); + Elf_Internal_ABIFlags_v0 *abiflags = NULL; + + /* We won't ever get here if !HAVE_BFD_MIPS_ELF_GET_ABIFLAGS, + because we won't then have a MIPS/ELF BFD, however we need + to guard against a link error in a `--enable-targets=...' + configuration with a 32-bit host where the MIPS target is + a secondary, or with MIPS/ECOFF configurations. */ +#ifdef HAVE_BFD_MIPS_ELF_GET_ABIFLAGS + abiflags = bfd_mips_elf_get_abiflags (abfd); +#endif + /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */ + if (is_newabi (header)) + mips_gpr_names = mips_gpr_names_newabi; + /* If a microMIPS binary, then don't use MIPS16 bindings. */ + micromips_ase = is_micromips (header); + /* OR in any extra ASE flags set in ELF file structures. */ + if (abiflags) + mips_ase |= mips_convert_abiflags_ases (abiflags->ases); + else if (header->e_flags & EF_MIPS_ARCH_ASE_MDMX) + mips_ase |= ASE_MDMX; + } #endif + mips_ase |= mips_calculate_combination_ases (mips_ase); +} + +/* Parse an ASE disassembler option and set the corresponding global + ASE flag(s). Return TRUE if successful, FALSE otherwise. */ + +static bfd_boolean +parse_mips_ase_option (const char *option) +{ + if (CONST_STRNEQ (option, "msa")) + { + mips_ase |= ASE_MSA; + if ((mips_isa & INSN_ISA_MASK) == ISA_MIPS64R2 + || (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R3 + || (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R5 + || (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R6) + mips_ase |= ASE_MSA64; + return TRUE; + } + + if (CONST_STRNEQ (option, "virt")) + { + mips_ase |= ASE_VIRT; + if (mips_isa & ISA_MIPS64R2 + || mips_isa & ISA_MIPS64R3 + || mips_isa & ISA_MIPS64R5 + || mips_isa & ISA_MIPS64R6) + mips_ase |= ASE_VIRT64; + return TRUE; + } + + if (CONST_STRNEQ (option, "xpa")) + { + mips_ase |= ASE_XPA; + return TRUE; + } + + return FALSE; } static void @@ -797,22 +946,12 @@ parse_mips_dis_option (const char *option, unsigned int len) return; } - if (CONST_STRNEQ (option, "msa")) + if (parse_mips_ase_option (option)) { - mips_ase |= ASE_MSA; - if ((mips_isa & INSN_ISA_MASK) == ISA_MIPS64R2) - mips_ase |= ASE_MSA64; + mips_ase |= mips_calculate_combination_ases (mips_ase); return; } - if (CONST_STRNEQ (option, "virt")) - { - mips_ase |= ASE_VIRT; - if (mips_isa & ISA_MIPS64R2) - mips_ase |= ASE_VIRT64; - return; - } - /* Look for the = that delimits the end of the option name. */ for (i = 0; i < len; i++) if (option[i] == '=') @@ -1043,6 +1182,8 @@ struct mips_print_arg_state { OP_REPEAT_DEST_REG and OP_REPEAT_PREV_REG. */ enum mips_reg_operand_type last_reg_type; unsigned int last_regno; + unsigned int dest_regno; + unsigned int seen_dest; }; /* Initialize STATE for the start of an instruction. */ @@ -1072,6 +1213,98 @@ print_vu0_channel (struct disassemble_info *info, abort (); } +/* Record information about a register operand. */ + +static void +mips_seen_register (struct mips_print_arg_state *state, + unsigned int regno, + enum mips_reg_operand_type reg_type) +{ + state->last_reg_type = reg_type; + state->last_regno = regno; + + if (!state->seen_dest) + { + state->seen_dest = 1; + state->dest_regno = regno; + } +} + +/* Print SAVE/RESTORE instruction operands according to the argument + register mask AMASK, the number of static registers saved NSREG, + the $ra, $s0 and $s1 register specifiers RA, S0 and S1 respectively, + and the frame size FRAME_SIZE. */ + +static void +mips_print_save_restore (struct disassemble_info *info, unsigned int amask, + unsigned int nsreg, unsigned int ra, + unsigned int s0, unsigned int s1, + unsigned int frame_size) +{ + const fprintf_ftype infprintf = info->fprintf_func; + unsigned int nargs, nstatics, smask, i, j; + void *is = info->stream; + const char *sep; + + if (amask == MIPS_SVRS_ALL_ARGS) + { + nargs = 4; + nstatics = 0; + } + else if (amask == MIPS_SVRS_ALL_STATICS) + { + nargs = 0; + nstatics = 4; + } + else + { + nargs = amask >> 2; + nstatics = amask & 3; + } + + sep = ""; + if (nargs > 0) + { + infprintf (is, "%s", mips_gpr_names[4]); + if (nargs > 1) + infprintf (is, "-%s", mips_gpr_names[4 + nargs - 1]); + sep = ","; + } + + infprintf (is, "%s%d", sep, frame_size); + + if (ra) /* $ra */ + infprintf (is, ",%s", mips_gpr_names[31]); + + smask = 0; + if (s0) /* $s0 */ + smask |= 1 << 0; + if (s1) /* $s1 */ + smask |= 1 << 1; + if (nsreg > 0) /* $s2-$s8 */ + smask |= ((1 << nsreg) - 1) << 2; + + for (i = 0; i < 9; i++) + if (smask & (1 << i)) + { + infprintf (is, ",%s", mips_gpr_names[i == 8 ? 30 : (16 + i)]); + /* Skip over string of set bits. */ + for (j = i; smask & (2 << j); j++) + continue; + if (j > i) + infprintf (is, "-%s", mips_gpr_names[j == 8 ? 30 : (16 + j)]); + i = j + 1; + } + /* Statics $ax - $a3. */ + if (nstatics == 1) + infprintf (is, ",%s", mips_gpr_names[7]); + else if (nstatics > 0) + infprintf (is, ",%s-%s", + mips_gpr_names[7 - nstatics + 1], + mips_gpr_names[7]); +} + + /* Print operand OPERAND of OPCODE, using STATE to track inter-operand state. UVAL is the encoding of the operand (shifted into bit 0) and BASE_PC is the base address for OP_PCREL operands. */ @@ -1138,8 +1371,7 @@ print_insn_arg (struct disassemble_info *info, uval = mips_decode_reg_operand (reg_op, uval); print_reg (info, opcode, reg_op->reg_type, uval); - state->last_reg_type = reg_op->reg_type; - state->last_regno = uval; + mips_seen_register (state, uval, reg_op->reg_type); } break; @@ -1163,9 +1395,10 @@ print_insn_arg (struct disassemble_info *info, pcrel_op = (const struct mips_pcrel_operand *) operand; info->target = mips_decode_pcrel_operand (pcrel_op, base_pc, uval); - /* Preserve the ISA bit for the GDB disassembler, - otherwise clear it. */ - if (info->flavour != bfd_target_unknown_flavour) + /* For jumps and branches clear the ISA bit except for + the GDB disassembler. */ + if (pcrel_op->include_isa_bit + && info->flavour != bfd_target_unknown_flavour) info->target &= -2; (*info->print_address_func) (info->target, info); @@ -1205,6 +1438,15 @@ print_insn_arg (struct disassemble_info *info, } break; + case OP_SAME_RS_RT: + case OP_CHECK_PREV: + case OP_NON_ZERO_REG: + { + print_reg (info, opcode, OP_REG_GP, uval & 31); + mips_seen_register (state, uval, OP_REG_GP); + } + break; + case OP_LWM_SWM_LIST: if (operand->size == 2) { @@ -1295,7 +1537,7 @@ print_insn_arg (struct disassemble_info *info, break; case OP_SAVE_RESTORE_LIST: - /* Should be handled by the caller due to extend behavior. */ + /* Should be handled by the caller due to complex behavior. */ abort (); case OP_MDMX_IMM_REG: @@ -1327,13 +1569,17 @@ print_insn_arg (struct disassemble_info *info, break; case OP_REPEAT_DEST_REG: - /* Should always match OP_REPEAT_PREV_REG first. */ - abort (); + print_reg (info, opcode, state->last_reg_type, state->dest_regno); + break; case OP_PC: infprintf (is, "$pc"); break; + case OP_REG28: + print_reg (info, opcode, OP_REG_GP, 28); + break; + case OP_VU0_SUFFIX: case OP_VU0_MATCH_SUFFIX: print_vu0_channel (info, operand, uval); @@ -1351,15 +1597,128 @@ print_insn_arg (struct disassemble_info *info, } } +/* Validate the arguments for INSN, which is described by OPCODE. + Use DECODE_OPERAND to get the encoding of each operand. */ + +static bfd_boolean +validate_insn_args (const struct mips_opcode *opcode, + const struct mips_operand *(*decode_operand) (const char *), + unsigned int insn) +{ + struct mips_print_arg_state state; + const struct mips_operand *operand; + const char *s; + unsigned int uval; + + init_print_arg_state (&state); + for (s = opcode->args; *s; ++s) + { + switch (*s) + { + case ',': + case '(': + case ')': + break; + + case '#': + ++s; + break; + + default: + operand = decode_operand (s); + + if (operand) + { + uval = mips_extract_operand (operand, insn); + switch (operand->type) + { + case OP_REG: + case OP_OPTIONAL_REG: + { + const struct mips_reg_operand *reg_op; + + reg_op = (const struct mips_reg_operand *) operand; + uval = mips_decode_reg_operand (reg_op, uval); + mips_seen_register (&state, uval, reg_op->reg_type); + } + break; + + case OP_SAME_RS_RT: + { + unsigned int reg1, reg2; + + reg1 = uval & 31; + reg2 = uval >> 5; + + if (reg1 != reg2 || reg1 == 0) + return FALSE; + } + break; + + case OP_CHECK_PREV: + { + const struct mips_check_prev_operand *prev_op; + + prev_op = (const struct mips_check_prev_operand *) operand; + + if (!prev_op->zero_ok && uval == 0) + return FALSE; + + if (((prev_op->less_than_ok && uval < state.last_regno) + || (prev_op->greater_than_ok && uval > state.last_regno) + || (prev_op->equal_ok && uval == state.last_regno))) + break; + + return FALSE; + } + + case OP_NON_ZERO_REG: + { + if (uval == 0) + return FALSE; + } + break; + + case OP_INT: + case OP_MAPPED_INT: + case OP_MSB: + case OP_REG_PAIR: + case OP_PCREL: + case OP_PERF_REG: + case OP_ADDIUSP_INT: + case OP_CLO_CLZ_DEST: + case OP_LWM_SWM_LIST: + case OP_ENTRY_EXIT_LIST: + case OP_MDMX_IMM_REG: + case OP_REPEAT_PREV_REG: + case OP_REPEAT_DEST_REG: + case OP_PC: + case OP_REG28: + case OP_VU0_SUFFIX: + case OP_VU0_MATCH_SUFFIX: + case OP_IMM_INDEX: + case OP_REG_INDEX: + case OP_SAVE_RESTORE_LIST: + break; + } + } + if (*s == 'm' || *s == '+' || *s == '-') + ++s; + } + } + return TRUE; +} + /* Print the arguments for INSN, which is described by OPCODE. Use DECODE_OPERAND to get the encoding of each operand. Use BASE_PC - as the base of OP_PCREL operands. */ + as the base of OP_PCREL operands, adjusting by LENGTH if the OP_PCREL + operand is for a branch or jump. */ static void print_insn_args (struct disassemble_info *info, const struct mips_opcode *opcode, const struct mips_operand *(*decode_operand) (const char *), - unsigned int insn, bfd_vma base_pc) + unsigned int insn, bfd_vma insn_pc, unsigned int length) { const fprintf_ftype infprintf = info->fprintf_func; void *is = info->stream; @@ -1393,12 +1752,26 @@ print_insn_args (struct disassemble_info *info, opcode->name, opcode->args); return; } - if (operand->type == OP_REG - && s[1] == ',' - && s[2] == 'H' - && opcode->name[strlen (opcode->name) - 1] == '0') + + if (operand->type == OP_SAVE_RESTORE_LIST) + { + /* Handle this case here because of the complex behavior. */ + unsigned int amask = (insn >> 15) & 0xf; + unsigned int nsreg = (insn >> 23) & 0x7; + unsigned int ra = insn & 0x1000; /* $ra */ + unsigned int s0 = insn & 0x800; /* $s0 */ + unsigned int s1 = insn & 0x400; /* $s1 */ + unsigned int frame_size = (((insn >> 15) & 0xf0) + | ((insn >> 6) & 0x0f)) * 8; + mips_print_save_restore (info, amask, nsreg, ra, s0, s1, + frame_size); + } + else if (operand->type == OP_REG + && s[1] == ',' + && s[2] == 'H' + && opcode->name[strlen (opcode->name) - 1] == '0') { - /* Coprocessor register 0 with sel field (MT ASE). */ + /* Coprocessor register 0 with sel field. */ const struct mips_cp0sel_name *n; unsigned int reg, sel; @@ -1421,9 +1794,27 @@ print_insn_args (struct disassemble_info *info, infprintf (is, "$%d,%d", reg, sel); } else - print_insn_arg (info, &state, opcode, operand, base_pc, - mips_extract_operand (operand, insn)); - if (*s == 'm' || *s == '+') + { + bfd_vma base_pc = insn_pc; + + /* Adjust the PC relative base so that branch/jump insns use + the following PC as the base but genuinely PC relative + operands use the current PC. */ + if (operand->type == OP_PCREL) + { + const struct mips_pcrel_operand *pcrel_op; + + pcrel_op = (const struct mips_pcrel_operand *) operand; + /* The include_isa_bit flag is sufficient to distinguish + branch/jump from other PC relative operands. */ + if (pcrel_op->include_isa_bit) + base_pc += length; + } + + print_insn_arg (info, &state, opcode, operand, base_pc, + mips_extract_operand (operand, insn)); + } + if (*s == 'm' || *s == '+' || *s == '-') ++s; break; } @@ -1485,13 +1876,15 @@ print_insn_mips (bfd_vma memaddr, { for (; op < &mips_opcodes[NUMOPCODES]; op++) { - if (op->pinfo != INSN_MACRO + if (op->pinfo != INSN_MACRO && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) && (word & op->mask) == op->match) { - /* We always allow to disassemble the jalx instruction. */ + /* We always disassemble the jalx instruction, except for MIPS r6. */ if (!opcode_is_member (op, mips_isa, mips_ase, mips_processor) - && strcmp (op->name, "jalx")) + && (strcmp (op->name, "jalx") + || (mips_isa & INSN_ISA_MASK) == ISA_MIPS32R6 + || (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R6)) continue; /* Figure out instruction type and branch delay information. */ @@ -1516,6 +1909,9 @@ print_insn_mips (bfd_vma memaddr, | INSN_LOAD_MEMORY)) != 0) info->insn_type = dis_dref; + if (!validate_insn_args (op, decode_mips_operand, word)) + continue; + infprintf (is, "%s", op->name); if (op->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) { @@ -1530,7 +1926,7 @@ print_insn_mips (bfd_vma memaddr, { infprintf (is, "\t"); print_insn_args (info, op, decode_mips_operand, word, - memaddr + 4); + memaddr, 4); } return INSNLEN; @@ -1558,6 +1954,7 @@ print_mips16_insn_arg (struct disassemble_info *info, const fprintf_ftype infprintf = info->fprintf_func; void *is = info->stream; const struct mips_operand *operand, *ext_operand; + unsigned short ext_size; unsigned int uval; bfd_vma baseaddr; @@ -1584,72 +1981,17 @@ print_mips16_insn_arg (struct disassemble_info *info, if (operand->type == OP_SAVE_RESTORE_LIST) { - /* Handle this case here because of the complex interation + /* Handle this case here because of the complex interaction with the EXTEND opcode. */ - unsigned int amask, nargs, nstatics, nsreg, smask, frame_size, i, j; - const char *sep; - - amask = extend & 0xf; - if (amask == MIPS16_ALL_ARGS) - { - nargs = 4; - nstatics = 0; - } - else if (amask == MIPS16_ALL_STATICS) - { - nargs = 0; - nstatics = 4; - } - else - { - nargs = amask >> 2; - nstatics = amask & 3; - } - - sep = ""; - if (nargs > 0) - { - infprintf (is, "%s", mips_gpr_names[4]); - if (nargs > 1) - infprintf (is, "-%s", mips_gpr_names[4 + nargs - 1]); - sep = ","; - } - - frame_size = ((extend & 0xf0) | (insn & 0x0f)) * 8; + unsigned int amask = extend & 0xf; + unsigned int nsreg = (extend >> 8) & 0x7; + unsigned int ra = insn & 0x40; /* $ra */ + unsigned int s0 = insn & 0x20; /* $s0 */ + unsigned int s1 = insn & 0x10; /* $s1 */ + unsigned int frame_size = ((extend & 0xf0) | (insn & 0x0f)) * 8; if (frame_size == 0 && !use_extend) frame_size = 128; - infprintf (is, "%s%d", sep, frame_size); - - if (insn & 0x40) /* $ra */ - infprintf (is, ",%s", mips_gpr_names[31]); - - nsreg = (extend >> 8) & 0x7; - smask = 0; - if (insn & 0x20) /* $s0 */ - smask |= 1 << 0; - if (insn & 0x10) /* $s1 */ - smask |= 1 << 1; - if (nsreg > 0) /* $s2-$s8 */ - smask |= ((1 << nsreg) - 1) << 2; - - for (i = 0; i < 9; i++) - if (smask & (1 << i)) - { - infprintf (is, ",%s", mips_gpr_names[i == 8 ? 30 : (16 + i)]); - /* Skip over string of set bits. */ - for (j = i; smask & (2 << j); j++) - continue; - if (j > i) - infprintf (is, "-%s", mips_gpr_names[j == 8 ? 30 : (16 + j)]); - i = j + 1; - } - /* Statics $ax - $a3. */ - if (nstatics == 1) - infprintf (is, ",%s", mips_gpr_names[7]); - else if (nstatics > 0) - infprintf (is, ",%s-%s", - mips_gpr_names[7 - nstatics + 1], - mips_gpr_names[7]); + mips_print_save_restore (info, amask, nsreg, ra, s0, s1, frame_size); break; } @@ -1662,29 +2004,30 @@ print_mips16_insn_arg (struct disassemble_info *info, info->data_size = 1 << int_op->shift; } - if (operand->size == 26) - /* In this case INSN is the first two bytes of the instruction - and EXTEND is the second two bytes. */ - uval = ((insn & 0x1f) << 21) | ((insn & 0x3e0) << 11) | extend; - else + ext_size = 0; + if (use_extend) { - /* Calculate the full field value. */ - uval = mips_extract_operand (operand, insn); - if (use_extend) + ext_operand = decode_mips16_operand (type, TRUE); + if (ext_operand != operand + || (operand->type == OP_INT && operand->lsb == 0 + && mips_opcode_32bit_p (opcode))) { - ext_operand = decode_mips16_operand (type, TRUE); - if (ext_operand != operand) - { - operand = ext_operand; - if (operand->size == 16) - uval |= ((extend & 0x1f) << 11) | (extend & 0x7e0); - else if (operand->size == 15) - uval |= ((extend & 0xf) << 11) | (extend & 0x7f0); - else - uval = ((extend >> 6) & 0x1f) | (extend & 0x20); - } + ext_size = ext_operand->size; + operand = ext_operand; } } + if (operand->size == 26) + uval = ((extend & 0x1f) << 21) | ((extend & 0x3e0) << 11) | insn; + else if (ext_size == 16 || ext_size == 9) + uval = ((extend & 0x1f) << 11) | (extend & 0x7e0) | (insn & 0x1f); + else if (ext_size == 15) + uval = ((extend & 0xf) << 11) | (extend & 0x7f0) | (insn & 0xf); + else if (ext_size == 6) + uval = ((extend >> 6) & 0x1f) | (extend & 0x20); + else + uval = mips_extract_operand (operand, (extend << 16) | insn); + if (ext_size == 9) + uval &= (1U << ext_size) - 1; baseaddr = memaddr + 2; if (operand->type == OP_PCREL) @@ -1695,32 +2038,36 @@ print_mips16_insn_arg (struct disassemble_info *info, if (!pcrel_op->include_isa_bit && use_extend) baseaddr = memaddr - 2; else if (!pcrel_op->include_isa_bit) - { - bfd_byte buffer[2]; - - /* If this instruction is in the delay slot of a JR - instruction, the base address is the address of the - JR instruction. If it is in the delay slot of a JALR - instruction, the base address is the address of the - JALR instruction. This test is unreliable: we have - no way of knowing whether the previous word is - instruction or data. */ - if (info->read_memory_func (memaddr - 4, buffer, 2, info) == 0 - && (((info->endian == BFD_ENDIAN_BIG - ? bfd_getb16 (buffer) - : bfd_getl16 (buffer)) - & 0xf800) == 0x1800)) - baseaddr = memaddr - 4; - else if (info->read_memory_func (memaddr - 2, buffer, 2, - info) == 0 - && (((info->endian == BFD_ENDIAN_BIG - ? bfd_getb16 (buffer) - : bfd_getl16 (buffer)) - & 0xf81f) == 0xe800)) - baseaddr = memaddr - 2; - else - baseaddr = memaddr; - } + { + bfd_byte buffer[2]; + + /* If this instruction is in the delay slot of a JAL/JALX + instruction, the base address is the address of the + JAL/JALX instruction. If it is in the delay slot of + a JR/JALR instruction, the base address is the address + of the JR/JALR instruction. This test is unreliable: + we have no way of knowing whether the previous word is + instruction or data. */ + if (info->read_memory_func (memaddr - 4, buffer, 2, info) == 0 + && (((info->endian == BFD_ENDIAN_BIG + ? bfd_getb16 (buffer) + : bfd_getl16 (buffer)) + & 0xf800) == 0x1800)) + baseaddr = memaddr - 4; + else if (info->read_memory_func (memaddr - 2, buffer, 2, + info) == 0 + && (((info->endian == BFD_ENDIAN_BIG + ? bfd_getb16 (buffer) + : bfd_getl16 (buffer)) + & 0xf89f) == 0xe800) + && (((info->endian == BFD_ENDIAN_BIG + ? bfd_getb16 (buffer) + : bfd_getl16 (buffer)) + & 0x0060) != 0x0060)) + baseaddr = memaddr - 2; + else + baseaddr = memaddr; + } } print_insn_arg (info, state, opcode, operand, baseaddr + 1, uval); @@ -1745,6 +2092,15 @@ is_mips16_plt_tail (struct disassemble_info *info, bfd_vma addr) return FALSE; } +/* Whether none, a 32-bit or a 16-bit instruction match has been done. */ + +enum match_kind +{ + MATCH_NONE, + MATCH_FULL, + MATCH_SHORT +}; + /* Disassemble mips16 instructions. */ static int @@ -1753,13 +2109,14 @@ print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info) const fprintf_ftype infprintf = info->fprintf_func; int status; bfd_byte buffer[4]; - int length; - int insn; - bfd_boolean use_extend; - int extend = 0; const struct mips_opcode *op, *opend; struct mips_print_arg_state state; void *is = info->stream; + bfd_boolean have_second; + bfd_boolean extend_only; + unsigned int second; + unsigned int first; + unsigned int full; info->bytes_per_chunk = 2; info->display_endian = info->endian; @@ -1800,44 +2157,28 @@ print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info) return -1; } - length = 2; + extend_only = FALSE; if (info->endian == BFD_ENDIAN_BIG) - insn = bfd_getb16 (buffer); + first = bfd_getb16 (buffer); else - insn = bfd_getl16 (buffer); + first = bfd_getl16 (buffer); - /* Handle the extend opcode specially. */ - use_extend = FALSE; - if ((insn & 0xf800) == 0xf000) + status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info); + if (status == 0) { - use_extend = TRUE; - extend = insn & 0x7ff; - - memaddr += 2; - - status = (*info->read_memory_func) (memaddr, buffer, 2, info); - if (status != 0) - { - infprintf (is, "extend 0x%x", (unsigned int) extend); - (*info->memory_error_func) (status, memaddr, info); - return -1; - } - + have_second = TRUE; if (info->endian == BFD_ENDIAN_BIG) - insn = bfd_getb16 (buffer); + second = bfd_getb16 (buffer); else - insn = bfd_getl16 (buffer); - - /* Check for an extend opcode followed by an extend opcode. */ - if ((insn & 0xf800) == 0xf000) - { - infprintf (is, "extend 0x%x", (unsigned int) extend); - info->insn_type = dis_noninsn; - return length; - } - - length += 2; + second = bfd_getl16 (buffer); + full = (first << 16) | second; + } + else + { + have_second = FALSE; + second = 0; + full = first; } /* FIXME: Should probably use a hash table on the major opcode here. */ @@ -1845,37 +2186,47 @@ print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info) opend = mips16_opcodes + bfd_mips16_num_opcodes; for (op = mips16_opcodes; op < opend; op++) { - if (op->pinfo != INSN_MACRO - && !(no_aliases && (op->pinfo2 & INSN2_ALIAS)) - && (insn & op->mask) == op->match) - { - const char *s; - - if (op->args[0] == 'a' || op->args[0] == 'i') - { - if (use_extend) - { - infprintf (is, "extend 0x%x", (unsigned int) extend); - info->insn_type = dis_noninsn; - return length - 2; - } + enum match_kind match; - use_extend = FALSE; + if (!opcode_is_member (op, mips_isa, mips_ase, mips_processor)) + continue; - memaddr += 2; - - status = (*info->read_memory_func) (memaddr, buffer, 2, - info); - if (status == 0) - { - use_extend = TRUE; - if (info->endian == BFD_ENDIAN_BIG) - extend = bfd_getb16 (buffer); - else - extend = bfd_getl16 (buffer); - length += 2; - } + if (op->pinfo == INSN_MACRO + || (no_aliases && (op->pinfo2 & INSN2_ALIAS))) + match = MATCH_NONE; + else if (mips_opcode_32bit_p (op)) + { + if (have_second + && (full & op->mask) == op->match) + match = MATCH_FULL; + else + match = MATCH_NONE; + } + else if ((first & op->mask) == op->match) + { + match = MATCH_SHORT; + second = 0; + full = first; + } + else if ((first & 0xf800) == 0xf000 + && have_second + && !extend_only + && (second & op->mask) == op->match) + { + if (op->pinfo2 & INSN2_SHORT_ONLY) + { + match = MATCH_NONE; + extend_only = TRUE; } + else + match = MATCH_FULL; + } + else + match = MATCH_NONE; + + if (match != MATCH_NONE) + { + const char *s; infprintf (is, "%s", op->name); if (op->args[0] != '\0') @@ -1886,7 +2237,7 @@ print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info) { if (*s == ',' && s[1] == 'w' - && GET_OP (insn, RX) == GET_OP (insn, RY)) + && GET_OP (full, RX) == GET_OP (full, RY)) { /* Skip the register and the comma. */ ++s; @@ -1894,14 +2245,55 @@ print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info) } if (*s == ',' && s[1] == 'v' - && GET_OP (insn, RZ) == GET_OP (insn, RX)) + && GET_OP (full, RZ) == GET_OP (full, RX)) { /* Skip the register and the comma. */ ++s; continue; } - print_mips16_insn_arg (info, &state, op, *s, memaddr, insn, - use_extend, extend, s[1] == '('); + if (s[0] == 'N' + && s[1] == ',' + && s[2] == 'O' + && op->name[strlen (op->name) - 1] == '0') + { + /* Coprocessor register 0 with sel field. */ + const struct mips_cp0sel_name *n; + const struct mips_operand *operand; + unsigned int reg, sel; + + operand = decode_mips16_operand (*s, TRUE); + reg = mips_extract_operand (operand, (first << 16) | second); + s += 2; + operand = decode_mips16_operand (*s, TRUE); + sel = mips_extract_operand (operand, (first << 16) | second); + + /* CP0 register including 'sel' code for mftc0, to be + printed textually if known. If not known, print both + CP0 register name and sel numerically since CP0 register + with sel 0 may have a name unrelated to register being + printed. */ + n = lookup_mips_cp0sel_name (mips_cp0sel_names, + mips_cp0sel_names_len, + reg, sel); + if (n != NULL) + infprintf (is, "%s", n->name); + else + infprintf (is, "$%d,%d", reg, sel); + } + else + switch (match) + { + case MATCH_FULL: + print_mips16_insn_arg (info, &state, op, *s, memaddr + 2, + second, TRUE, first, s[1] == '('); + break; + case MATCH_SHORT: + print_mips16_insn_arg (info, &state, op, *s, memaddr, + first, FALSE, 0, s[1] == '('); + break; + case MATCH_NONE: /* Stop the compiler complaining. */ + break; + } } /* Figure out branch instruction type and delay slot information. */ @@ -1918,17 +2310,15 @@ print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info) else if ((op->pinfo2 & INSN2_COND_BRANCH) != 0) info->insn_type = dis_condbranch; - return length; + return match == MATCH_FULL ? 4 : 2; } } #undef GET_OP - if (use_extend) - infprintf (is, "0x%x", extend | 0xf000); - infprintf (is, "0x%x", insn); + infprintf (is, "0x%x", first); info->insn_type = dis_noninsn; - return length; + return 2; } /* Disassemble microMIPS instructions. */ @@ -1968,41 +2358,7 @@ print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info) else insn = bfd_getl16 (buffer); - if ((insn & 0xfc00) == 0x7c00) - { - /* This is a 48-bit microMIPS instruction. */ - higher = insn; - - status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info); - if (status != 0) - { - infprintf (is, "micromips 0x%x", higher); - (*info->memory_error_func) (status, memaddr + 2, info); - return -1; - } - if (info->endian == BFD_ENDIAN_BIG) - insn = bfd_getb16 (buffer); - else - insn = bfd_getl16 (buffer); - higher = (higher << 16) | insn; - - status = (*info->read_memory_func) (memaddr + 4, buffer, 2, info); - if (status != 0) - { - infprintf (is, "micromips 0x%x", higher); - (*info->memory_error_func) (status, memaddr + 4, info); - return -1; - } - if (info->endian == BFD_ENDIAN_BIG) - insn = bfd_getb16 (buffer); - else - insn = bfd_getl16 (buffer); - infprintf (is, "0x%x%04x (48-bit insn)", higher, insn); - - info->insn_type = dis_noninsn; - return 6; - } - else if ((insn & 0x1c00) == 0x0000 || (insn & 0x1000) == 0x1000) + if ((insn & 0x1c00) == 0x0000 || (insn & 0x1000) == 0x1000) { /* This is a 32-bit microMIPS instruction. */ higher = insn; @@ -2036,13 +2392,16 @@ print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info) && ((length == 2 && (op->mask & 0xffff0000) == 0) || (length == 4 && (op->mask & 0xffff0000) != 0))) { + if (!validate_insn_args (op, decode_micromips_operand, insn)) + continue; + infprintf (is, "%s", op->name); if (op->args[0]) { infprintf (is, "\t"); print_insn_args (info, op, decode_micromips_operand, insn, - memaddr + length + 1); + memaddr + 1, length); } /* Figure out instruction type and branch delay information. */ @@ -2080,33 +2439,33 @@ print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info) } /* Return 1 if a symbol associated with the location being disassembled - indicates a compressed (MIPS16 or microMIPS) mode. We iterate over - all the symbols at the address being considered assuming if at least - one of them indicates code compression, then such code has been - genuinely produced here (other symbols could have been derived from - function symbols defined elsewhere or could define data). Otherwise, - return 0. */ + indicates a compressed mode, either MIPS16 or microMIPS, according to + MICROMIPS_P. We iterate over all the symbols at the address being + considered assuming if at least one of them indicates code compression, + then such code has been genuinely produced here (other symbols could + have been derived from function symbols defined elsewhere or could + define data). Otherwise, return 0. */ static bfd_boolean -is_compressed_mode_p (struct disassemble_info *info) +is_compressed_mode_p (struct disassemble_info *info, bfd_boolean micromips_p) { int i; int l; for (i = info->symtab_pos, l = i + info->num_symbols; i < l; i++) if (((info->symtab[i])->flags & BSF_SYNTHETIC) != 0 - && ((!micromips_ase + && ((!micromips_p && ELF_ST_IS_MIPS16 ((*info->symbols)->udata.i)) - || (micromips_ase + || (micromips_p && ELF_ST_IS_MICROMIPS ((*info->symbols)->udata.i)))) return 1; else if (bfd_asymbol_flavour (info->symtab[i]) == bfd_target_elf_flavour && info->symtab[i]->section == info->section) { elf_symbol_type *symbol = (elf_symbol_type *) info->symtab[i]; - if ((!micromips_ase + if ((!micromips_p && ELF_ST_IS_MIPS16 (symbol->internal_elf_sym.st_other)) - || (micromips_ase + || (micromips_p && ELF_ST_IS_MICROMIPS (symbol->internal_elf_sym.st_other))) return 1; } @@ -2125,7 +2484,6 @@ _print_insn_mips (bfd_vma memaddr, struct disassemble_info *info, enum bfd_endian endianness) { - int (*print_insn_compr) (bfd_vma, struct disassemble_info *); bfd_byte buffer[INSNLEN]; int status; @@ -2137,18 +2495,23 @@ _print_insn_mips (bfd_vma memaddr, if (info->mach == bfd_mach_mips_micromips) return print_insn_micromips (memaddr, info); - print_insn_compr = !micromips_ase ? print_insn_mips16 : print_insn_micromips; - #if 1 /* FIXME: If odd address, this is CLEARLY a compressed instruction. */ /* Only a few tools will work this way. */ if (memaddr & 0x01) - return print_insn_compr (memaddr, info); + { + if (micromips_ase) + return print_insn_micromips (memaddr, info); + else + return print_insn_mips16 (memaddr, info); + } #endif #if SYMTAB_AVAILABLE - if (is_compressed_mode_p (info)) - return print_insn_compr (memaddr, info); + if (is_compressed_mode_p (info, TRUE)) + return print_insn_micromips (memaddr, info); + if (is_compressed_mode_p (info, FALSE)) + return print_insn_mips16 (memaddr, info); #endif status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info); @@ -2192,13 +2555,20 @@ The following MIPS specific disassembler options are supported for use\n\ with the -M switch (multiple options should be separated by commas):\n")); fprintf (stream, _("\n\ - msa Recognize MSA instructions.\n")); + no-aliases Use canonical instruction forms.\n")); + + fprintf (stream, _("\n\ + msa Recognize MSA instructions.\n")); + + fprintf (stream, _("\n\ + virt Recognize the virtualization ASE instructions.\n")); fprintf (stream, _("\n\ - virt Recognize the virtualization ASE instructions.\n")); + xpa Recognize the eXtended Physical Address (XPA)\n\ + ASE instructions.\n")); fprintf (stream, _("\n\ - gpr-names=ABI Print GPR names according to specified ABI.\n\ + gpr-names=ABI Print GPR names according to specified ABI.\n\ Default: based on binary being disassembled.\n")); fprintf (stream, _("\n\ @@ -2212,7 +2582,7 @@ with the -M switch (multiple options should be separated by commas):\n")); fprintf (stream, _("\n\ hwr-names=ARCH Print HWR names according to specified \n\ - architecture.\n\ + architecture.\n\ Default: based on binary being disassembled.\n")); fprintf (stream, _("\n\