X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Fmips-opc.c;h=8f51643ee4716d288b43c48eabdae1880a194bab;hb=e10abd8fbe1d22774878cdaedf031c8fdc2a42cb;hp=230d0f8c9d732a48de221d944e5b3192bb754533;hpb=704897fbeff6f2247f87578efb9054e246fd0cd0;p=deliverable%2Fbinutils-gdb.git

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 230d0f8c9d..8f51643ee4 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -107,6 +107,7 @@
 
 #define IL2E    (INSN_LOONGSON_2E)
 #define IL2F    (INSN_LOONGSON_2F)
+#define IL3A    (INSN_LOONGSON_3A)
 
 #define P3	INSN_4650
 #define L1	INSN_4010
@@ -163,6 +164,13 @@
 /* MIPS MT ASE support.  */
 #define MT32	INSN_MT
 
+/* Loongson support.  */
+#define WR_z	INSN2_WRITE_GPR_Z
+#define WR_Z	INSN2_WRITE_FPR_Z
+#define RD_z	INSN2_READ_GPR_Z
+#define RD_Z	INSN2_READ_FPR_Z
+#define RD_d	INSN2_READ_GPR_D
+
 /* The order of overloaded instructions matters.  Label arguments and
    register arguments look the same. Instructions that can have either
    for arguments must apear in the correct order in this table for the
@@ -183,6 +191,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
    instruction name anyhow.  */
 /* name,    args,	match,	    mask,	pinfo,          	pinfo2,		membership */
 {"pref",    "k,o(b)",   0xcc000000, 0xfc000000, RD_b,           	0,		I4_32|G3	},
+{"pref",    "k,A(b)",	0,    (int) M_PREF_AB,	INSN_MACRO,		0,		I4_32|G3	},
 {"prefx",   "h,t(b)",	0x4c00000f, 0xfc0007ff, RD_b|RD_t|FP_S,		0,		I4_33	},
 {"nop",     "",         0x00000000, 0xffffffff, 0,              	INSN2_ALIAS,	I1      }, /* sll */
 {"ssnop",   "",         0x00000040, 0xffffffff, 0,              	INSN2_ALIAS,	I1	}, /* sll */
@@ -198,6 +207,64 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"b",       "p",	0x04010000, 0xffff0000,	UBD,			INSN2_ALIAS,	I1	},/* bgez 0 */
 {"bal",     "p",	0x04110000, 0xffff0000,	UBD|WR_31,		INSN2_ALIAS,	I1	},/* bgezal 0*/
 
+/* Loongson specific instructions.  Loongson 3A redefines the Coprocessor 2
+   instructions.  Put them here so that disassembler will find them first.
+   The assemblers uses a hash table based on the instruction name anyhow.  */
+{"campi",	"d,s",		0x70000075,	0xfc1f07ff,	WR_d|RD_s,	0,	IL3A	},
+{"campv",	"d,s",		0x70000035,	0xfc1f07ff,	WR_d|RD_s,	0,	IL3A	},
+{"camwi",	"d,s,t",	0x700000b5,	0xfc0007ff,	RD_s|RD_t,	RD_d,	IL3A	},
+{"ramri",	"d,s",		0x700000f5,	0xfc1f07ff,	WR_d|RD_s,	0,	IL3A	},
+{"gsle",	"s,t",		0x70000026,	0xfc00ffff,	RD_s|RD_t,	0,	IL3A	},
+{"gsgt",	"s,t",		0x70000027,	0xfc00ffff,	RD_s|RD_t,	0,	IL3A	},
+{"gslble",	"t,b,d",	0xc8000010,	0xfc0007ff,	WR_t|RD_b|LDD,	RD_d,	IL3A	},
+{"gslbgt",	"t,b,d",	0xc8000011,	0xfc0007ff,	WR_t|RD_b|LDD,	RD_d,	IL3A	},
+{"gslhle",	"t,b,d",	0xc8000012,	0xfc0007ff,	WR_t|RD_b|LDD,	RD_d,	IL3A	},
+{"gslhgt",	"t,b,d",	0xc8000013,	0xfc0007ff,	WR_t|RD_b|LDD,	RD_d,	IL3A	},
+{"gslwle",	"t,b,d",	0xc8000014,	0xfc0007ff,	WR_t|RD_b|LDD,	RD_d,	IL3A	},
+{"gslwgt",	"t,b,d",	0xc8000015,	0xfc0007ff,	WR_t|RD_b|LDD,	RD_d,	IL3A	},
+{"gsldle",	"t,b,d",	0xc8000016,	0xfc0007ff,	WR_t|RD_b|LDD,	RD_d,	IL3A	},
+{"gsldgt",	"t,b,d",	0xc8000017,	0xfc0007ff,	WR_t|RD_b|LDD,	RD_d,	IL3A	},
+{"gssble",	"t,b,d",	0xe8000010,	0xfc0007ff,	RD_t|RD_b|SM,	RD_d,	IL3A	},
+{"gssbgt",	"t,b,d",	0xe8000011,	0xfc0007ff,	RD_t|RD_b|SM,	RD_d,	IL3A	},
+{"gsshle",	"t,b,d",	0xe8000012,	0xfc0007ff,	RD_t|RD_b|SM,	RD_d,	IL3A	},
+{"gsshgt",	"t,b,d",	0xe8000013,	0xfc0007ff,	RD_t|RD_b|SM,	RD_d,	IL3A	},
+{"gsswle",	"t,b,d",	0xe8000014,	0xfc0007ff,	RD_t|RD_b|SM,	RD_d,	IL3A	},
+{"gsswgt",	"t,b,d",	0xe8000015,	0xfc0007ff,	RD_t|RD_b|SM,	RD_d,	IL3A	},
+{"gssdle",	"t,b,d",	0xe8000016,	0xfc0007ff,	RD_t|RD_b|SM,	RD_d,	IL3A	},
+{"gssdgt",	"t,b,d",	0xe8000017,	0xfc0007ff,	RD_t|RD_b|SM,	RD_d,	IL3A	},
+{"gslwlec1",	"T,b,d",	0xc8000018,	0xfc0007ff,	WR_T|RD_b|LDD,	RD_d,	IL3A	},
+{"gslwgtc1",	"T,b,d",	0xc8000019,	0xfc0007ff,	WR_T|RD_b|LDD,	RD_d,	IL3A	},
+{"gsldlec1",	"T,b,d",	0xc800001a,	0xfc0007ff,	WR_T|RD_b|LDD,	RD_d,	IL3A	},
+{"gsldgtc1",	"T,b,d",	0xc800001b,	0xfc0007ff,	WR_T|RD_b|LDD,	RD_d,	IL3A	},
+{"gsswlec1",	"T,b,d",	0xe800001c,	0xfc0007ff,	RD_T|RD_b|SM,	RD_d,	IL3A	},
+{"gsswgtc1",	"T,b,d",	0xe800001d,	0xfc0007ff,	RD_T|RD_b|SM,	RD_d,	IL3A	},
+{"gssdlec1",	"T,b,d",	0xe800001e,	0xfc0007ff,	RD_T|RD_b|SM,	RD_d,	IL3A	},
+{"gssdgtc1",	"T,b,d",	0xe800001f,	0xfc0007ff,	RD_T|RD_b|SM,	RD_d,	IL3A	},
+{"gslwlc1",	"T,+a(b)",	0xc8000004,	0xfc00c03f,	WR_T|RD_b|LDD,	0,	IL3A	},
+{"gslwrc1",	"T,+a(b)",	0xc8000005,	0xfc00c03f,	WR_T|RD_b|LDD,	0,	IL3A	},
+{"gsldlc1",	"T,+a(b)",	0xc8000006,	0xfc00c03f,	WR_T|RD_b|LDD,	0,	IL3A	},
+{"gsldrc1",	"T,+a(b)",	0xc8000007,	0xfc00c03f,	WR_T|RD_b|LDD,	0,	IL3A	},
+{"gsswlc1",	"T,+a(b)",	0xe8000004,	0xfc00c03f,	RD_T|RD_b|SM,	0,	IL3A	},
+{"gsswrc1",	"T,+a(b)",	0xe8000005,	0xfc00c03f,	RD_T|RD_b|SM,	0,	IL3A	},
+{"gssdlc1",	"T,+a(b)",	0xe8000006,	0xfc00c03f,	RD_T|RD_b|SM,	0,	IL3A	},
+{"gssdrc1",	"T,+a(b)",	0xe8000007,	0xfc00c03f,	RD_T|RD_b|SM,	0,	IL3A	},
+{"gslbx",	"t,+b(b,d)",	0xd8000000,	0xfc000007,	WR_t|RD_b|LDD,	RD_d,	IL3A	},
+{"gslhx",	"t,+b(b,d)",	0xd8000001,	0xfc000007,	WR_t|RD_b|LDD,	RD_d,	IL3A	},
+{"gslwx",	"t,+b(b,d)",	0xd8000002,	0xfc000007,	WR_t|RD_b|LDD,	RD_d,	IL3A	},
+{"gsldx",	"t,+b(b,d)",	0xd8000003,	0xfc000007,	WR_t|RD_b|LDD,	RD_d,	IL3A	},
+{"gssbx",	"t,+b(b,d)",	0xf8000000,	0xfc000007,	RD_t|RD_b|SM,	RD_d,	IL3A	},
+{"gsshx",	"t,+b(b,d)",	0xf8000001,	0xfc000007,	RD_t|RD_b|SM,	RD_d,	IL3A	},
+{"gsswx",	"t,+b(b,d)",	0xf8000002,	0xfc000007,	RD_t|RD_b|SM,	RD_d,	IL3A	},
+{"gssdx",	"t,+b(b,d)",	0xf8000003,	0xfc000007,	RD_t|RD_b|SM,	RD_d,	IL3A	},
+{"gslwxc1",	"T,+b(b,d)",	0xd8000006,	0xfc000007,	WR_T|RD_b|LDD,	RD_d,	IL3A	},
+{"gsldxc1",	"T,+b(b,d)",	0xd8000007,	0xfc000007,	WR_T|RD_b|LDD,	RD_d,	IL3A	},
+{"gsswxc1",	"T,+b(b,d)",	0xf8000006,	0xfc000007,	RD_T|RD_b|SM,	RD_d,	IL3A	},
+{"gssdxc1",	"T,+b(b,d)",	0xf8000007,	0xfc000007,	RD_T|RD_b|SM,	RD_d,	IL3A	},
+{"gslq",	"+z,t,+c(b)",	0xc8000020,	0xfc008020,	WR_t|RD_b|LDD,	WR_z,	IL3A	},
+{"gssq",	"+z,t,+c(b)",	0xe8000020,	0xfc008020,	RD_t|RD_b|SM,	RD_z,	IL3A	},
+{"gslqc1",	"+Z,T,+c(b)",	0xc8008020,	0xfc008020,	WR_T|RD_b|LDD,	WR_Z,	IL3A	},
+{"gssqc1",	"+Z,T,+c(b)",	0xe8008020,	0xfc008020,	RD_T|RD_b|SM,	RD_Z,	IL3A	},
+
 {"abs",     "d,v",	0,    (int) M_ABS,	INSN_MACRO,		0,		I1	},
 {"abs.s",   "D,V",	0x46000005, 0xffff003f,	WR_D|RD_S|FP_S,		0,		I1	},
 {"abs.d",   "D,V",	0x46200005, 0xffff003f,	WR_D|RD_S|FP_D,		0,		I1	},
@@ -206,7 +273,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"add",     "d,v,t",	0x00000020, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I1	},
 {"add",     "t,r,I",	0,    (int) M_ADD_I,	INSN_MACRO,		0,		I1	},
 {"add",	"D,S,T",	0x45c00000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_S,	0,	IL2E	},
-{"add",	"D,S,T",	0x4b40000c,	0xffe0003f,	RD_S|RD_T|WR_D|FP_S,	0,	IL2F	},
+{"add",	"D,S,T",	0x4b40000c,	0xffe0003f,	RD_S|RD_T|WR_D|FP_S,	0,	IL2F|IL3A	},
 {"add.s",   "D,V,T",	0x46000000, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S,	0,		I1	},
 {"add.d",   "D,V,T",	0x46200000, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		I1	},
 {"add.ob",  "X,Y,Q",	0x7800000b, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
@@ -226,17 +293,17 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"addu",    "d,v,t",	0x00000021, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I1	},
 {"addu",    "t,r,I",	0,    (int) M_ADDU_I,	INSN_MACRO,		0,		I1	},
 {"addu",	"D,S,T",	0x45800000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_S,	0,	IL2E	},
-{"addu",	"D,S,T",	0x4b00000c,	0xffe0003f,	RD_S|RD_T|WR_D|FP_S,	0,	IL2F	},
+{"addu",	"D,S,T",	0x4b00000c,	0xffe0003f,	RD_S|RD_T|WR_D|FP_S,	0,	IL2F|IL3A	},
 {"alni.ob", "X,Y,Z,O",	0x78000018, 0xff00003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
 {"alni.ob", "D,S,T,%",	0x48000018, 0xff00003f,	WR_D|RD_S|RD_T, 	0,		N54	},
 {"alni.qh", "X,Y,Z,O",	0x7800001a, 0xff00003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX	},
-{"alnv.ps", "D,V,T,s",	0x4c00001e, 0xfc00003f,	WR_D|RD_S|RD_T|FP_D,	0,		I5_33	},
+{"alnv.ps", "D,V,T,s",	0x4c00001e, 0xfc00003f,	WR_D|RD_S|RD_T|RD_s|FP_D, 0,		I5_33	},
 {"alnv.ob", "X,Y,Z,s",	0x78000019, 0xfc00003f,	WR_D|RD_S|RD_T|RD_s|FP_D, 0,		MX|SB1	},
 {"alnv.qh", "X,Y,Z,s",	0x7800001b, 0xfc00003f,	WR_D|RD_S|RD_T|RD_s|FP_D, 0,		MX	},
 {"and",     "d,v,t",	0x00000024, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I1	},
 {"and",     "t,r,I",	0,    (int) M_AND_I,	INSN_MACRO,		0,		I1	},
 {"and",	"D,S,T",	0x47c00002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"and",	"D,S,T",	0x4bc00002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"and",	"D,S,T",	0x4bc00002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"and.ob",  "X,Y,Q",	0x7800000c, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
 {"and.ob",  "D,S,T",	0x4ac0000c, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
 {"and.ob",  "D,S,T[e]",	0x4800000c, 0xfe20003f,	WR_D|RD_S|RD_T,		0,		N54	},
@@ -552,7 +619,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dadd",    "d,v,t",	0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		I3	},
 {"dadd",    "t,r,I",	0,    (int) M_DADD_I,	INSN_MACRO,		0,		I3	},
 {"dadd",	"D,S,T",	0x45e00000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"dadd",	"D,S,T",	0x4b60000c,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"dadd",	"D,S,T",	0x4b60000c,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"daddi",   "t,r,j",	0x60000000, 0xfc000000, WR_t|RD_s,		0,		I3	},
 {"daddiu",  "t,r,j",	0x64000000, 0xfc000000, WR_t|RD_s,		0,		I3	},
 {"daddu",   "d,v,t",	0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		I3	},
@@ -669,25 +736,25 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dsll",    "d,w,>",	0x0000003c, 0xffe0003f, WR_d|RD_t,		0,		I3	}, /* dsll32 */
 {"dsll",    "d,w,<",	0x00000038, 0xffe0003f,	WR_d|RD_t,		0,		I3	},
 {"dsll",	"D,S,T",	0x45a00002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"dsll",	"D,S,T",	0x4b20000e,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"dsll",	"D,S,T",	0x4b20000e,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"dsrav",   "d,t,s",	0x00000017, 0xfc0007ff,	WR_d|RD_t|RD_s,		0,		I3	},
 {"dsra32",  "d,w,<",	0x0000003f, 0xffe0003f, WR_d|RD_t,		0,		I3	},
 {"dsra",    "d,w,s",	0x00000017, 0xfc0007ff,	WR_d|RD_t|RD_s,		0,		I3	}, /* dsrav */
 {"dsra",    "d,w,>",	0x0000003f, 0xffe0003f, WR_d|RD_t,		0,		I3	}, /* dsra32 */
 {"dsra",    "d,w,<",	0x0000003b, 0xffe0003f,	WR_d|RD_t,		0,		I3	},
 {"dsra",	"D,S,T",	0x45e00003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"dsra",	"D,S,T",	0x4b60000f,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"dsra",	"D,S,T",	0x4b60000f,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"dsrlv",   "d,t,s",	0x00000016, 0xfc0007ff,	WR_d|RD_t|RD_s,		0,		I3	},
 {"dsrl32",  "d,w,<",	0x0000003e, 0xffe0003f, WR_d|RD_t,		0,		I3	},
 {"dsrl",    "d,w,s",	0x00000016, 0xfc0007ff,	WR_d|RD_t|RD_s,		0,		I3	}, /* dsrlv */
 {"dsrl",    "d,w,>",	0x0000003e, 0xffe0003f, WR_d|RD_t,		0,		I3	}, /* dsrl32 */
 {"dsrl",    "d,w,<",	0x0000003a, 0xffe0003f,	WR_d|RD_t,		0,		I3	},
 {"dsrl",	"D,S,T",	0x45a00003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"dsrl",	"D,S,T",	0x4b20000f,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"dsrl",	"D,S,T",	0x4b20000f,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"dsub",    "d,v,t",	0x0000002e, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I3	},
 {"dsub",    "d,v,I",	0,    (int) M_DSUB_I,	INSN_MACRO,		0,		I3	},
 {"dsub",	"D,S,T",	0x45e00001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"dsub",	"D,S,T",	0x4b60000d,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"dsub",	"D,S,T",	0x4b60000d,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"dsubu",   "d,v,t",	0x0000002f, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I3	},
 {"dsubu",   "d,v,I",	0,    (int) M_DSUBU_I,	INSN_MACRO,		0,		I3	},
 {"dvpe",    "",		0x41600001, 0xffffffff, TRAP,			0,		MT32	},
@@ -745,7 +812,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"lca",     "t,A(b)",	0,    (int) M_LCA_AB,	INSN_MACRO,		0,		I1	},
 /* The macro has to be first to handle o32 correctly.  */
 {"ld",      "t,o(b)",	0,    (int) M_LD_OB,	INSN_MACRO,		0,		I1	},
-{"ld",      "t,o(b)",   0xdc000000, 0xfc000000, WR_t|RD_b,		0,		I3	},
+{"ld",      "t,o(b)",	0xdc000000, 0xfc000000, WR_t|RD_b,		0,		I3	},
 {"ld",      "t,A(b)",	0,    (int) M_LD_AB,	INSN_MACRO,		0,		I1	},
 {"ldaddw",  "t,b",	0x70000010, 0xfc00ffff,	SM|RD_t|WR_t|RD_b,	0,		XLR	},
 {"ldaddwu", "t,b",	0x70000011, 0xfc00ffff,	SM|RD_t|WR_t|RD_b,	0,		XLR	},
@@ -834,13 +901,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"madd",    "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,           0,		L1	},
 {"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,		I32|N55	},
 {"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      0,		G1	},
-{"madd",    "7,s,t",	0x70000000, 0xfc00e7ff, MOD_a|RD_s|RD_t,             0,         D33	},
+{"madd",    "7,s,t",	0x70000000, 0xfc00e7ff, MOD_a|RD_s|RD_t,             0,         D32	},
 {"madd",    "d,s,t",    0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,		G1	},
 {"maddp",   "s,t",      0x70000441, 0xfc00ffff,	RD_s|RD_t|MOD_HILO,	     0,		SMT	},
 {"maddu",   "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO,           0,		L1	},
 {"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,		I32|N55	},
 {"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      0,		G1	},
-{"maddu",   "7,s,t",	0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t,             0,         D33	},
+{"maddu",   "7,s,t",	0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t,             0,         D32	},
 {"maddu",   "d,s,t",    0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,		G1	},
 {"madd16",  "s,t",      0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO,	0,		N411    },
 {"max.ob",  "X,Y,Q",	0x78000007, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
@@ -901,7 +968,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"movf.s",  "D,S,N",    0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   0,		I4_32	},
 {"movf.ps", "D,S,N",	0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,	0,		I5_33	},
 {"movn",    "d,v,t",    0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 	0,		I4_32|IL2E|IL2F	},
-{"movnz",   "d,v,t",    0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 	0,		IL2E|IL2F	},
+{"movnz",   "d,v,t",    0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 	0,		IL2E|IL2F|IL3A	},
 {"ffc",     "d,v",	0x0000000b, 0xfc1f07ff,	WR_d|RD_s,		0,		L1	},
 {"movn.d",  "D,S,t",    0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,		I4_32	},
 {"movn.l",  "D,S,t",    0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,		MX|SB1	},
@@ -943,10 +1010,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"msub.ps",	"D,S,T",	0x71600019,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
 {"msub",    "s,t",      0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,	0,		L1    	},
 {"msub",    "s,t",      0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,		I32|N55 },
-{"msub",    "7,s,t",	0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33	},
+{"msub",    "7,s,t",	0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D32	},
 {"msubu",   "s,t",      0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,	0,		L1	},
 {"msubu",   "s,t",      0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,		I32|N55	},
-{"msubu",   "7,s,t",	0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33	},
+{"msubu",   "7,s,t",	0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D32	},
 {"mtpc",    "t,P",	0x4080c801, 0xffe0ffc1,	COD|RD_t|WR_C0,		0,		M1|N5	},
 {"mtps",    "t,P",	0x4080c800, 0xffe0ffc1,	COD|RD_t|WR_C0,		0,		M1|N5	},
 {"mtc0",    "t,G",	0x40800000, 0xffe007ff,	COD|RD_t|WR_C0|WR_CC,	0,		I1|IOCT	},
@@ -1035,11 +1102,11 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mulsl.ob", "S,k",	0x4bc00432, 0xffe007ff,	WR_CC|RD_S|RD_T,	0,		N54	},
 {"mulsl.qh", "Y,Q",	0x78200432, 0xfc2007ff,	RD_S|RD_T|FP_D,		WR_MACC,	MX	},
 {"mult",    "s,t",      0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0,		I1	},
-{"mult",    "7,s,t",	0x00000018, 0xfc00e7ff, WR_a|RD_s|RD_t,         0,              D33	},
+{"mult",    "7,s,t",	0x00000018, 0xfc00e7ff, WR_a|RD_s|RD_t,         0,              D32	},
 {"mult",    "d,s,t",    0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,		G1	},
 {"multp",   "s,t",	0x00000459, 0xfc00ffff,	RD_s|RD_t|MOD_HILO,	0,		SMT	},
 {"multu",   "s,t",      0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0,		I1	},
-{"multu",   "7,s,t",	0x00000019, 0xfc00e7ff, WR_a|RD_s|RD_t,         0,              D33	},
+{"multu",   "7,s,t",	0x00000019, 0xfc00e7ff, WR_a|RD_s|RD_t,         0,              D32	},
 {"multu",   "d,s,t",    0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,		G1	},
 {"mulu",    "d,s,t",	0x00000059, 0xfc0007ff,	RD_s|RD_t|WR_HILO|WR_d,	0,		N5	},
 {"neg",     "d,w",	0x00000022, 0xffe007ff,	WR_d|RD_t,		0,		I1	}, /* sub 0 */
@@ -1070,7 +1137,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"nor",     "d,v,t",	0x00000027, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I1	},
 {"nor",     "t,r,I",	0,    (int) M_NOR_I,	INSN_MACRO,		0,		I1	},
 {"nor",	"D,S,T",	0x47a00002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"nor",	"D,S,T",	0x4ba00002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"nor",	"D,S,T",	0x4ba00002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"nor.ob",  "X,Y,Q",	0x7800000f, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
 {"nor.ob",  "D,S,T",	0x4ac0000f, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
 {"nor.ob",  "D,S,T[e]",	0x4800000f, 0xfe20003f,	WR_D|RD_S|RD_T,		0,		N54	},
@@ -1080,7 +1147,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"or",      "d,v,t",	0x00000025, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I1	},
 {"or",      "t,r,I",	0,    (int) M_OR_I,	INSN_MACRO,		0,		I1	},
 {"or",	"D,S,T",	0x45a00000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"or",	"D,S,T",	0x4b20000c,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"or",	"D,S,T",	0x4b20000c,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"or.ob",   "X,Y,Q",	0x7800000e, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
 {"or.ob",   "D,S,T",	0x4ac0000e, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
 {"or.ob",   "D,S,T[e]",	0x4800000e, 0xfe20003f,	WR_D|RD_S|RD_T,		0,		N54	},
@@ -1207,7 +1274,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"seq",     "d,v,t",	0,    (int) M_SEQ,	INSN_MACRO,		0,		I1	},
 {"seq",     "d,v,I",	0,    (int) M_SEQ_I,	INSN_MACRO,		0,		I1	},
 {"seq",	"S,T",		0x46a00032,	0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,	IL2E	},
-{"seq",	"S,T",		0x4ba0000c,	0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,	IL2F	},
+{"seq",	"S,T",		0x4ba0000c,	0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,	IL2F|IL3A	},
 {"seqi",    "t,r,+Q",	0x7000002e, 0xfc00003f, WR_t|RD_s,		0,		IOCT	},
 {"sge",     "d,v,t",	0,    (int) M_SGE,	INSN_MACRO,		0,		I1	},
 {"sge",     "d,v,I",	0,    (int) M_SGE_I,	INSN_MACRO,		0,		I1	},
@@ -1236,16 +1303,16 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"sle",     "d,v,t",	0,    (int) M_SLE,	INSN_MACRO,		0,		I1	},
 {"sle",     "d,v,I",	0,    (int) M_SLE_I,	INSN_MACRO,		0,		I1	},
 {"sle",	"S,T",		0x46a0003e,	0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,	IL2E	},
-{"sle",	"S,T",		0x4ba0000e,	0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,	IL2F	},
+{"sle",	"S,T",		0x4ba0000e,	0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,	IL2F|IL3A	},
 {"sleu",    "d,v,t",	0,    (int) M_SLEU,	INSN_MACRO,		0,		I1	},
 {"sleu",    "d,v,I",	0,    (int) M_SLEU_I,	INSN_MACRO,		0,		I1	},
 {"sleu",	"S,T",		0x4680003e,	0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,	IL2E	},
-{"sleu",	"S,T",		0x4b80000e,	0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,	IL2F	},
+{"sleu",	"S,T",		0x4b80000e,	0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,	IL2F|IL3A	},
 {"sllv",    "d,t,s",	0x00000004, 0xfc0007ff,	WR_d|RD_t|RD_s,		0,		I1	},
 {"sll",     "d,w,s",	0x00000004, 0xfc0007ff,	WR_d|RD_t|RD_s,		0,		I1	}, /* sllv */
 {"sll",     "d,w,<",	0x00000000, 0xffe0003f,	WR_d|RD_t,		0,		I1	},
 {"sll",	"D,S,T",	0x45800002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"sll",	"D,S,T",	0x4b00000e,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"sll",	"D,S,T",	0x4b00000e,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"sll.ob",  "X,Y,Q",	0x78000010, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
 {"sll.ob",  "D,S,T[e]",	0x48000010, 0xfe20003f,	WR_D|RD_S|RD_T,		0,		N54	},
 {"sll.ob",  "D,S,k",	0x4bc00010, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
@@ -1253,13 +1320,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"slt",     "d,v,t",	0x0000002a, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I1	},
 {"slt",     "d,v,I",	0,    (int) M_SLT_I,	INSN_MACRO,		0,		I1	},
 {"slt",	"S,T",		0x46a0003c,	0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,	IL2E	},
-{"slt",	"S,T",		0x4ba0000d,	0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,	IL2F	},
+{"slt",	"S,T",		0x4ba0000d,	0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,	IL2F|IL3A	},
 {"slti",    "t,r,j",	0x28000000, 0xfc000000,	WR_t|RD_s,		0,		I1	},
 {"sltiu",   "t,r,j",	0x2c000000, 0xfc000000,	WR_t|RD_s,		0,		I1	},
 {"sltu",    "d,v,t",	0x0000002b, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I1	},
 {"sltu",    "d,v,I",	0,    (int) M_SLTU_I,	INSN_MACRO,		0,		I1	},
 {"sltu",	"S,T",		0x4680003c,	0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,	IL2E	},
-{"sltu",	"S,T",		0x4b80000d,	0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,	IL2F	},
+{"sltu",	"S,T",		0x4b80000d,	0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,	IL2F|IL3A	},
 {"sne",	    "d,v,t",	0x7000002b, 0xfc0007ff, WR_d|RD_s|RD_t,		0,		IOCT	},
 {"sne",     "d,v,t",	0,    (int) M_SNE,	INSN_MACRO,		0,		I1	},
 {"sne",     "d,v,I",	0,    (int) M_SNE_I,	INSN_MACRO,		0,		I1	},
@@ -1271,13 +1338,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"sra",     "d,w,s",	0x00000007, 0xfc0007ff,	WR_d|RD_t|RD_s,		0,		I1	}, /* srav */
 {"sra",     "d,w,<",	0x00000003, 0xffe0003f,	WR_d|RD_t,		0,		I1	},
 {"sra",	"D,S,T",	0x45c00003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"sra",	"D,S,T",	0x4b40000f,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"sra",	"D,S,T",	0x4b40000f,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"sra.qh",  "X,Y,Q",	0x78200013, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX	},
 {"srlv",    "d,t,s",	0x00000006, 0xfc0007ff,	WR_d|RD_t|RD_s,		0,		I1	},
 {"srl",     "d,w,s",	0x00000006, 0xfc0007ff,	WR_d|RD_t|RD_s,		0,		I1	}, /* srlv */
 {"srl",     "d,w,<",	0x00000002, 0xffe0003f,	WR_d|RD_t,		0,		I1	},
 {"srl",	"D,S,T",	0x45800003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"srl",	"D,S,T",	0x4b00000f,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"srl",	"D,S,T",	0x4b00000f,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"srl.ob",  "X,Y,Q",	0x78000012, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
 {"srl.ob",  "D,S,T[e]",	0x48000012, 0xfe20003f,	WR_D|RD_S|RD_T,		0,		N54	},
 {"srl.ob",  "D,S,k",	0x4bc00012, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
@@ -1287,7 +1354,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"sub",     "d,v,t",	0x00000022, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I1	},
 {"sub",     "d,v,I",	0,    (int) M_SUB_I,	INSN_MACRO,		0,		I1	},
 {"sub",	"D,S,T",	0x45c00001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_S,	0,	IL2E	},
-{"sub",	"D,S,T",	0x4b40000d,	0xffe0003f,	RD_S|RD_T|WR_D|FP_S,	0,	IL2F	},
+{"sub",	"D,S,T",	0x4b40000d,	0xffe0003f,	RD_S|RD_T|WR_D|FP_S,	0,	IL2F|IL3A	},
 {"sub.d",   "D,V,T",	0x46200001, 0xffe0003f,	WR_D|RD_S|RD_T|FP_D,	0,		I1	},
 {"sub.s",   "D,V,T",	0x46000001, 0xffe0003f,	WR_D|RD_S|RD_T|FP_S,	0,		I1	},
 {"sub.ob",  "X,Y,Q",	0x7800000a, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
@@ -1304,7 +1371,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"subu",    "d,v,t",	0x00000023, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I1	},
 {"subu",    "d,v,I",	0,    (int) M_SUBU_I,	INSN_MACRO,		0,		I1	},
 {"subu",	"D,S,T",	0x45800001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_S,	0,	IL2E	},
-{"subu",	"D,S,T",	0x4b00000d,	0xffe0003f,	RD_S|RD_T|WR_D|FP_S,	0,	IL2F	},
+{"subu",	"D,S,T",	0x4b00000d,	0xffe0003f,	RD_S|RD_T|WR_D|FP_S,	0,	IL2F|IL3A	},
 {"suspend", "",         0x42000022, 0xffffffff,	0,			0,		V1	},
 {"suxc1",   "S,t(b)",   0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D,	0,		I5_33|N55},
 {"sw",      "t,o(b)",	0xac000000, 0xfc000000,	SM|RD_t|RD_b,		0,		I1	},
@@ -1422,7 +1489,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"xor",     "d,v,t",	0x00000026, 0xfc0007ff,	WR_d|RD_s|RD_t,		0,		I1	},
 {"xor",     "t,r,I",	0,    (int) M_XOR_I,	INSN_MACRO,		0,		I1	},
 {"xor",	"D,S,T",	0x47800002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"xor",	"D,S,T",	0x4b800002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"xor",	"D,S,T",	0x4b800002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"xor.ob",  "X,Y,Q",	0x7800000d, 0xfc20003f,	WR_D|RD_S|RD_T|FP_D,	0,		MX|SB1	},
 {"xor.ob",  "D,S,T",	0x4ac0000d, 0xffe0003f,	WR_D|RD_S|RD_T,		0,		N54	},
 {"xor.ob",  "D,S,T[e]",	0x4800000d, 0xfe20003f,	WR_D|RD_S|RD_T,		0,		N54	},
@@ -1837,146 +1904,158 @@ const struct mips_opcode mips_builtin_opcodes[] =
 /* ST Microelectronics Loongson-2E and -2F.  */
 {"mult.g",	"d,s,t",	0x7c000018,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2E	},
 {"mult.g",	"d,s,t",	0x70000010,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2F	},
+{"gsmult",	"d,s,t",	0x70000010,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL3A	},
 {"multu.g",	"d,s,t",	0x7c000019,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2E	},
 {"multu.g",	"d,s,t",	0x70000012,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2F	},
+{"gsmultu",	"d,s,t",	0x70000012,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL3A	},
 {"dmult.g",	"d,s,t",	0x7c00001c,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2E	},
 {"dmult.g",	"d,s,t",	0x70000011,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2F	},
+{"gsdmult",	"d,s,t",	0x70000011,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL3A	},
 {"dmultu.g",	"d,s,t",	0x7c00001d,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2E	},
 {"dmultu.g",	"d,s,t",	0x70000013,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2F	},
+{"gsdmultu",	"d,s,t",	0x70000013,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL3A	},
 {"div.g",	"d,s,t",	0x7c00001a,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2E	},
 {"div.g",	"d,s,t",	0x70000014,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2F	},
+{"gsdiv",	"d,s,t",	0x70000014,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL3A	},
 {"divu.g",	"d,s,t",	0x7c00001b,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2E	},
 {"divu.g",	"d,s,t",	0x70000016,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2F	},
+{"gsdivu",	"d,s,t",	0x70000016,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL3A	},
 {"ddiv.g",	"d,s,t",	0x7c00001e,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2E	},
 {"ddiv.g",	"d,s,t",	0x70000015,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2F	},
+{"gsddiv",	"d,s,t",	0x70000015,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL3A	},
 {"ddivu.g",	"d,s,t",	0x7c00001f,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2E	},
 {"ddivu.g",	"d,s,t",	0x70000017,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2F	},
+{"gsddivu",	"d,s,t",	0x70000017,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL3A	},
 {"mod.g",	"d,s,t",	0x7c000022,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2E	},
 {"mod.g",	"d,s,t",	0x7000001c,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2F	},
+{"gsmod",	"d,s,t",	0x7000001c,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL3A	},
 {"modu.g",	"d,s,t",	0x7c000023,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2E	},
 {"modu.g",	"d,s,t",	0x7000001e,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2F	},
+{"gsmodu",	"d,s,t",	0x7000001e,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL3A	},
 {"dmod.g",	"d,s,t",	0x7c000026,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2E	},
 {"dmod.g",	"d,s,t",	0x7000001d,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2F	},
+{"gsdmod",	"d,s,t",	0x7000001d,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL3A	},
 {"dmodu.g",	"d,s,t",	0x7c000027,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2E	},
 {"dmodu.g",	"d,s,t",	0x7000001f,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL2F	},
+{"gsdmodu",	"d,s,t",	0x7000001f,	0xfc0007ff,	RD_s|RD_t|WR_d,	0,	IL3A	},
 {"packsshb",	"D,S,T",	0x47400002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"packsshb",	"D,S,T",	0x4b400002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"packsshb",	"D,S,T",	0x4b400002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"packsswh",	"D,S,T",	0x47200002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"packsswh",	"D,S,T",	0x4b200002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"packsswh",	"D,S,T",	0x4b200002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"packushb",	"D,S,T",	0x47600002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"packushb",	"D,S,T",	0x4b600002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"packushb",	"D,S,T",	0x4b600002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"paddb",	"D,S,T",	0x47c00000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"paddb",	"D,S,T",	0x4bc00000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"paddb",	"D,S,T",	0x4bc00000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"paddh",	"D,S,T",	0x47400000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"paddh",	"D,S,T",	0x4b400000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"paddh",	"D,S,T",	0x4b400000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"paddw",	"D,S,T",	0x47600000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"paddw",	"D,S,T",	0x4b600000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"paddw",	"D,S,T",	0x4b600000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"paddd",	"D,S,T",	0x47e00000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"paddd",	"D,S,T",	0x4be00000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"paddd",	"D,S,T",	0x4be00000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"paddsb",	"D,S,T",	0x47800000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"paddsb",	"D,S,T",	0x4b800000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"paddsb",	"D,S,T",	0x4b800000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"paddsh",	"D,S,T",	0x47000000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"paddsh",	"D,S,T",	0x4b000000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"paddsh",	"D,S,T",	0x4b000000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"paddusb",	"D,S,T",	0x47a00000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"paddusb",	"D,S,T",	0x4ba00000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"paddusb",	"D,S,T",	0x4ba00000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"paddush",	"D,S,T",	0x47200000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"paddush",	"D,S,T",	0x4b200000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"paddush",	"D,S,T",	0x4b200000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"pandn",	"D,S,T",	0x47e00002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pandn",	"D,S,T",	0x4be00002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"pandn",	"D,S,T",	0x4be00002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"pavgb",	"D,S,T",	0x46600000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pavgb",	"D,S,T",	0x4b200008,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"pavgb",	"D,S,T",	0x4b200008,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"pavgh",	"D,S,T",	0x46400000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pavgh",	"D,S,T",	0x4b000008,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"pavgh",	"D,S,T",	0x4b000008,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"pcmpeqb",	"D,S,T",	0x46c00001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pcmpeqb",	"D,S,T",	0x4b800009,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"pcmpeqb",	"D,S,T",	0x4b800009,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"pcmpeqh",	"D,S,T",	0x46800001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pcmpeqh",	"D,S,T",	0x4b400009,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"pcmpeqh",	"D,S,T",	0x4b400009,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"pcmpeqw",	"D,S,T",	0x46400001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pcmpeqw",	"D,S,T",	0x4b000009,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"pcmpeqw",	"D,S,T",	0x4b000009,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"pcmpgtb",	"D,S,T",	0x46e00001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pcmpgtb",	"D,S,T",	0x4ba00009,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"pcmpgtb",	"D,S,T",	0x4ba00009,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"pcmpgth",	"D,S,T",	0x46a00001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pcmpgth",	"D,S,T",	0x4b600009,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"pcmpgth",	"D,S,T",	0x4b600009,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"pcmpgtw",	"D,S,T",	0x46600001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pcmpgtw",	"D,S,T",	0x4b200009,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"pcmpgtw",	"D,S,T",	0x4b200009,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"pextrh",	"D,S,T",	0x45c00002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pextrh",	"D,S,T",	0x4b40000e,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"pextrh",	"D,S,T",	0x4b40000e,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"pinsrh_0",	"D,S,T",	0x47800003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pinsrh_0",	"D,S,T",	0x4b800003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"pinsrh_0",	"D,S,T",	0x4b800003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"pinsrh_1",	"D,S,T",	0x47a00003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pinsrh_1",	"D,S,T",	0x4ba00003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"pinsrh_1",	"D,S,T",	0x4ba00003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"pinsrh_2",	"D,S,T",	0x47c00003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pinsrh_2",	"D,S,T",	0x4bc00003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"pinsrh_2",	"D,S,T",	0x4bc00003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"pinsrh_3",	"D,S,T",	0x47e00003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pinsrh_3",	"D,S,T",	0x4be00003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"pinsrh_3",	"D,S,T",	0x4be00003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"pmaddhw",	"D,S,T",	0x45e00002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pmaddhw",	"D,S,T",	0x4b60000e,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"pmaddhw",	"D,S,T",	0x4b60000e,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"pmaxsh",	"D,S,T",	0x46800000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pmaxsh",	"D,S,T",	0x4b400008,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"pmaxsh",	"D,S,T",	0x4b400008,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"pmaxub",	"D,S,T",	0x46c00000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pmaxub",	"D,S,T",	0x4b800008,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"pmaxub",	"D,S,T",	0x4b800008,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"pminsh",	"D,S,T",	0x46a00000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pminsh",	"D,S,T",	0x4b600008,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"pminsh",	"D,S,T",	0x4b600008,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"pminub",	"D,S,T",	0x46e00000,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pminub",	"D,S,T",	0x4ba00008,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"pminub",	"D,S,T",	0x4ba00008,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"pmovmskb",	"D,S",		0x46a00005,	0xffff003f,	RD_S|WR_D|FP_D,	0,	IL2E	},
-{"pmovmskb",	"D,S",		0x4ba0000f,	0xffff003f,	RD_S|WR_D|FP_D,	0,	IL2F	},
+{"pmovmskb",	"D,S",		0x4ba0000f,	0xffff003f,	RD_S|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"pmulhuh",	"D,S,T",	0x46e00002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pmulhuh",	"D,S,T",	0x4ba0000a,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"pmulhuh",	"D,S,T",	0x4ba0000a,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"pmulhh",	"D,S,T",	0x46a00002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pmulhh",	"D,S,T",	0x4b60000a,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"pmulhh",	"D,S,T",	0x4b60000a,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"pmullh",	"D,S,T",	0x46800002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pmullh",	"D,S,T",	0x4b40000a,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"pmullh",	"D,S,T",	0x4b40000a,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"pmuluw",	"D,S,T",	0x46c00002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pmuluw",	"D,S,T",	0x4b80000a,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"pmuluw",	"D,S,T",	0x4b80000a,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"pasubub",	"D,S,T",	0x45a00001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pasubub",	"D,S,T",	0x4b20000d,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"pasubub",	"D,S,T",	0x4b20000d,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"biadd",	"D,S",		0x46800005,	0xffff003f,	RD_S|WR_D|FP_D,	0,	IL2E	},
-{"biadd",	"D,S",		0x4b80000f,	0xffff003f,	RD_S|WR_D|FP_D,	0,	IL2F	},
+{"biadd",	"D,S",		0x4b80000f,	0xffff003f,	RD_S|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"pshufh",	"D,S,T",	0x47000002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"pshufh",	"D,S,T",	0x4b000002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"pshufh",	"D,S,T",	0x4b000002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"psllh",	"D,S,T",	0x46600002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"psllh",	"D,S,T",	0x4b20000a,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"psllh",	"D,S,T",	0x4b20000a,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"psllw",	"D,S,T",	0x46400002,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"psllw",	"D,S,T",	0x4b00000a,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"psllw",	"D,S,T",	0x4b00000a,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"psrah",	"D,S,T",	0x46a00003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"psrah",	"D,S,T",	0x4b60000b,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"psrah",	"D,S,T",	0x4b60000b,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"psraw",	"D,S,T",	0x46800003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"psraw",	"D,S,T",	0x4b40000b,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"psraw",	"D,S,T",	0x4b40000b,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"psrlh",	"D,S,T",	0x46600003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"psrlh",	"D,S,T",	0x4b20000b,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"psrlh",	"D,S,T",	0x4b20000b,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"psrlw",	"D,S,T",	0x46400003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"psrlw",	"D,S,T",	0x4b00000b,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"psrlw",	"D,S,T",	0x4b00000b,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"psubb",	"D,S,T",	0x47c00001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"psubb",	"D,S,T",	0x4bc00001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"psubb",	"D,S,T",	0x4bc00001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"psubh",	"D,S,T",	0x47400001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"psubh",	"D,S,T",	0x4b400001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"psubh",	"D,S,T",	0x4b400001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"psubw",	"D,S,T",	0x47600001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"psubw",	"D,S,T",	0x4b600001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"psubw",	"D,S,T",	0x4b600001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"psubd",	"D,S,T",	0x47e00001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"psubd",	"D,S,T",	0x4be00001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"psubd",	"D,S,T",	0x4be00001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"psubsb",	"D,S,T",	0x47800001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"psubsb",	"D,S,T",	0x4b800001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"psubsb",	"D,S,T",	0x4b800001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"psubsh",	"D,S,T",	0x47000001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"psubsh",	"D,S,T",	0x4b000001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"psubsh",	"D,S,T",	0x4b000001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"psubusb",	"D,S,T",	0x47a00001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"psubusb",	"D,S,T",	0x4ba00001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"psubusb",	"D,S,T",	0x4ba00001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"psubush",	"D,S,T",	0x47200001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"psubush",	"D,S,T",	0x4b200001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"psubush",	"D,S,T",	0x4b200001,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"punpckhbh",	"D,S,T",	0x47600003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"punpckhbh",	"D,S,T",	0x4b600003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"punpckhbh",	"D,S,T",	0x4b600003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"punpckhhw",	"D,S,T",	0x47200003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"punpckhhw",	"D,S,T",	0x4b200003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"punpckhhw",	"D,S,T",	0x4b200003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"punpckhwd",	"D,S,T",	0x46e00003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"punpckhwd",	"D,S,T",	0x4ba0000b,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"punpckhwd",	"D,S,T",	0x4ba0000b,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"punpcklbh",	"D,S,T",	0x47400003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"punpcklbh",	"D,S,T",	0x4b400003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"punpcklbh",	"D,S,T",	0x4b400003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"punpcklhw",	"D,S,T",	0x47000003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"punpcklhw",	"D,S,T",	0x4b000003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"punpcklhw",	"D,S,T",	0x4b000003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"punpcklwd",	"D,S,T",	0x46c00003,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2E	},
-{"punpcklwd",	"D,S,T",	0x4b80000b,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F	},
+{"punpcklwd",	"D,S,T",	0x4b80000b,	0xffe0003f,	RD_S|RD_T|WR_D|FP_D,	0,	IL2F|IL3A	},
 {"sequ",	"S,T",		0x46800032,	0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,	IL2E	},
-{"sequ",	"S,T",		0x4b80000c,	0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,	IL2F	},
+{"sequ",	"S,T",		0x4b80000c,	0xffe007ff,	RD_S|RD_T|WR_CC|FP_D,	0,	IL2F|IL3A	},
 /* No hazard protection on coprocessor instructions--they shouldn't
    change the state of the processor and if they do it's up to the
    user to put in nops as necessary.  These are at the end so that the