X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Fmips-opc.c;h=e2386e886a8bb8a2b70c7a87f3955954338dd3c8;hb=8bf7d691eb8662b118fa709a530e64ac9e17e85d;hp=5fc17ba5652649255d5fe4ea5ca9d643c7b023f4;hpb=e93d71992f11429c856aecc56b27cb0c3e5ee20e;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index 5fc17ba565..e2386e886a 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -86,17 +86,17 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * #define L1 INSN_4010 #define V1 INSN_4100 #define T3 INSN_3900 +#define M1 INSN_10000 +#define SB1 INSN_SB1 #define G1 (T3 \ ) -#define G2 (T3 \ +#define G2 (T3 \ ) -#define G3 (I4 \ - ) - -#define G6 INSN_GP32 +#define G3 (I4 \ + ) /* The order of overloaded instructions matters. Label arguments and register arguments look the same. Instructions that can have either @@ -115,12 +115,13 @@ const struct mips_opcode mips_builtin_opcodes[] = instruction name anyhow. */ /* name, args, match, mask, pinfo, membership */ {"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, I32|G3 }, +{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, I4 }, {"nop", "", 0x00000000, 0xffffffff, 0, I1 }, {"ssnop", "", 0x00000040, 0xffffffff, 0, I32 }, {"li", "t,j", 0x24000000, 0xffe00000, WR_t, I1 }, /* addiu */ {"li", "t,i", 0x34000000, 0xffe00000, WR_t, I1 }, /* ori */ {"li", "t,I", 0, (int) M_LI, INSN_MACRO, I1 }, -{"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, I1|G6 },/* or */ +{"move", "d,s", 0, (int) M_MOVE, INSN_MACRO, I1 }, {"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, I3 },/* daddu */ {"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, I1 },/* addu */ {"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, I1 },/* or */ @@ -172,57 +173,57 @@ const struct mips_opcode mips_builtin_opcodes[] = {"beq", "s,t,p", 0x10000000, 0xfc000000, CBD|RD_s|RD_t, I1 }, {"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, I1 }, {"beql", "s,t,p", 0x50000000, 0xfc000000, CBL|RD_s|RD_t, I2|T3 }, -{"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, I2 }, +{"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, I2|T3 }, {"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, I1 }, {"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO, I1 }, -{"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, I2 }, -{"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, I2 }, +{"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, I2|T3 }, +{"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, I2|T3 }, {"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO, I1 }, {"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO, I1 }, -{"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, I2 }, -{"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, I2 }, +{"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, I2|T3 }, +{"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, I2|T3 }, {"bgez", "s,p", 0x04010000, 0xfc1f0000, CBD|RD_s, I1 }, {"bgezl", "s,p", 0x04030000, 0xfc1f0000, CBL|RD_s, I2|T3 }, {"bgezal", "s,p", 0x04110000, 0xfc1f0000, CBD|RD_s|WR_31, I1 }, -{"bgezall", "s,p", 0x04130000, 0xfc1f0000, CBL|RD_s, I2|T3 }, +{"bgezall", "s,p", 0x04130000, 0xfc1f0000, CBL|RD_s|WR_31, I2|T3 }, {"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO, I1 }, {"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO, I1 }, -{"bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, I2 }, -{"bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, I2 }, +{"bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, I2|T3 }, +{"bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, I2|T3 }, {"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO, I1 }, {"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO, I1 }, -{"bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, I2 }, -{"bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, I2 }, +{"bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, I2|T3 }, +{"bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, I2|T3 }, {"bgtz", "s,p", 0x1c000000, 0xfc1f0000, CBD|RD_s, I1 }, {"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, CBL|RD_s, I2|T3 }, {"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO, I1 }, {"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO, I1 }, -{"blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, I2 }, -{"blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, I2 }, +{"blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, I2|T3 }, +{"blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, I2|T3 }, {"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO, I1 }, {"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO, I1 }, -{"bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, I2 }, -{"bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, I2 }, +{"bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, I2|T3 }, +{"bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, I2|T3 }, {"blez", "s,p", 0x18000000, 0xfc1f0000, CBD|RD_s, I1 }, {"blezl", "s,p", 0x58000000, 0xfc1f0000, CBL|RD_s, I2|T3 }, {"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO, I1 }, {"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO, I1 }, -{"bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, I2 }, -{"bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, I2 }, +{"bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, I2|T3 }, +{"bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, I2|T3 }, {"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO, I1 }, {"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO, I1 }, -{"bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, I2 }, -{"bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, I2 }, +{"bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, I2|T3 }, +{"bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, I2|T3 }, {"bltz", "s,p", 0x04000000, 0xfc1f0000, CBD|RD_s, I1 }, {"bltzl", "s,p", 0x04020000, 0xfc1f0000, CBL|RD_s, I2|T3 }, {"bltzal", "s,p", 0x04100000, 0xfc1f0000, CBD|RD_s|WR_31, I1 }, -{"bltzall", "s,p", 0x04120000, 0xfc1f0000, CBL|RD_s, I2|T3 }, +{"bltzall", "s,p", 0x04120000, 0xfc1f0000, CBL|RD_s|WR_31, I2|T3 }, {"bnez", "s,p", 0x14000000, 0xfc1f0000, CBD|RD_s, I1 }, {"bnezl", "s,p", 0x54000000, 0xfc1f0000, CBL|RD_s, I2|T3 }, {"bne", "s,t,p", 0x14000000, 0xfc000000, CBD|RD_s|RD_t, I1 }, {"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, I1 }, {"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t, I2|T3 }, -{"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, I2 }, +{"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, I2|T3 }, {"break", "", 0x0000000d, 0xffffffff, TRAP, I1 }, {"break", "B", 0x0000000d, 0xfc00003f, TRAP, I32 }, {"break", "c", 0x0000000d, 0xfc00ffff, TRAP, I1 }, @@ -251,8 +252,6 @@ const struct mips_opcode mips_builtin_opcodes[] = {"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, {"c.ueq.ps","S,T", 0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, {"c.ueq.ps","M,S,T", 0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, -{"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, -{"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, {"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, {"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, {"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, @@ -265,8 +264,6 @@ const struct mips_opcode mips_builtin_opcodes[] = {"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, {"c.ult.ps","S,T", 0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, {"c.ult.ps","M,S,T", 0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, -{"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, -{"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, {"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, {"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, {"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, @@ -305,6 +302,8 @@ const struct mips_opcode mips_builtin_opcodes[] = {"c.ngl.ps","M,S,T", 0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, {"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, {"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, +{"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, +{"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, {"c.lt.ps", "S,T", 0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, {"c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, {"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, @@ -315,6 +314,8 @@ const struct mips_opcode mips_builtin_opcodes[] = {"c.nge.ps","M,S,T", 0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, {"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, {"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|I32 }, +{"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, +{"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|I32 }, {"c.le.ps", "S,T", 0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, {"c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, {"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, @@ -384,6 +385,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, I1 }, {"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 }, {"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 }, +{"div.ps", "D,V,T", 0x46c00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, SB1 }, /* For divu, see the comments about div. */ {"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, I1 }, {"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO, I1 }, @@ -558,6 +560,8 @@ const struct mips_opcode mips_builtin_opcodes[] = {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, G1 }, {"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, G1 }, {"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO, V1 }, +{"mfpc", "t,P", 0x4000c801, 0xffe0ffc1, LCD|WR_t|RD_C0, M1 }, +{"mfps", "t,P", 0x4000c800, 0xffe0ffc1, LCD|WR_t|RD_C0, M1 }, {"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, I1 }, {"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, I32 }, {"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 }, @@ -595,6 +599,8 @@ const struct mips_opcode mips_builtin_opcodes[] = {"msub", "s,t", 0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO, I32 }, {"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, L1 }, {"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO, I32 }, +{"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0, M1 }, +{"mtps", "t,P", 0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0, M1 }, {"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, I1 }, {"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, I32 }, {"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, I1 }, @@ -641,14 +647,14 @@ const struct mips_opcode mips_builtin_opcodes[] = {"pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 }, {"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 }, -/* pref is at the start of the table. */ -{"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, I4 }, + /* pref and prefx are at the start of the table. */ {"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 }, {"puu.ps", "D,V,T", 0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 }, {"recip.d", "D,S", 0x46200015, 0xffff003f, WR_D|RD_S|FP_D, I4 }, {"recip.s", "D,S", 0x46000015, 0xffff003f, WR_D|RD_S|FP_S, I4 }, +{"recip.ps","D,S", 0x46c00015, 0xffff003f, WR_D|RD_S|FP_D, SB1 }, {"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, I1 }, {"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, I1 }, {"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, I1 }, @@ -666,6 +672,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_D|RD_S|FP_S, I2 }, {"rsqrt.d", "D,S", 0x46200016, 0xffff003f, WR_D|RD_S|FP_D, I4 }, {"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D|RD_S|FP_S, I4 }, +{"rsqrt.ps","D,S", 0x46c00016, 0xffff003f, WR_D|RD_S|FP_D, SB1 }, {"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, I1 }, {"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, I1 }, {"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, I2 }, @@ -727,6 +734,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO, I1 }, {"sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_D|RD_S|FP_D, I2 }, {"sqrt.s", "D,S", 0x46000004, 0xffff003f, WR_D|RD_S|FP_S, I2 }, +{"sqrt.ps", "D,S", 0x46c00004, 0xffff003f, WR_D|RD_S|FP_D, SB1 }, {"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, {"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, I1 }, /* srav */ {"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_d|RD_t, I1 }, @@ -737,7 +745,7 @@ const struct mips_opcode mips_builtin_opcodes[] = {"standby", "", 0x42000021, 0xffffffff, 0, V1 }, {"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, {"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, I1 }, -{"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 }, +{"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I1 }, {"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, I1 }, {"sub.ps", "D,V,T", 0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, I5 }, {"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t, I1 }, @@ -838,7 +846,7 @@ const struct mips_opcode mips_builtin_opcodes[] = /* No hazard protection on coprocessor instructions--they shouldn't change the state of the processor and if they do it's up to the user to put in nops as necessary. These are at the end so that the - disasembler recognizes more specific versions first. */ + disassembler recognizes more specific versions first. */ {"c0", "C", 0x42000000, 0xfe000000, 0, I1 }, {"c1", "C", 0x46000000, 0xfe000000, 0, I1 }, {"c2", "C", 0x4a000000, 0xfe000000, 0, I1 }, @@ -858,10 +866,9 @@ const struct mips_opcode mips_builtin_opcodes[] = ((sizeof mips_builtin_opcodes) / (sizeof (mips_builtin_opcodes[0]))) const int bfd_mips_num_builtin_opcodes = MIPS_NUM_OPCODES; -/* const removed from the following to allow for dynamic extensions to the +/* const removed from the following to allow for dynamic extensions to the * built-in instruction set. */ struct mips_opcode *mips_opcodes = (struct mips_opcode *) mips_builtin_opcodes; int bfd_mips_num_opcodes = MIPS_NUM_OPCODES; #undef MIPS_NUM_OPCODES -