X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Fmt-desc.c;h=1a3441adfcaa8501b35f6316d242fb61c03073bb;hb=9494d9636612cd9bd22e38625fbc89147beafea7;hp=b633e976bc0ca93ab2db42429d74877486184434;hpb=87337981d937b6b00c55827ea15438e19c518884;p=deliverable%2Fbinutils-gdb.git

diff --git a/opcodes/mt-desc.c b/opcodes/mt-desc.c
index b633e976bc..1a3441adfc 100644
--- a/opcodes/mt-desc.c
+++ b/opcodes/mt-desc.c
@@ -2,7 +2,7 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996-2009 Free Software Foundation, Inc.
+Copyright (C) 1996-2017 Free Software Foundation, Inc.
 
 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
 
@@ -186,11 +186,7 @@ CGEN_KEYWORD mt_cgen_opval_h_spr =
 
 /* The hardware table.  */
 
-#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 #define A(a) (1 << CGEN_HW_##a)
-#else
-#define A(a) (1 << CGEN_HW_/**/a)
-#endif
 
 const CGEN_HW_ENTRY mt_cgen_hw_table[] =
 {
@@ -209,11 +205,7 @@ const CGEN_HW_ENTRY mt_cgen_hw_table[] =
 
 /* The instruction field table.  */
 
-#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 #define A(a) (1 << CGEN_IFLD_##a)
-#else
-#define A(a) (1 << CGEN_IFLD_/**/a)
-#endif
 
 const CGEN_IFLD mt_cgen_ifld_table[] =
 {
@@ -311,238 +303,230 @@ const CGEN_IFLD mt_cgen_ifld_table[] =
 
 /* The operand table.  */
 
-#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 #define A(a) (1 << CGEN_OPERAND_##a)
-#else
-#define A(a) (1 << CGEN_OPERAND_/**/a)
-#endif
-#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 #define OPERAND(op) MT_OPERAND_##op
-#else
-#define OPERAND(op) MT_OPERAND_/**/op
-#endif
 
 const CGEN_OPERAND mt_cgen_operand_table[] =
 {
 /* pc: program counter */
   { "pc", MT_OPERAND_PC, HW_H_PC, 0, 0,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_NIL] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_NIL] } },
     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 /* frsr1: register */
   { "frsr1", MT_OPERAND_FRSR1, HW_H_SPR, 23, 4,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_SR1] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_SR1] } },
     { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 /* frsr2: register */
   { "frsr2", MT_OPERAND_FRSR2, HW_H_SPR, 19, 4,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_SR2] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_SR2] } },
     { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 /* frdr: register */
   { "frdr", MT_OPERAND_FRDR, HW_H_SPR, 19, 4,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_DR] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_DR] } },
     { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 /* frdrrr: register */
   { "frdrrr", MT_OPERAND_FRDRRR, HW_H_SPR, 15, 4,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_DRRR] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_DRRR] } },
     { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 /* imm16: immediate value - sign extd */
   { "imm16", MT_OPERAND_IMM16, HW_H_SINT, 15, 16,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16S] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16S] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* imm16z: immediate value - zero extd */
   { "imm16z", MT_OPERAND_IMM16Z, HW_H_UINT, 15, 16,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16U] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16U] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* imm16o: immediate value */
   { "imm16o", MT_OPERAND_IMM16O, HW_H_UINT, 15, 16,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16S] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16S] } },
     { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 /* rc: rc */
   { "rc", MT_OPERAND_RC, HW_H_UINT, 15, 1,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* rcnum: rcnum */
   { "rcnum", MT_OPERAND_RCNUM, HW_H_UINT, 14, 3,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RCNUM] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RCNUM] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* contnum: context number */
   { "contnum", MT_OPERAND_CONTNUM, HW_H_UINT, 8, 9,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CONTNUM] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CONTNUM] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* rbbc: omega network configuration */
   { "rbbc", MT_OPERAND_RBBC, HW_H_UINT, 25, 2,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RBBC] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RBBC] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* colnum: column number */
   { "colnum", MT_OPERAND_COLNUM, HW_H_UINT, 18, 3,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_COLNUM] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_COLNUM] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* rownum: row number */
   { "rownum", MT_OPERAND_ROWNUM, HW_H_UINT, 14, 3,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ROWNUM] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ROWNUM] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* rownum1: row number */
   { "rownum1", MT_OPERAND_ROWNUM1, HW_H_UINT, 12, 3,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ROWNUM1] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ROWNUM1] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* rownum2: row number */
   { "rownum2", MT_OPERAND_ROWNUM2, HW_H_UINT, 9, 3,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ROWNUM2] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ROWNUM2] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* rc1: rc1 */
   { "rc1", MT_OPERAND_RC1, HW_H_UINT, 11, 1,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC1] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC1] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* rc2: rc2 */
   { "rc2", MT_OPERAND_RC2, HW_H_UINT, 6, 1,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC2] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC2] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* cbrb: data-bus orientation */
   { "cbrb", MT_OPERAND_CBRB, HW_H_UINT, 10, 1,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CBRB] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CBRB] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* cell: cell */
   { "cell", MT_OPERAND_CELL, HW_H_UINT, 9, 3,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CELL] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CELL] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* dup: dup */
   { "dup", MT_OPERAND_DUP, HW_H_UINT, 6, 1,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_DUP] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_DUP] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* ctxdisp: context displacement */
   { "ctxdisp", MT_OPERAND_CTXDISP, HW_H_UINT, 5, 6,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CTXDISP] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CTXDISP] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* fbdisp: frame buffer displacement */
   { "fbdisp", MT_OPERAND_FBDISP, HW_H_UINT, 15, 6,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_FBDISP] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_FBDISP] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* type: type */
   { "type", MT_OPERAND_TYPE, HW_H_UINT, 21, 2,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_TYPE] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_TYPE] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* mask: mask */
   { "mask", MT_OPERAND_MASK, HW_H_UINT, 25, 16,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_MASK] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_MASK] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* bankaddr: bank address */
   { "bankaddr", MT_OPERAND_BANKADDR, HW_H_UINT, 25, 13,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BANKADDR] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BANKADDR] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* incamt: increment amount */
   { "incamt", MT_OPERAND_INCAMT, HW_H_UINT, 19, 8,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_INCAMT] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_INCAMT] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* xmode: xmode */
   { "xmode", MT_OPERAND_XMODE, HW_H_UINT, 23, 1,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_XMODE] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_XMODE] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* mask1: mask1 */
   { "mask1", MT_OPERAND_MASK1, HW_H_UINT, 22, 3,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_MASK1] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_MASK1] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* ball: b_all */
   { "ball", MT_OPERAND_BALL, HW_H_UINT, 19, 1,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BALL] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BALL] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* brc: b_r_c */
   { "brc", MT_OPERAND_BRC, HW_H_UINT, 18, 3,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BRC] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BRC] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* rda: rd */
   { "rda", MT_OPERAND_RDA, HW_H_UINT, 25, 1,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RDA] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RDA] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* wr: wr */
   { "wr", MT_OPERAND_WR, HW_H_UINT, 24, 1,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_WR] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_WR] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* ball2: b_all2 */
   { "ball2", MT_OPERAND_BALL2, HW_H_UINT, 15, 1,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BALL2] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BALL2] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* brc2: b_r_c2 */
   { "brc2", MT_OPERAND_BRC2, HW_H_UINT, 14, 3,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BRC2] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BRC2] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* perm: perm */
   { "perm", MT_OPERAND_PERM, HW_H_UINT, 25, 2,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_PERM] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_PERM] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* a23: a23 */
   { "a23", MT_OPERAND_A23, HW_H_UINT, 23, 1,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_A23] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_A23] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* cr: c-r */
   { "cr", MT_OPERAND_CR, HW_H_UINT, 22, 3,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CR] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CR] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* cbs: cbs */
   { "cbs", MT_OPERAND_CBS, HW_H_UINT, 19, 2,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CBS] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CBS] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* incr: incr */
   { "incr", MT_OPERAND_INCR, HW_H_UINT, 17, 6,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_INCR] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_INCR] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* length: length */
   { "length", MT_OPERAND_LENGTH, HW_H_UINT, 15, 3,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_LENGTH] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_LENGTH] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* cbx: cbx */
   { "cbx", MT_OPERAND_CBX, HW_H_UINT, 14, 3,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CBX] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CBX] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* ccb: ccb */
   { "ccb", MT_OPERAND_CCB, HW_H_UINT, 11, 1,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CCB] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CCB] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* cdb: cdb */
   { "cdb", MT_OPERAND_CDB, HW_H_UINT, 10, 1,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CDB] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CDB] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* mode: mode */
   { "mode", MT_OPERAND_MODE, HW_H_UINT, 25, 2,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_MODE] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_MODE] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* id: i/d */
   { "id", MT_OPERAND_ID, HW_H_UINT, 14, 1,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ID] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ID] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* size: size */
   { "size", MT_OPERAND_SIZE, HW_H_UINT, 13, 14,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_SIZE] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_SIZE] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* fbincr: fb incr */
   { "fbincr", MT_OPERAND_FBINCR, HW_H_UINT, 23, 4,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_FBINCR] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_FBINCR] } },
     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 /* loopsize: immediate value */
   { "loopsize", MT_OPERAND_LOOPSIZE, HW_H_UINT, 7, 8,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_LOOPO] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_LOOPO] } },
     { 0|A(PCREL_ADDR), { { { (1<<MACH_MS2), 0 } } } }  },
 /* imm16l: immediate value */
   { "imm16l", MT_OPERAND_IMM16L, HW_H_UINT, 23, 16,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16L] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16L] } },
     { 0, { { { (1<<MACH_MS2), 0 } } } }  },
 /* rc3: rc3 */
   { "rc3", MT_OPERAND_RC3, HW_H_UINT, 7, 1,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC3] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC3] } },
     { 0, { { { (1<<MACH_MS2), 0 } } } }  },
 /* cb1sel: cb1sel */
   { "cb1sel", MT_OPERAND_CB1SEL, HW_H_UINT, 25, 3,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB1SEL] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB1SEL] } },
     { 0, { { { (1<<MACH_MS2), 0 } } } }  },
 /* cb2sel: cb2sel */
   { "cb2sel", MT_OPERAND_CB2SEL, HW_H_UINT, 22, 3,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB2SEL] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB2SEL] } },
     { 0, { { { (1<<MACH_MS2), 0 } } } }  },
 /* cb1incr: cb1incr */
   { "cb1incr", MT_OPERAND_CB1INCR, HW_H_SINT, 19, 6,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB1INCR] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB1INCR] } },
     { 0|A(SIGNED), { { { (1<<MACH_MS2), 0 } } } }  },
 /* cb2incr: cb2incr */
   { "cb2incr", MT_OPERAND_CB2INCR, HW_H_SINT, 13, 6,
-    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB2INCR] } }, 
+    { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB2INCR] } },
     { 0|A(SIGNED), { { { (1<<MACH_MS2), 0 } } } }  },
 /* sentinel */
   { 0, 0, 0, 0, 0,
@@ -556,11 +540,7 @@ const CGEN_OPERAND mt_cgen_operand_table[] =
 /* The instruction table.  */
 
 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
-#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 #define A(a) (1 << CGEN_INSN_##a)
-#else
-#define A(a) (1 << CGEN_INSN_/**/a)
-#endif
 
 static const CGEN_IBASE mt_cgen_insn_table[MAX_INSNS] =
 {
@@ -1190,11 +1170,7 @@ mt_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
    CGEN_CPU_OPEN_END:     terminates arguments
 
    ??? Simultaneous multiple isas might not make sense, but it's not (yet)
-   precluded.
-
-   ??? We only support ISO C stdargs here, not K&R.
-   Laziness, plus experiment to see if anything requires K&R - eventually
-   K&R will no longer be supported - e.g. GDB is currently trying this.  */
+   precluded.  */
 
 CGEN_CPU_DESC
 mt_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
@@ -1273,7 +1249,7 @@ mt_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
 
   /* Default to not allowing signed overflow.  */
   cd->signed_overflow_ok_p = 0;
-  
+
   return (CGEN_CPU_DESC) cd;
 }
 
@@ -1313,7 +1289,7 @@ mt_cgen_cpu_close (CGEN_CPU_DESC cd)
       for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
 	if (CGEN_INSN_RX (insns))
 	  regfree (CGEN_INSN_RX (insns));
-    }  
+    }
 
   if (cd->macro_insn_table.init_entries)
     free ((CGEN_INSN *) cd->macro_insn_table.init_entries);