X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Friscv-dis.c;h=40893c3dcb013eef4f067a300af136e013a4ef6f;hb=159653d8c0bcc45b479e4329c2e5f304fa942280;hp=764c4d4d256705aeed855484e791bd4eed6c0c39;hpb=827041555ac443bd57340060f3e034fd7b199dd8;p=deliverable%2Fbinutils-gdb.git

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 764c4d4d25..40893c3dcb 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -395,9 +395,13 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
 
   insnlen = riscv_insn_length (word);
 
+  /* RISC-V instructions are always little-endian.  */
+  info->endian_code = BFD_ENDIAN_LITTLE;
+
   info->bytes_per_chunk = insnlen % 4 == 0 ? 4 : 2;
   info->bytes_per_line = 8;
-  info->display_endian = info->endian;
+  /* We don't support constant pools, so this must be code.  */
+  info->display_endian = info->endian_code;
   info->insn_info_valid = 1;
   info->branch_delay_insns = 0;
   info->data_size = 0;