X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Friscv-dis.c;h=f26a46e0b34aa8c2e59530714f18d1126317a92b;hb=50d036364fb2a71b3ac9a0b0cdbe58296832a1b2;hp=20b685456d40043ca708854a7a8ffcb8366608c0;hpb=b52d3cfcfb472263eca181da37dfc0377978acba;p=deliverable%2Fbinutils-gdb.git
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 20b685456d..f26a46e0b3 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -1,5 +1,5 @@
/* RISC-V disassembler
- Copyright (C) 2011-2017 Free Software Foundation, Inc.
+ Copyright (C) 2011-2020 Free Software Foundation, Inc.
Contributed by Andrew Waterman (andrew@sifive.com).
Based on MIPS target.
@@ -21,16 +21,18 @@
see . */
#include "sysdep.h"
-#include "dis-asm.h"
+#include "disassemble.h"
#include "libiberty.h"
#include "opcode/riscv.h"
#include "opintl.h"
#include "elf-bfd.h"
#include "elf/riscv.h"
-#include
+#include "bfd_stdint.h"
#include
+static enum riscv_priv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE;
+
struct riscv_private_data
{
bfd_vma gp;
@@ -52,8 +54,8 @@ set_default_riscv_dis_options (void)
no_aliases = 0;
}
-static void
-parse_riscv_dis_option (const char *option)
+static bfd_boolean
+parse_riscv_dis_option_without_args (const char *option)
{
if (strcmp (option, "no-aliases") == 0)
no_aliases = 1;
@@ -63,9 +65,47 @@ parse_riscv_dis_option (const char *option)
riscv_fpr_names = riscv_fpr_names_numeric;
}
else
+ return FALSE;
+ return TRUE;
+}
+
+static void
+parse_riscv_dis_option (const char *option)
+{
+ char *equal, *value;
+
+ if (parse_riscv_dis_option_without_args (option))
+ return;
+
+ equal = strchr (option, '=');
+ if (equal == NULL)
{
- /* Invalid option. */
- fprintf (stderr, _("Unrecognized disassembler option: %s\n"), option);
+ /* The option without '=' should be defined above. */
+ opcodes_error_handler (_("unrecognized disassembler option: %s"), option);
+ return;
+ }
+ if (equal == option
+ || *(equal + 1) == '\0')
+ {
+ /* Invalid options with '=', no option name before '=',
+ and no value after '='. */
+ opcodes_error_handler (_("unrecognized disassembler option with '=': %s"),
+ option);
+ return;
+ }
+
+ *equal = '\0';
+ value = equal + 1;
+ if (strcmp (option, "priv-spec") == 0)
+ {
+ if (!riscv_get_priv_spec_class (value, &default_priv_spec))
+ opcodes_error_handler (_("unknown privilege spec set by %s=%s"),
+ option, value);
+ }
+ else
+ {
+ /* xgettext:c-format */
+ opcodes_error_handler (_("unrecognized disassembler option: %s"), option);
}
}
@@ -101,7 +141,7 @@ maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset)
{
if (pd->hi_addr[base_reg] != (bfd_vma)-1)
{
- pd->print_addr = pd->hi_addr[base_reg] + offset;
+ pd->print_addr = (base_reg != 0 ? pd->hi_addr[base_reg] : 0) + offset;
pd->hi_addr[base_reg] = -1;
}
else if (base_reg == X_GP && pd->gp != (bfd_vma)-1)
@@ -153,6 +193,7 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
case 'i':
print (info->stream, "%d", (int)EXTRACT_RVC_SIMM3 (l));
break;
+ case 'o':
case 'j':
print (info->stream, "%d", (int)EXTRACT_RVC_IMM (l));
break;
@@ -225,6 +266,8 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
case 'b':
case 's':
+ if ((l & MASK_JALR) == MATCH_JALR)
+ maybe_print_address (pd, rs1, 0);
print (info->stream, "%s", riscv_gpr_names[rs1]);
break;
@@ -319,16 +362,32 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
case 'E':
{
- const char* csr_name = NULL;
+ static const char *riscv_csr_hash[4096]; /* Total 2^12 CSR. */
+ static bfd_boolean init_csr = FALSE;
unsigned int csr = EXTRACT_OPERAND (CSR, l);
- switch (csr)
+
+ if (!init_csr)
{
-#define DECLARE_CSR(name, num) case num: csr_name = #name; break;
+ unsigned int i;
+ for (i = 0; i < 4096; i++)
+ riscv_csr_hash[i] = NULL;
+
+ /* Set to the newest privilege version. */
+ if (default_priv_spec == PRIV_SPEC_CLASS_NONE)
+ default_priv_spec = PRIV_SPEC_CLASS_DRAFT - 1;
+
+#define DECLARE_CSR(name, num, class, define_version, abort_version) \
+ if (default_priv_spec >= define_version \
+ && default_priv_spec < abort_version) \
+ riscv_csr_hash[num] = #name;
+#define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \
+ DECLARE_CSR (name, num, class, define_version, abort_version)
#include "opcode/riscv-opc.h"
#undef DECLARE_CSR
}
- if (csr_name)
- print (info->stream, "%s", csr_name);
+
+ if (riscv_csr_hash[csr] != NULL)
+ print (info->stream, "%s", riscv_csr_hash[csr]);
else
print (info->stream, "0x%x", csr);
break;
@@ -384,7 +443,7 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
pd->hi_addr[i] = -1;
for (i = 0; i < info->symtab_size; i++)
- if (strcmp (bfd_asymbol_name (info->symtab[i]), "_gp") == 0)
+ if (strcmp (bfd_asymbol_name (info->symtab[i]), RISCV_GP_SYMBOL) == 0)
pd->gp = bfd_asymbol_value (info->symtab[i]);
}
else
@@ -392,9 +451,13 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
insnlen = riscv_insn_length (word);
+ /* RISC-V instructions are always little-endian. */
+ info->endian_code = BFD_ENDIAN_LITTLE;
+
info->bytes_per_chunk = insnlen % 4 == 0 ? 4 : 2;
info->bytes_per_line = 8;
- info->display_endian = info->endian;
+ /* We don't support constant pools, so this must be code. */
+ info->display_endian = info->endian_code;
info->insn_info_valid = 1;
info->branch_delay_insns = 0;
info->data_size = 0;
@@ -405,7 +468,7 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
op = riscv_hash[OP_HASH_IDX (word)];
if (op != NULL)
{
- int xlen = 0;
+ unsigned xlen = 0;
/* If XLEN is not known, get its value from the ELF class. */
if (info->mach == bfd_mach_riscv64)
@@ -427,7 +490,7 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
if (no_aliases && (op->pinfo & INSN_ALIAS))
continue;
/* Is this instruction restricted to a certain value of XLEN? */
- if (isdigit (op->subset[0]) && atoi (op->subset) != xlen)
+ if ((op->xlen_requirement != 0) && (op->xlen_requirement != xlen))
continue;
/* It's a match. */
@@ -443,6 +506,32 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
pd->print_addr = -1;
}
+ /* Finish filling out insn_info fields. */
+ switch (op->pinfo & INSN_TYPE)
+ {
+ case INSN_BRANCH:
+ info->insn_type = dis_branch;
+ break;
+ case INSN_CONDBRANCH:
+ info->insn_type = dis_condbranch;
+ break;
+ case INSN_JSR:
+ info->insn_type = dis_jsr;
+ break;
+ case INSN_DREF:
+ info->insn_type = dis_dref;
+ break;
+ default:
+ break;
+ }
+
+ if (op->pinfo & INSN_DATA_SIZE)
+ {
+ int size = ((op->pinfo & INSN_DATA_SIZE)
+ >> INSN_DATA_SIZE_SHIFT);
+ info->data_size = 1 << (size - 1);
+ }
+
return insnlen;
}
}
@@ -489,6 +578,23 @@ print_insn_riscv (bfd_vma memaddr, struct disassemble_info *info)
return riscv_disassemble_insn (memaddr, insn, info);
}
+/* Prevent use of the fake labels that are generated as part of the DWARF
+ and for relaxable relocations in the assembler. */
+
+bfd_boolean
+riscv_symbol_is_valid (asymbol * sym,
+ struct disassemble_info * info ATTRIBUTE_UNUSED)
+{
+ const char * name;
+
+ if (sym == NULL)
+ return FALSE;
+
+ name = bfd_asymbol_name (sym);
+
+ return (strcmp (name, RISCV_FAKE_LABEL_NAME) != 0);
+}
+
void
print_riscv_disassembler_options (FILE *stream)
{
@@ -497,11 +603,15 @@ The following RISC-V-specific disassembler options are supported for use\n\
with the -M switch (multiple options should be separated by commas):\n"));
fprintf (stream, _("\n\
- numeric Print numeric reigster names, rather than ABI names.\n"));
+ numeric Print numeric register names, rather than ABI names.\n"));
+
+ fprintf (stream, _("\n\
+ no-aliases Disassemble only into canonical instructions, rather\n\
+ than into pseudoinstructions.\n"));
fprintf (stream, _("\n\
- no-aliases Disassemble only into canonical instructions, rather\n\
- than into pseudoinstructions.\n"));
+ priv-spec=PRIV Print the CSR according to the chosen privilege spec\n\
+ (1.9, 1.9.1, 1.10, 1.11).\n"));
fprintf (stream, _("\n"));
}