X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Fs390-opc.c;h=a99eeb242a752446fb64d01d9acd142bbf9b2fa8;hb=173373c6f6388171d1d62a217fae90a052395be2;hp=8b544cfd5efbc9fafab499af0b4ee52697497890;hpb=5e4b319cdce89a35764b749bf7ea33e7dfbddf0e;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c index 8b544cfd5e..a99eeb242a 100644 --- a/opcodes/s390-opc.c +++ b/opcodes/s390-opc.c @@ -1,6 +1,5 @@ /* s390-opc.c -- S390 opcode list - Copyright 2000, 2001, 2003, 2005, 2007, 2008, 2009 - Free Software Foundation, Inc. + Copyright (C) 2000-2014 Free Software Foundation, Inc. Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). This file is part of the GNU opcodes library. @@ -67,19 +66,19 @@ const struct s390_operand s390_operands[] = /* General purpose register pair operands. */ #define RE_8 10 /* GPR starting at position 8 */ - { 4, 8, S390_OPERAND_GPR | S390_OPERAND_REG_EVEN }, + { 4, 8, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, #define RE_12 11 /* GPR starting at position 12 */ - { 4, 12, S390_OPERAND_GPR | S390_OPERAND_REG_EVEN }, + { 4, 12, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, #define RE_16 12 /* GPR starting at position 16 */ - { 4, 16, S390_OPERAND_GPR | S390_OPERAND_REG_EVEN }, + { 4, 16, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, #define RE_20 13 /* GPR starting at position 20 */ - { 4, 20, S390_OPERAND_GPR | S390_OPERAND_REG_EVEN }, + { 4, 20, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, #define RE_24 14 /* GPR starting at position 24 */ - { 4, 24, S390_OPERAND_GPR | S390_OPERAND_REG_EVEN }, + { 4, 24, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, #define RE_28 15 /* GPR starting at position 28 */ - { 4, 28, S390_OPERAND_GPR | S390_OPERAND_REG_EVEN }, + { 4, 28, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, #define RE_32 16 /* GPR starting at position 32 */ - { 4, 32, S390_OPERAND_GPR | S390_OPERAND_REG_EVEN }, + { 4, 32, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, /* Floating point register operands. */ @@ -102,19 +101,19 @@ const struct s390_operand s390_operands[] = /* Floating point register pair operands. */ #define FE_8 24 /* FPR starting at position 8 */ - { 4, 8, S390_OPERAND_FPR | S390_OPERAND_REG_EVEN }, + { 4, 8, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, #define FE_12 25 /* FPR starting at position 12 */ - { 4, 12, S390_OPERAND_FPR | S390_OPERAND_REG_EVEN }, + { 4, 12, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, #define FE_16 26 /* FPR starting at position 16 */ - { 4, 16, S390_OPERAND_FPR | S390_OPERAND_REG_EVEN }, + { 4, 16, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, #define FE_20 27 /* FPR starting at position 16 */ - { 4, 16, S390_OPERAND_FPR | S390_OPERAND_REG_EVEN }, + { 4, 16, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, #define FE_24 28 /* FPR starting at position 24 */ - { 4, 24, S390_OPERAND_FPR | S390_OPERAND_REG_EVEN }, + { 4, 24, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, #define FE_28 29 /* FPR starting at position 28 */ - { 4, 28, S390_OPERAND_FPR | S390_OPERAND_REG_EVEN }, + { 4, 28, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, #define FE_32 30 /* FPR starting at position 32 */ - { 4, 32, S390_OPERAND_FPR | S390_OPERAND_REG_EVEN }, + { 4, 32, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, /* Access register operands. */ @@ -171,51 +170,70 @@ const struct s390_operand s390_operands[] = { 8, 8, S390_OPERAND_SIGNED }, #define I8_32 48 /* 8 bit signed value starting at 32 */ { 8, 32, S390_OPERAND_SIGNED }, -#define I16_16 49 /* 16 bit signed value starting at 16 */ +#define I12_12 49 /* 12 bit signed value starting at 12 */ + { 12, 12, S390_OPERAND_SIGNED }, +#define I16_16 50 /* 16 bit signed value starting at 16 */ { 16, 16, S390_OPERAND_SIGNED }, -#define I16_32 50 /* 16 bit signed value starting at 32 */ +#define I16_32 51 /* 16 bit signed value starting at 32 */ { 16, 32, S390_OPERAND_SIGNED }, -#define I32_16 51 /* 32 bit signed value starting at 16 */ +#define I24_24 52 /* 24 bit signed value starting at 24 */ + { 24, 24, S390_OPERAND_SIGNED }, +#define I32_16 53 /* 32 bit signed value starting at 16 */ { 32, 16, S390_OPERAND_SIGNED }, /* Unsigned immediate operands. */ -#define U4_8 52 /* 4 bit unsigned value starting at 8 */ +#define U4_8 54 /* 4 bit unsigned value starting at 8 */ { 4, 8, 0 }, -#define U4_12 53 /* 4 bit unsigned value starting at 12 */ +#define U4_12 55 /* 4 bit unsigned value starting at 12 */ { 4, 12, 0 }, -#define U4_16 54 /* 4 bit unsigned value starting at 16 */ +#define U4_16 56 /* 4 bit unsigned value starting at 16 */ { 4, 16, 0 }, -#define U4_20 55 /* 4 bit unsigned value starting at 20 */ +#define U4_20 57 /* 4 bit unsigned value starting at 20 */ { 4, 20, 0 }, -#define U4_32 56 /* 4 bit unsigned value starting at 32 */ +#define U4_24 58 /* 4 bit unsigned value starting at 24 */ + { 4, 24, 0 }, +#define U4_28 59 /* 4 bit unsigned value starting at 28 */ + { 4, 28, 0 }, +#define U4_32 60 /* 4 bit unsigned value starting at 32 */ { 4, 32, 0 }, -#define U8_8 57 /* 8 bit unsigned value starting at 8 */ +#define U4_36 61 /* 4 bit unsigned value starting at 36 */ + { 4, 36, 0 }, +#define U8_8 62 /* 8 bit unsigned value starting at 8 */ { 8, 8, 0 }, -#define U8_16 58 /* 8 bit unsigned value starting at 16 */ +#define U8_16 63 /* 8 bit unsigned value starting at 16 */ { 8, 16, 0 }, -#define U8_24 59 /* 8 bit unsigned value starting at 24 */ +#define U8_24 64 /* 8 bit unsigned value starting at 24 */ { 8, 24, 0 }, -#define U8_32 60 /* 8 bit unsigned value starting at 32 */ +#define U8_32 65 /* 8 bit unsigned value starting at 32 */ { 8, 32, 0 }, -#define U16_16 61 /* 16 bit unsigned value starting at 16 */ +#define U16_16 66 /* 16 bit unsigned value starting at 16 */ { 16, 16, 0 }, -#define U16_32 62 /* 16 bit unsigned value starting at 32 */ +#define U16_32 67 /* 16 bit unsigned value starting at 32 */ { 16, 32, 0 }, -#define U32_16 63 /* 32 bit unsigned value starting at 16 */ +#define U32_16 68 /* 32 bit unsigned value starting at 16 */ { 32, 16, 0 }, /* PC-relative address operands. */ -#define J16_16 64 /* PC relative jump offset at 16 */ +#define J12_12 69 /* 12 bit PC relative offset at 12 */ + { 12, 12, S390_OPERAND_PCREL }, +#define J16_16 70 /* 16 bit PC relative offset at 16 */ { 16, 16, S390_OPERAND_PCREL }, -#define J32_16 65 /* PC relative long offset at 16 */ +#define J16_32 71 /* 16 bit PC relative offset at 32 */ + { 16, 32, S390_OPERAND_PCREL }, +#define J24_24 72 /* 24 bit PC relative offset at 24 */ + { 24, 24, S390_OPERAND_PCREL }, +#define J32_16 73 /* 32 bit PC relative offset at 16 */ { 32, 16, S390_OPERAND_PCREL }, + /* Conditional mask operands. */ -#define M_16OPT 66 /* 4 bit optional mask starting at 16 */ +#define M_16OPT 74 /* 4 bit optional mask starting at 16 */ { 4, 16, S390_OPERAND_OPTIONAL }, +#define M_20OPT 75 /* 4 bit optional mask starting at 20 */ + { 4, 20, S390_OPERAND_OPTIONAL }, }; @@ -240,13 +258,13 @@ const struct s390_operand s390_operands[] = c - control register d - displacement, 12 bit f - floating pointer register - fe - even numbered floating point register operand + fe - fpr extended operand, a valid floating pointer register pair i - signed integer, 4, 8, 16 or 32 bit l - length, 4 or 8 bit p - pc relative r - general purpose register ro - optional register operand - re - even numbered register operand + re - gpr extended operand, a valid general purpose register pair u - unsigned integer, 4, 8, 16 or 32 bit m - mode field, 4 bit 0 - operand skipped. @@ -267,6 +285,8 @@ const struct s390_operand s390_operands[] = The instruction format is: INSTR_SS_LLRDRD / MASK_SS_LLRDRD. */ #define INSTR_E 2, { 0,0,0,0,0,0 } /* e.g. pr */ +#define INSTR_IE_UU 4, { U4_24,U4_28,0,0,0,0 } /* e.g. niai */ +#define INSTR_MII_UPP 6, { U4_8,J12_12,J24_24 } /* e.g. bprp */ #define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */ #define INSTR_RIE_RRPU 6, { R_8,R_12,U4_32,J16_16,0,0 } /* e.g. crj */ #define INSTR_RIE_RRP0 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. crjne */ @@ -326,8 +346,10 @@ const struct s390_operand s390_operands[] = #define INSTR_RRF_FUFF2 4, { F_24,F_28,F_16,U4_20,0,0 } /* e.g. adtra */ #define INSTR_RRF_FEUFEFE2 4, { FE_24,FE_28,FE_16,U4_20,0,0 } /* e.g. axtra */ #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */ +#define INSTR_RRF_RURR2 4, { R_24,R_16,R_28,U4_20,0,0 } /* e.g. lptea */ #define INSTR_RRF_R0RR 4, { R_24,R_16,R_28,0,0,0 } /* e.g. idte */ #define INSTR_RRF_R0RR2 4, { R_24,R_28,R_16,0,0,0 } /* e.g. ark */ +#define INSTR_RRF_RMRR 4, { R_24,R_16,R_28,M_20OPT,0,0 } /* e.g. crdte */ #define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fixr */ #define INSTR_RRF_U0FEFE 4, { FE_24,U4_16,FE_28,0,0,0 } /* e.g. fixbr */ #define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */ @@ -336,7 +358,7 @@ const struct s390_operand s390_operands[] = #define INSTR_RRF_UUFFE 4, { F_24,U4_16,FE_28,U4_20,0,0 } /* e.g. ldxtr */ #define INSTR_RRF_UUFEFE 4, { FE_24,U4_16,FE_28,U4_20,0,0 } /* e.g. fixtr */ #define INSTR_RRF_0UFF 4, { F_24,F_28,U4_20,0,0,0 } /* e.g. ldetr */ -#define INSTR_RRF_0UFEF 4, { F_24,FE_28,U4_20,0,0,0 } /* e.g. lxdtr */ +#define INSTR_RRF_0UFEF 4, { FE_24,F_28,U4_20,0,0,0 } /* e.g. lxdtr */ #define INSTR_RRF_FFRU 4, { F_24,F_16,R_28,U4_20,0,0 } /* e.g. rrdtr */ #define INSTR_RRF_FEFERU 4, { FE_24,FE_16,R_28,U4_20,0,0 } /* e.g. rrxtr */ #define INSTR_RRF_M0RR 4, { R_24,R_28,M_16OPT,0,0,0 } /* e.g. sske */ @@ -368,14 +390,16 @@ const struct s390_operand s390_operands[] = #define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lmh */ #define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */ #define INSTR_RSL_R0RD 6, { D_20,L4_8,B_16,0,0,0 } /* e.g. tp */ +#define INSTR_RSL_LRDFU 6, { F_32,D_20,L8_8,B_16,U4_36,0 } /* e.g. cdzt */ +#define INSTR_RSL_LRDFEU 6, { FE_32,D_20,L8_8,B_16,U4_36,0 } /* e.g. cxzt */ #define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */ #define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */ #define INSTR_RSY_RERERD 6, { RE_8,RE_12,D20_20,B_16,0,0 } /* e.g. cdsy */ #define INSTR_RSY_RURD 6, { R_8,U4_12,D20_20,B_16,0,0 } /* e.g. icmh */ +#define INSTR_RSY_RURD2 6, { R_8,D20_20,B_16,U4_12,0,0 } /* e.g. loc */ +#define INSTR_RSY_R0RD 6, { R_8,D20_20,B_16,0,0,0 } /* e.g. locgt */ #define INSTR_RSY_AARD 6, { A_8,A_12,D20_20,B_16,0,0 } /* e.g. lamy */ -#define INSTR_RSY_CCRD 6, { C_8,C_12,D20_20,B_16,0,0 } /* e.g. lamy */ -#define INSTR_RSY_RDRM 6, { R_8,D20_20,B_16,U4_12,0,0 } /* e.g. loc */ -#define INSTR_RSY_RDR0 6, { R_8,D20_20,B_16,0,0,0 } /* e.g. loc */ +#define INSTR_RSY_CCRD 6, { C_8,C_12,D20_20,B_16,0,0 } /* e.g. stctg */ #define INSTR_RS_AARD 4, { A_8,A_12,D_20,B_16,0,0 } /* e.g. lam */ #define INSTR_RS_CCRD 4, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lctl */ #define INSTR_RS_R0RD 4, { R_8,D_20,B_16,0,0,0 } /* e.g. sll */ @@ -407,6 +431,7 @@ const struct s390_operand s390_operands[] = #define INSTR_SIY_IRD 6, { D20_20,B_16,I8_8,0,0,0 } /* e.g. asi */ #define INSTR_SIL_RDI 6, { D_20,B_16,I16_32,0,0,0 } /* e.g. chhsi */ #define INSTR_SIL_RDU 6, { D_20,B_16,U16_32,0,0,0 } /* e.g. clfhsi */ +#define INSTR_SMI_U0RDP 6, { U4_8,J16_32,D_20,B_16,0,0 } /* e.g. bpp */ #define INSTR_SSE_RDRD 6, { D_20,B_16,D_36,B_32,0,0 } /* e.g. mvsdk */ #define INSTR_SS_L0RDRD 6, { D_20,L8_8,B_16,D_36,B_32,0 } /* e.g. mvc */ #define INSTR_SS_L2RDRD 6, { D_20,B_16,D_36,L8_8,B_32,0 } /* e.g. pka */ @@ -422,6 +447,8 @@ const struct s390_operand s390_operands[] = #define INSTR_S_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. lpsw */ #define MASK_E { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_IE_UU { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_MII_UPP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_RIE_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_RIE_RRPU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_RIE_RRP0 { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } @@ -479,8 +506,10 @@ const struct s390_operand s390_operands[] = #define MASK_RRF_FUFF2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_RRF_FEUFEFE2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_RRF_RURR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_RURR2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_RRF_R0RR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_RRF_R0RR2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_RMRR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_RRF_U0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } #define MASK_RRF_U0FEFE { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } #define MASK_RRF_U0RF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } @@ -521,6 +550,8 @@ const struct s390_operand s390_operands[] = #define MASK_RSE_CCRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } #define MASK_RSE_RURD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } #define MASK_RSL_R0RD { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff } +#define MASK_RSL_LRDFU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RSL_LRDFEU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_RSI_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_RS_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_RS_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } @@ -532,10 +563,10 @@ const struct s390_operand s390_operands[] = #define MASK_RSY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_RSY_RERERD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_RSY_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RSY_RURD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RSY_R0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } #define MASK_RSY_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_RSY_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -#define MASK_RSY_RDRM { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } -#define MASK_RSY_RDR0 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } #define MASK_RXE_FRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } #define MASK_RXE_FERRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } #define MASK_RXE_RRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } @@ -560,6 +591,7 @@ const struct s390_operand s390_operands[] = #define MASK_SIY_IRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_SIL_RDI { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_SIL_RDU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SMI_U0RDP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } #define MASK_SSE_RDRD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_SS_L0RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_SS_L2RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }