X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Fsh-opc.h;h=d64f50ce1b764783de15c25b9e910599d62d43c8;hb=06fe285fd293e999481ec8f5c619658aa5e3b48b;hp=ee235bd5328d2dad23d73e41daa4998fce3605aa;hpb=b90efa5b79ac1524ec260f8eb89d1be37e0219a7;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/sh-opc.h b/opcodes/sh-opc.h index ee235bd532..d64f50ce1b 100644 --- a/opcodes/sh-opc.h +++ b/opcodes/sh-opc.h @@ -1,5 +1,5 @@ /* Definitions for SH opcodes. - Copyright (C) 1993-2015 Free Software Foundation, Inc. + Copyright (C) 1993-2016 Free Software Foundation, Inc. This file is part of the GNU opcodes library. @@ -20,6 +20,10 @@ #include "bfd.h" +#ifdef __cplusplus +extern "C" { +#endif + typedef enum { HEX_0, @@ -201,10 +205,10 @@ typedef enum sh_dsp_reg_nums; /* Return a mask with bits LO to HI (inclusive) set. */ -#define MASK(LO,HI) ( LO < 1 ? ((1 << (HI + 1)) - 1) \ - : HI > 30 ? (-1 << LO) \ - : LO == HI ? (1 << LO) \ - : (((1 << (HI + 1)) - 1) & (-1 << LO))) +#define MASK(LO,HI) ( LO < 1 ? ((1U << (HI + 1)) - 1) \ + : HI > 30 ? (-1U << LO) \ + : LO == HI ? (1U << LO) \ + : (((1U << (HI + 1)) - 1) & (-1U << LO))) #define arch_sh1_base (1 << 0) #define arch_sh2_base (1 << 1) @@ -230,7 +234,7 @@ sh_dsp_reg_nums; #define arch_sh_no_co (1 << 28) /* Neither FPU nor DSP co-processor. */ #define arch_sh_sp_fpu (1 << 29) /* Single precision FPU. */ #define arch_sh_dp_fpu (1 << 30) /* Double precision FPU. */ -#define arch_sh_has_dsp (1 << 31) +#define arch_sh_has_dsp (1u << 31) #define arch_sh_co_mask MASK (28, 31) @@ -281,11 +285,10 @@ sh_dsp_reg_nums; unsigned int sh_get_arch_from_bfd_mach (unsigned long mach); unsigned int sh_get_arch_up_from_bfd_mach (unsigned long mach); unsigned long sh_get_bfd_mach_from_arch_set (unsigned int arch_set); -bfd_boolean sh_merge_bfd_arch (bfd *ibfd, bfd *obfd); /* Below are the 'architecture sets'. They describe the following inheritance graph: - + SH1 | SH2 @@ -371,7 +374,7 @@ SH4AL-dsp SH4A typedef struct { - char *name; + const char *name; sh_arg_type arg[4]; sh_nibble_type nibbles[9]; unsigned int arch; @@ -415,7 +418,7 @@ const sh_opcode_info sh_table[] = /* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}, -/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}, +/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh3_nommu_up}, /* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}, @@ -529,7 +532,7 @@ const sh_opcode_info sh_table[] = /* 0100nnnn10111010 lds ,Y1 */{"lds",{A_REG_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up}, /* 0100nnnn01011010 lds ,FPUL */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up}, - + /* 0100nnnn01101010 lds ,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up}, /* 0100nnnn00000110 lds.l @+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}, @@ -551,7 +554,7 @@ const sh_opcode_info sh_table[] = /* 0100nnnn10110110 lds.l @+,Y1 */{"lds.l",{A_INC_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_6}, arch_sh_dsp_up}, /* 0100nnnn01010110 lds.l @+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up}, - + /* 0100nnnn01100110 lds.l @+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}, /* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}, @@ -683,7 +686,7 @@ const sh_opcode_info sh_table[] = /* 11001111i8*1.... or.b #,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}, -/* 0000nnnn10000011 pref @ */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up}, +/* 0000nnnn10000011 pref @ */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up}, /* 0000nnnn11010011 prefi @ */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up}, @@ -702,7 +705,7 @@ const sh_opcode_info sh_table[] = /* 0000000010011000 setdmx */{"setdmx",{0},{HEX_0,HEX_0,HEX_9,HEX_8}, arch_sh4al_dsp_up}, /* 0000000011001000 setdmy */{"setdmy",{0},{HEX_0,HEX_0,HEX_C,HEX_8}, arch_sh4al_dsp_up}, -/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}, +/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}, /* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}, /* 0100nnnn00010100 setrc */{"setrc",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}, @@ -804,7 +807,7 @@ const sh_opcode_info sh_table[] = /* 0000nnnn10111010 sts Y1, */{"sts",{A_Y1,A_REG_N},{HEX_0,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up}, /* 0000nnnn01011010 sts FPUL, */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up}, - + /* 0000nnnn01101010 sts FPSCR, */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up}, /* 0100nnnn00000010 sts.l MACH,@-*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}, @@ -826,7 +829,7 @@ const sh_opcode_info sh_table[] = /* 0100nnnn10110110 sts.l Y1,@- */{"sts.l",{A_Y1,A_DEC_N},{HEX_4,REG_N,HEX_B,HEX_2}, arch_sh_dsp_up}, /* 0100nnnn01010010 sts.l FPUL,@-*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up}, - + /* 0100nnnn01100010 sts.l FPSCR,@-*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up}, /* 0011nnnnmmmm1000 sub , */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}, @@ -1194,7 +1197,11 @@ const sh_opcode_info sh_table[] = /* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(,), */ {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}, -{ 0, {0}, {0}, 0 } +{ 0, {0}, {0}, 0 } }; +#ifdef __cplusplus +} +#endif + #endif