X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Fspu-opc.c;h=92ecd124dc0d84e6657dadef4c871fdc08440f6c;hb=b0bfa7b5b884f78b798ab8d34d2a50bc63f558df;hp=bd1a844d9ac6e6c504d4fc0ee5e908a03e7eda81;hpb=9b201bb5e5daa9b4f783e6ece9cbfbdbf9f1d6f4;p=deliverable%2Fbinutils-gdb.git

diff --git a/opcodes/spu-opc.c b/opcodes/spu-opc.c
index bd1a844d9a..92ecd124dc 100644
--- a/opcodes/spu-opc.c
+++ b/opcodes/spu-opc.c
@@ -1,6 +1,6 @@
 /* SPU opcode list
 
-   Copyright 2006, 2007 Free Software Foundation, Inc.
+   Copyright (C) 2006-2016 Free Software Foundation, Inc.
 
    This file is part of the GNU opcodes library.
 
@@ -26,9 +26,9 @@
 
 /*
    Example contents of spu-insn.h
-      id_tag	mode	mode	type	opcode	mnemonic	asmtype	    dependency		FPU	L/S?	branch?	instruction   
-                QUAD	WORD                                               (0,RC,RB,RA,RT)    latency  			              		
-   APUOP(M_LQD,	1,	0,	RI9,	0x1f8,	"lqd",		ASM_RI9IDX,	00012,		FXU,	1,	0)	Load Quadword d-form 
+      id_tag	mode	mode	type	opcode	mnemonic	asmtype	    dependency		FPU	L/S?	branch?	instruction
+                QUAD	WORD                                               (0,RC,RB,RA,RT)    latency
+   APUOP(M_LQD,	1,	0,	RI9,	0x1f8,	"lqd",		ASM_RI9IDX,	00012,		FXU,	1,	0)	Load Quadword d-form
  */
 
 const struct spu_opcode spu_opcodes[] = {