X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Ftic80-opc.c;h=70e38ec511f898f0b488584f2e4170fd4434c3cc;hb=365b60b058820ac395db8305aa5ab4ff5ce1a3af;hp=061b63761c4d13ac6c5d9349d98342f94c93ea87;hpb=e98fe4f7b54cbdf29aef9287bbb1bea8801dd05a;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/tic80-opc.c b/opcodes/tic80-opc.c index 061b63761c..70e38ec511 100644 --- a/opcodes/tic80-opc.c +++ b/opcodes/tic80-opc.c @@ -1,24 +1,25 @@ /* Opcode table for TI TMS320C80 (MVP). - Copyright 1996 Free Software Foundation, Inc. + Copyright 1996, 1997, 2000, 2005, 2007 Free Software Foundation, Inc. -This file is part of GDB, GAS, and the GNU binutils. + This file is part of the GNU opcodes library. -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -1, or (at your option) any later version. + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ #include -#include "ansidecl.h" +#include "sysdep.h" #include "opcode/tic80.h" /* This file holds various tables for the TMS320C80 (MVP). @@ -218,7 +219,7 @@ const int tic80_num_predefined_symbols = sizeof (tic80_predefined_symbols) / siz in CLASS, and translates it to a numeric value, which it returns. If CLASS is zero, any symbol that matches NAME is translated. If - CLASS is non-zero, then only a symbol that has class CLASS is + CLASS is non-zero, then only a symbol that has symbol_class CLASS is matched. If no translation is possible, it returns -1, a value not used by @@ -232,9 +233,9 @@ const int tic80_num_predefined_symbols = sizeof (tic80_predefined_symbols) / siz */ int -tic80_symbol_to_value (name, class) +tic80_symbol_to_value (name, symbol_class) char *name; - int class; + int symbol_class; { const struct predefined_symbol *pdsp; int low = 0; @@ -258,7 +259,7 @@ tic80_symbol_to_value (name, class) else { pdsp = &tic80_predefined_symbols[middle]; - if ((class == 0) || (class & PDS_VALUE (pdsp))) + if ((symbol_class == 0) || (symbol_class & PDS_VALUE (pdsp))) { rtnval = PDS_VALUE (pdsp); } @@ -270,13 +271,13 @@ tic80_symbol_to_value (name, class) } /* This function takes a value VAL and finds a matching predefined - symbol that is in the operand class specified by CLASS. If CLASS + symbol that is in the operand symbol_class specified by CLASS. If CLASS is zero, the first matching symbol is returned. */ const char * -tic80_value_to_symbol (val, class) +tic80_value_to_symbol (val, symbol_class) int val; - int class; + int symbol_class; { const struct predefined_symbol *pdsp; int ival; @@ -290,7 +291,7 @@ tic80_value_to_symbol (val, class) ival = PDS_VALUE (pdsp) & ~TIC80_OPERAND_MASK; if (ival == val) { - if ((class == 0) || (class & PDS_VALUE (pdsp))) + if ((symbol_class == 0) || (symbol_class & PDS_VALUE (pdsp))) { /* Found the desired match */ name = PDS_NAME (pdsp); @@ -604,11 +605,11 @@ const struct tic80_opcode tic80_opcodes[] = { /* The "br" instruction is really "bbz target,r0,31". We put it first so that this specific bit pattern will get disassembled as a br rather than bbz. */ - {"br", OP_LI(0x391), 0xFFFFF000, 0, {OFF_SL_PC} }, {"br", OP_SI(0x48), 0xFFFF8000, 0, {OFF_SS_PC} }, + {"br", OP_LI(0x391), 0xFFFFF000, 0, {OFF_SL_PC} }, {"br", OP_REG(0x390), 0xFFFFF000, 0, {REG_0} }, - {"br.a", OP_LI(0x393), 0xFFFFF000, 0, {OFF_SL_PC} }, {"br.a", OP_SI(0x49), 0xFFFF8000, 0, {OFF_SS_PC} }, + {"br.a", OP_LI(0x393), 0xFFFFF000, 0, {OFF_SL_PC} }, {"br.a", OP_REG(0x392), 0xFFFFF000, 0, {REG_0} }, /* Signed integer ADD */ @@ -652,38 +653,38 @@ const struct tic80_opcode tic80_opcodes[] = { /* Branch Bit One - nonannulled */ - {"bbo", OP_LI(0x395), MASK_LI, 0, {OFF_SL_PC, REG_22, BITNUM} }, {"bbo", OP_SI(0x4A), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} }, + {"bbo", OP_LI(0x395), MASK_LI, 0, {OFF_SL_PC, REG_22, BITNUM} }, {"bbo", OP_REG(0x394), MASK_REG, 0, {REG_0, REG_22, BITNUM} }, /* Branch Bit One - annulled */ - {"bbo.a", OP_LI(0x397), MASK_LI, 0, {OFF_SL_PC, REG_22, BITNUM} }, {"bbo.a", OP_SI(0x4B), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} }, + {"bbo.a", OP_LI(0x397), MASK_LI, 0, {OFF_SL_PC, REG_22, BITNUM} }, {"bbo.a", OP_REG(0x396), MASK_REG, 0, {REG_0, REG_22, BITNUM} }, /* Branch Bit Zero - nonannulled */ - {"bbz", OP_LI(0x391), MASK_LI, 0, {OFF_SL_PC, REG_22, BITNUM} }, {"bbz", OP_SI(0x48), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} }, + {"bbz", OP_LI(0x391), MASK_LI, 0, {OFF_SL_PC, REG_22, BITNUM} }, {"bbz", OP_REG(0x390), MASK_REG, 0, {REG_0, REG_22, BITNUM} }, /* Branch Bit Zero - annulled */ - {"bbz.a", OP_LI(0x393), MASK_LI, 0, {OFF_SL_PC, REG_22, BITNUM} }, {"bbz.a", OP_SI(0x49), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} }, + {"bbz.a", OP_LI(0x393), MASK_LI, 0, {OFF_SL_PC, REG_22, BITNUM} }, {"bbz.a", OP_REG(0x392), MASK_REG, 0, {REG_0, REG_22, BITNUM} }, /* Branch Conditional - nonannulled */ - {"bcnd", OP_LI(0x399), MASK_LI, 0, {OFF_SL_PC, REG_22, CC} }, {"bcnd", OP_SI(0x4C), MASK_SI, 0, {OFF_SS_PC, REG_22, CC} }, + {"bcnd", OP_LI(0x399), MASK_LI, 0, {OFF_SL_PC, REG_22, CC} }, {"bcnd", OP_REG(0x398), MASK_REG, 0, {REG_0, REG_22, CC} }, /* Branch Conditional - annulled */ - {"bcnd.a", OP_LI(0x39B), MASK_LI, 0, {OFF_SL_PC, REG_22, CC} }, {"bcnd.a", OP_SI(0x4D), MASK_SI, 0, {OFF_SS_PC, REG_22, CC} }, + {"bcnd.a", OP_LI(0x39B), MASK_LI, 0, {OFF_SL_PC, REG_22, CC} }, {"bcnd.a", OP_REG(0x39A), MASK_REG, 0, {REG_0, REG_22, CC} }, /* Branch Control Register */ @@ -694,14 +695,14 @@ const struct tic80_opcode tic80_opcodes[] = { /* Branch and save return - nonannulled */ - {"bsr", OP_LI(0x381), MASK_LI, 0, {OFF_SL_PC, REG_DEST} }, {"bsr", OP_SI(0x40), MASK_SI, 0, {OFF_SS_PC, REG_DEST} }, + {"bsr", OP_LI(0x381), MASK_LI, 0, {OFF_SL_PC, REG_DEST} }, {"bsr", OP_REG(0x380), MASK_REG, 0, {REG_0, REG_DEST} }, /* Branch and save return - annulled */ - {"bsr.a", OP_LI(0x383), MASK_LI, 0, {OFF_SL_PC, REG_DEST} }, {"bsr.a", OP_SI(0x41), MASK_SI, 0, {OFF_SS_PC, REG_DEST} }, + {"bsr.a", OP_LI(0x383), MASK_LI, 0, {OFF_SL_PC, REG_DEST} }, {"bsr.a", OP_REG(0x382), MASK_REG, 0, {REG_0, REG_DEST} }, /* Send command */