X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Ftic80-opc.c;h=70e38ec511f898f0b488584f2e4170fd4434c3cc;hb=a8acc5fb18af9d4b0da318218680534414325e13;hp=25a03f3e4aa4268bc63e06eeecbd9dfe03d64bf1;hpb=cceb79baa82bc668007536032f692da09ca60482;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/tic80-opc.c b/opcodes/tic80-opc.c index 25a03f3e4a..70e38ec511 100644 --- a/opcodes/tic80-opc.c +++ b/opcodes/tic80-opc.c @@ -1,24 +1,25 @@ /* Opcode table for TI TMS320C80 (MVP). - Copyright 1996 Free Software Foundation, Inc. + Copyright 1996, 1997, 2000, 2005, 2007 Free Software Foundation, Inc. -This file is part of GDB, GAS, and the GNU binutils. + This file is part of the GNU opcodes library. -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -1, or (at your option) any later version. + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ #include -#include "ansidecl.h" +#include "sysdep.h" #include "opcode/tic80.h" /* This file holds various tables for the TMS320C80 (MVP). @@ -80,6 +81,7 @@ const struct predefined_symbol tic80_predefined_symbols[] = { "EIP", TIC80_OPERAND_CR | 1 }, { "EPC", TIC80_OPERAND_CR | 0 }, { "eq.b", TIC80_OPERAND_BITNUM | 0 }, + { "eq.f", TIC80_OPERAND_BITNUM | 20 }, { "eq.h", TIC80_OPERAND_BITNUM | 10 }, { "eq.w", TIC80_OPERAND_BITNUM | 20 }, { "eq0.b", TIC80_OPERAND_CC | 2 }, @@ -92,12 +94,14 @@ const struct predefined_symbol tic80_predefined_symbols[] = { "FLTTAG", TIC80_OPERAND_CR | 0x12 }, { "FPST", TIC80_OPERAND_CR | 8 }, { "ge.b", TIC80_OPERAND_BITNUM | 5 }, + { "ge.f", TIC80_OPERAND_BITNUM | 25 }, { "ge.h", TIC80_OPERAND_BITNUM | 15 }, { "ge.w", TIC80_OPERAND_BITNUM | 25 }, { "ge0.b", TIC80_OPERAND_CC | 3 }, { "ge0.h", TIC80_OPERAND_CC | 11 }, { "ge0.w", TIC80_OPERAND_CC | 19 }, { "gt.b", TIC80_OPERAND_BITNUM | 2 }, + { "gt.f", TIC80_OPERAND_BITNUM | 22 }, { "gt.h", TIC80_OPERAND_BITNUM | 12 }, { "gt.w", TIC80_OPERAND_BITNUM | 22 }, { "gt0.b", TIC80_OPERAND_CC | 1 }, @@ -109,8 +113,10 @@ const struct predefined_symbol tic80_predefined_symbols[] = { "hs.b", TIC80_OPERAND_BITNUM | 9 }, { "hs.h", TIC80_OPERAND_BITNUM | 19 }, { "hs.w", TIC80_OPERAND_BITNUM | 29 }, + { "ib.f", TIC80_OPERAND_BITNUM | 28 }, { "IE", TIC80_OPERAND_CR | 6 }, { "ILRU", TIC80_OPERAND_CR | 0x300 }, + { "in.f", TIC80_OPERAND_BITNUM | 27 }, { "IN0P", TIC80_OPERAND_CR | 0x4000 }, { "IN1P", TIC80_OPERAND_CR | 0x4001 }, { "INTPEN", TIC80_OPERAND_CR | 4 }, @@ -131,6 +137,7 @@ const struct predefined_symbol tic80_predefined_symbols[] = { "ITAG8", TIC80_OPERAND_CR | 0x208 }, { "ITAG9", TIC80_OPERAND_CR | 0x209 }, { "le.b", TIC80_OPERAND_BITNUM | 3 }, + { "le.f", TIC80_OPERAND_BITNUM | 23 }, { "le.h", TIC80_OPERAND_BITNUM | 13 }, { "le.w", TIC80_OPERAND_BITNUM | 23 }, { "le0.b", TIC80_OPERAND_CC | 6 }, @@ -143,6 +150,7 @@ const struct predefined_symbol tic80_predefined_symbols[] = { "ls.h", TIC80_OPERAND_BITNUM | 17 }, { "ls.w", TIC80_OPERAND_BITNUM | 27 }, { "lt.b", TIC80_OPERAND_BITNUM | 4 }, + { "lt.f", TIC80_OPERAND_BITNUM | 24 }, { "lt.h", TIC80_OPERAND_BITNUM | 14 }, { "lt.w", TIC80_OPERAND_BITNUM | 24 }, { "lt0.b", TIC80_OPERAND_CC | 4 }, @@ -151,6 +159,7 @@ const struct predefined_symbol tic80_predefined_symbols[] = { "MIP", TIC80_OPERAND_CR | 0x31 }, { "MPC", TIC80_OPERAND_CR | 0x30 }, { "ne.b", TIC80_OPERAND_BITNUM | 1 }, + { "ne.f", TIC80_OPERAND_BITNUM | 21 }, { "ne.h", TIC80_OPERAND_BITNUM | 11 }, { "ne.w", TIC80_OPERAND_BITNUM | 21 }, { "ne0.b", TIC80_OPERAND_CC | 5 }, @@ -159,6 +168,9 @@ const struct predefined_symbol tic80_predefined_symbols[] = { "nev.b", TIC80_OPERAND_CC | 0 }, { "nev.h", TIC80_OPERAND_CC | 8 }, { "nev.w", TIC80_OPERAND_CC | 16 }, + { "ob.f", TIC80_OPERAND_BITNUM | 29 }, + { "or.f", TIC80_OPERAND_BITNUM | 31 }, + { "ou.f", TIC80_OPERAND_BITNUM | 26 }, { "OUTP", TIC80_OPERAND_CR | 0x4002 }, { "PKTREQ", TIC80_OPERAND_CR | 0xD }, { "PPERROR", TIC80_OPERAND_CR | 0xA }, @@ -180,7 +192,7 @@ const struct predefined_symbol tic80_predefined_symbols[] = { "r22", TIC80_OPERAND_GPR | 22 }, { "r23", TIC80_OPERAND_GPR | 23 }, { "r24", TIC80_OPERAND_GPR | 24 }, - { "r24", TIC80_OPERAND_GPR | 24 }, + { "r25", TIC80_OPERAND_GPR | 25 }, { "r26", TIC80_OPERAND_GPR | 26 }, { "r27", TIC80_OPERAND_GPR | 27 }, { "r28", TIC80_OPERAND_GPR | 28 }, @@ -198,20 +210,34 @@ const struct predefined_symbol tic80_predefined_symbols[] = { "SYSTMP", TIC80_OPERAND_CR | 0x21 }, { "TCOUNT", TIC80_OPERAND_CR | 0xE }, { "TSCALE", TIC80_OPERAND_CR | 0xF }, + { "uo.f", TIC80_OPERAND_BITNUM | 30 }, }; const int tic80_num_predefined_symbols = sizeof (tic80_predefined_symbols) / sizeof (struct predefined_symbol); -/* This function takes a predefined symbol name in NAME and translates - it to a numeric value, which it returns. If no translation is - possible, it returns -1, a value not used by any predefined - symbol. Note that the predefined symbol array is presorted case - independently by name. */ +/* This function takes a predefined symbol name in NAME, symbol class + in CLASS, and translates it to a numeric value, which it returns. + + If CLASS is zero, any symbol that matches NAME is translated. If + CLASS is non-zero, then only a symbol that has symbol_class CLASS is + matched. + + If no translation is possible, it returns -1, a value not used by + any predefined symbol. Note that the predefined symbol array is + presorted case independently by name. + + This function is implemented with the assumption that there are no + duplicate names in the predefined symbol array, which happens to be + true at the moment. + + */ int -tic80_symbol_to_value (name) +tic80_symbol_to_value (name, symbol_class) char *name; + int symbol_class; { + const struct predefined_symbol *pdsp; int low = 0; int middle; int high = tic80_num_predefined_symbols - 1; @@ -232,7 +258,12 @@ tic80_symbol_to_value (name) } else { - rtnval = tic80_predefined_symbols[middle].value; + pdsp = &tic80_predefined_symbols[middle]; + if ((symbol_class == 0) || (symbol_class & PDS_VALUE (pdsp))) + { + rtnval = PDS_VALUE (pdsp); + } + /* For now we assume that there are no duplicate names */ break; } } @@ -240,13 +271,13 @@ tic80_symbol_to_value (name) } /* This function takes a value VAL and finds a matching predefined - symbol that is in the operand class specified by CLASS. If CLASS + symbol that is in the operand symbol_class specified by CLASS. If CLASS is zero, the first matching symbol is returned. */ const char * -tic80_value_to_symbol (val, class) +tic80_value_to_symbol (val, symbol_class) int val; - int class; + int symbol_class; { const struct predefined_symbol *pdsp; int ival; @@ -257,13 +288,13 @@ tic80_value_to_symbol (val, class) pdsp < tic80_predefined_symbols + tic80_num_predefined_symbols; pdsp++) { - ival = pdsp -> value & ~TIC80_OPERAND_MASK; + ival = PDS_VALUE (pdsp) & ~TIC80_OPERAND_MASK; if (ival == val) { - if ((class == 0) || (class & pdsp -> value)) + if ((symbol_class == 0) || (symbol_class & PDS_VALUE (pdsp))) { /* Found the desired match */ - name = pdsp -> name; + name = PDS_NAME (pdsp); break; } } @@ -271,6 +302,34 @@ tic80_value_to_symbol (val, class) return (name); } +/* This function returns a pointer to the next symbol in the predefined + symbol table after PDSP, or NULL if PDSP points to the last symbol. If + PDSP is NULL, it returns the first symbol in the table. Thus it can be + used to walk through the table by first calling it with NULL and then + calling it with each value it returned on the previous call, until it + returns NULL. */ + +const struct predefined_symbol * +tic80_next_predefined_symbol (pdsp) + const struct predefined_symbol *pdsp; +{ + if (pdsp == NULL) + { + pdsp = tic80_predefined_symbols; + } + else if (pdsp >= tic80_predefined_symbols && + pdsp < tic80_predefined_symbols + tic80_num_predefined_symbols - 1) + { + pdsp++; + } + else + { + pdsp = NULL; + } + return (pdsp); +} + + /* The operands table. The fields are: @@ -353,7 +412,7 @@ const struct tic80_operand tic80_operands[] = /* Even register in bits 31-27 */ #define REG_DEST_E (REG_DEST + 1) - { 5, 27, NULL, NULL, TIC80_OPERAND_GPR + TIC80_OPERAND_EVEN }, + { 5, 27, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_EVEN }, /* Floating point accumulator register (a0-a3) specified by bit 16 (MSB) and bit 11 (LSB) */ @@ -371,7 +430,7 @@ const struct tic80_operand tic80_operands[] = /* Long signed PC word offset in following 32 bit word */ #define OFF_SL_PC (OFF_SS_PC + 1) - {32, 0, NULL, NULL, TIC80_OPERAND_PCREL | TIC80_OPERAND_SIGNED }, + { 32, 0, NULL, NULL, TIC80_OPERAND_PCREL | TIC80_OPERAND_SIGNED }, /* Short signed base relative byte offset in bits 14-0 */ @@ -381,11 +440,17 @@ const struct tic80_operand tic80_operands[] = /* Long signed base relative byte offset in following 32 bit word */ #define OFF_SL_BR (OFF_SS_BR + 1) - {32, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED }, + { 32, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED }, + + /* Long signed base relative byte offset in following 32 bit word + with optional ":s" modifier flag in bit 11 */ + +#define OFF_SL_BR_SCALED (OFF_SL_BR + 1) + { 32, 0, NULL, NULL, TIC80_OPERAND_BASEREL | TIC80_OPERAND_SIGNED | TIC80_OPERAND_SCALED }, /* BITNUM in bits 31-27 */ -#define BITNUM (OFF_SL_BR + 1) +#define BITNUM (OFF_SL_BR_SCALED + 1) { 5, 27, NULL, NULL, TIC80_OPERAND_BITNUM }, /* Condition code in bits 31-27 */ @@ -425,15 +490,9 @@ const struct tic80_operand tic80_operands[] = #define REG_SCALED (REG_BASE_M_LI + 1) { 5, 0, NULL, NULL, TIC80_OPERAND_GPR | TIC80_OPERAND_SCALED }, - /* Long signed immediate in following 32 bit word, with optional ":s" modifier - flag in bit 11 */ - -#define LSI_SCALED (REG_SCALED + 1) - { 32, 0, NULL, NULL, TIC80_OPERAND_SIGNED | TIC80_OPERAND_SCALED }, - /* Unsigned immediate in bits 4-0, used only for shift instructions */ -#define ROTATE (LSI_SCALED + 1) +#define ROTATE (REG_SCALED + 1) { 5, 0, NULL, NULL, 0 }, /* Unsigned immediate in bits 9-5, used only for shift instructions */ @@ -530,7 +589,10 @@ const int tic80_num_operands = sizeof (tic80_operands)/sizeof(*tic80_operands); /* The opcode table. Formatted for better readability on a wide screen. Also, all entries with the same mnemonic are sorted so that they are adjacent in the table, allowing the use of a hash table to locate the first of a sequence of opcodes that have - a particular name. */ + a particular name. The short immediate forms also come before the long immediate forms + so that the assembler will pick the "best fit" for the size of the operand, except for + the case of the PC relative forms, where the long forms come first and are the default + forms. */ const struct tic80_opcode tic80_opcodes[] = { @@ -543,158 +605,158 @@ const struct tic80_opcode tic80_opcodes[] = { /* The "br" instruction is really "bbz target,r0,31". We put it first so that this specific bit pattern will get disassembled as a br rather than bbz. */ + {"br", OP_SI(0x48), 0xFFFF8000, 0, {OFF_SS_PC} }, {"br", OP_LI(0x391), 0xFFFFF000, 0, {OFF_SL_PC} }, {"br", OP_REG(0x390), 0xFFFFF000, 0, {REG_0} }, - {"br", OP_SI(0x48), 0xFFFF8000, 0, {OFF_SS_PC} }, + {"br.a", OP_SI(0x49), 0xFFFF8000, 0, {OFF_SS_PC} }, {"br.a", OP_LI(0x393), 0xFFFFF000, 0, {OFF_SL_PC} }, {"br.a", OP_REG(0x392), 0xFFFFF000, 0, {REG_0} }, - {"br.a", OP_SI(0x49), 0xFFFF8000, 0, {OFF_SS_PC} }, /* Signed integer ADD */ + {"add", OP_SI(0x58), MASK_SI, 0, {SSI, REG_22, REG_DEST} }, {"add", OP_LI(0x3B1), MASK_LI, 0, {LSI, REG_22, REG_DEST} }, {"add", OP_REG(0x3B0), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - {"add", OP_SI(0x58), MASK_SI, 0, {SSI, REG_22, REG_DEST} }, /* Unsigned integer ADD */ + {"addu", OP_SI(0x59), MASK_SI, 0, {SSI, REG_22, REG_DEST} }, {"addu", OP_LI(0x3B3), MASK_LI, 0, {LSI, REG_22, REG_DEST} }, {"addu", OP_REG(0x3B2), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - {"addu", OP_SI(0x59), MASK_SI, 0, {SSI, REG_22, REG_DEST} }, /* Bitwise AND */ + {"and", OP_SI(0x11), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, {"and", OP_LI(0x323), MASK_LI, 0, {LUBF, REG_22, REG_DEST} }, {"and", OP_REG(0x322), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - {"and", OP_SI(0x11), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, + {"and.tt", OP_SI(0x11), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, {"and.tt", OP_LI(0x323), MASK_LI, 0, {LUBF, REG_22, REG_DEST} }, {"and.tt", OP_REG(0x322), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - {"and.tt", OP_SI(0x11), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, /* Bitwise AND with ones complement of both sources */ + {"and.ff", OP_SI(0x18), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, {"and.ff", OP_LI(0x331), MASK_LI, 0, {LUBF, REG_22, REG_DEST} }, {"and.ff", OP_REG(0x330), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - {"and.ff", OP_SI(0x18), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, /* Bitwise AND with ones complement of source 1 */ + {"and.ft", OP_SI(0x14), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, {"and.ft", OP_LI(0x329), MASK_LI, 0, {LUBF, REG_22, REG_DEST} }, {"and.ft", OP_REG(0x328), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - {"and.ft", OP_SI(0x14), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, /* Bitwise AND with ones complement of source 2 */ + {"and.tf", OP_SI(0x12), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, {"and.tf", OP_LI(0x325), MASK_LI, 0, {LUBF, REG_22, REG_DEST} }, {"and.tf", OP_REG(0x324), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - {"and.tf", OP_SI(0x12), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, /* Branch Bit One - nonannulled */ + {"bbo", OP_SI(0x4A), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} }, {"bbo", OP_LI(0x395), MASK_LI, 0, {OFF_SL_PC, REG_22, BITNUM} }, {"bbo", OP_REG(0x394), MASK_REG, 0, {REG_0, REG_22, BITNUM} }, - {"bbo", OP_SI(0x4A), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} }, /* Branch Bit One - annulled */ + {"bbo.a", OP_SI(0x4B), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} }, {"bbo.a", OP_LI(0x397), MASK_LI, 0, {OFF_SL_PC, REG_22, BITNUM} }, {"bbo.a", OP_REG(0x396), MASK_REG, 0, {REG_0, REG_22, BITNUM} }, - {"bbo.a", OP_SI(0x4B), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} }, /* Branch Bit Zero - nonannulled */ + {"bbz", OP_SI(0x48), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} }, {"bbz", OP_LI(0x391), MASK_LI, 0, {OFF_SL_PC, REG_22, BITNUM} }, {"bbz", OP_REG(0x390), MASK_REG, 0, {REG_0, REG_22, BITNUM} }, - {"bbz", OP_SI(0x48), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} }, /* Branch Bit Zero - annulled */ + {"bbz.a", OP_SI(0x49), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} }, {"bbz.a", OP_LI(0x393), MASK_LI, 0, {OFF_SL_PC, REG_22, BITNUM} }, {"bbz.a", OP_REG(0x392), MASK_REG, 0, {REG_0, REG_22, BITNUM} }, - {"bbz.a", OP_SI(0x49), MASK_SI, 0, {OFF_SS_PC, REG_22, BITNUM} }, /* Branch Conditional - nonannulled */ + {"bcnd", OP_SI(0x4C), MASK_SI, 0, {OFF_SS_PC, REG_22, CC} }, {"bcnd", OP_LI(0x399), MASK_LI, 0, {OFF_SL_PC, REG_22, CC} }, {"bcnd", OP_REG(0x398), MASK_REG, 0, {REG_0, REG_22, CC} }, - {"bcnd", OP_SI(0x4C), MASK_SI, 0, {OFF_SS_PC, REG_22, CC} }, /* Branch Conditional - annulled */ + {"bcnd.a", OP_SI(0x4D), MASK_SI, 0, {OFF_SS_PC, REG_22, CC} }, {"bcnd.a", OP_LI(0x39B), MASK_LI, 0, {OFF_SL_PC, REG_22, CC} }, {"bcnd.a", OP_REG(0x39A), MASK_REG, 0, {REG_0, REG_22, CC} }, - {"bcnd.a", OP_SI(0x4D), MASK_SI, 0, {OFF_SS_PC, REG_22, CC} }, /* Branch Control Register */ + {"brcr", OP_SI(0x6), MASK_SI, 0, {CR_SI} }, {"brcr", OP_LI(0x30D), MASK_LI, 0, {CR_LI} }, {"brcr", OP_REG(0x30C), MASK_REG, 0, {REG_0} }, - {"brcr", OP_SI(0x6), MASK_SI, 0, {CR_SI} }, /* Branch and save return - nonannulled */ + {"bsr", OP_SI(0x40), MASK_SI, 0, {OFF_SS_PC, REG_DEST} }, {"bsr", OP_LI(0x381), MASK_LI, 0, {OFF_SL_PC, REG_DEST} }, {"bsr", OP_REG(0x380), MASK_REG, 0, {REG_0, REG_DEST} }, - {"bsr", OP_SI(0x40), MASK_SI, 0, {OFF_SS_PC, REG_DEST} }, /* Branch and save return - annulled */ + {"bsr.a", OP_SI(0x41), MASK_SI, 0, {OFF_SS_PC, REG_DEST} }, {"bsr.a", OP_LI(0x383), MASK_LI, 0, {OFF_SL_PC, REG_DEST} }, {"bsr.a", OP_REG(0x382), MASK_REG, 0, {REG_0, REG_DEST} }, - {"bsr.a", OP_SI(0x41), MASK_SI, 0, {OFF_SS_PC, REG_DEST} }, /* Send command */ + {"cmnd", OP_SI(0x2), MASK_SI, 0, {SUI} }, {"cmnd", OP_LI(0x305), MASK_LI, 0, {LUI} }, {"cmnd", OP_REG(0x304), MASK_REG, 0, {REG_0} }, - {"cmnd", OP_SI(0x2), MASK_SI, 0, {SUI} }, /* Integer compare */ + {"cmp", OP_SI(0x50), MASK_SI, 0, {SSI, REG_22, REG_DEST} }, {"cmp", OP_LI(0x3A1), MASK_LI, 0, {LSI, REG_22, REG_DEST} }, {"cmp", OP_REG(0x3A0), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - {"cmp", OP_SI(0x50), MASK_SI, 0, {SSI, REG_22, REG_DEST} }, /* Flush data cache subblock - don't clear subblock preset flag */ + {"dcachec", OP_SI(0x38), F(1) | (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI} }, {"dcachec", OP_LI(0x371), F(1) | (MASK_LI & ~M_LI(1)) | S(1) | D(1), 0, {LSI, REG_BASE_M_LI} }, {"dcachec", OP_REG(0x370), F(1) | (MASK_REG & ~M_REG(1)) | S(1) | D(1), 0, {REG_0, REG_BASE_M_LI} }, - {"dcachec", OP_SI(0x38), F(1) | (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI} }, /* Flush data cache subblock - clear subblock preset flag */ + {"dcachef", OP_SI(0x38) | F(1), F(1) | (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI} }, {"dcachef", OP_LI(0x371) | F(1), F(1) | (MASK_LI & ~M_LI(1)) | S(1) | D(1), 0, {LSI, REG_BASE_M_LI} }, {"dcachef", OP_REG(0x370) | F(1), F(1) | (MASK_REG & ~M_REG(1)) | S(1) | D(1), 0, {REG_0, REG_BASE_M_LI} }, - {"dcachef", OP_SI(0x38) | F(1), F(1) | (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI} }, /* Direct load signed data into register */ - {"dld", OP_LI(0x345) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"dld", OP_REG(0x344) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"dld.b", OP_LI(0x341) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"dld.b", OP_REG(0x340) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"dld.d", OP_LI(0x347) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST_E} }, - {"dld.d", OP_REG(0x346) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} }, - {"dld.h", OP_LI(0x343) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"dld.h", OP_REG(0x342) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"dld", OP_LI(0x345) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"dld", OP_REG(0x344) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"dld.b", OP_LI(0x341) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"dld.b", OP_REG(0x340) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"dld.d", OP_LI(0x347) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST_E} }, + {"dld.d", OP_REG(0x346) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} }, + {"dld.h", OP_LI(0x343) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"dld.h", OP_REG(0x342) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, /* Direct load unsigned data into register */ - {"dld.ub", OP_LI(0x351) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"dld.ub", OP_REG(0x350) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"dld.uh", OP_LI(0x353) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"dld.uh", OP_REG(0x352) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"dld.ub", OP_LI(0x351) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"dld.ub", OP_REG(0x350) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"dld.uh", OP_LI(0x353) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"dld.uh", OP_REG(0x352) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, /* Direct store data into memory */ - {"dst", OP_LI(0x365) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"dst", OP_REG(0x364) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"dst.b", OP_LI(0x361) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"dst.b", OP_REG(0x360) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"dst.d", OP_LI(0x367) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST_E} }, - {"dst.d", OP_REG(0x366) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} }, - {"dst.h", OP_LI(0x363) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"dst.h", OP_REG(0x362) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"dst", OP_LI(0x365) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"dst", OP_REG(0x364) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"dst.b", OP_LI(0x361) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"dst.b", OP_REG(0x360) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"dst.d", OP_LI(0x367) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST_E} }, + {"dst.d", OP_REG(0x366) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} }, + {"dst.h", OP_LI(0x363) | D(1), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"dst.h", OP_REG(0x362) | D(1), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, /* Emulation stop */ @@ -702,9 +764,9 @@ const struct tic80_opcode tic80_opcodes[] = { /* Emulation trap */ + {"etrap", OP_SI(0x1) | E(1), MASK_SI | E(1), 0, {SUI} }, {"etrap", OP_LI(0x303) | E(1), MASK_LI | E(1), 0, {LUI} }, {"etrap", OP_REG(0x302) | E(1), MASK_REG | E(1), 0, {REG_0} }, - {"etrap", OP_SI(0x1) | E(1), MASK_SI | E(1), 0, {SUI} }, /* Floating-point addition */ @@ -870,36 +932,36 @@ const struct tic80_opcode tic80_opcodes[] = { /* Jump and save return */ + {"jsr", OP_SI(0x44), MASK_SI, 0, {OFF_SS_BR, REG_BASE, REG_DEST} }, {"jsr", OP_LI(0x389), MASK_LI, 0, {OFF_SL_BR, REG_BASE, REG_DEST} }, {"jsr", OP_REG(0x388), MASK_REG, 0, {REG_0, REG_BASE, REG_DEST} }, - {"jsr", OP_SI(0x44), MASK_SI, 0, {OFF_SS_BR, REG_BASE, REG_DEST} }, + {"jsr.a", OP_SI(0x45), MASK_SI, 0, {OFF_SS_BR, REG_BASE, REG_DEST} }, {"jsr.a", OP_LI(0x38B), MASK_LI, 0, {OFF_SL_BR, REG_BASE, REG_DEST} }, {"jsr.a", OP_REG(0x38A), MASK_REG, 0, {REG_0, REG_BASE, REG_DEST} }, - {"jsr.a", OP_SI(0x45), MASK_SI, 0, {OFF_SS_BR, REG_BASE, REG_DEST} }, /* Load Signed Data Into Register */ - {"ld", OP_LI(0x345) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"ld", OP_REG(0x344) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"ld", OP_SI(0x22), (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI, REG_DEST} }, - {"ld.b", OP_LI(0x341) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"ld.b", OP_REG(0x340) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"ld.b", OP_SI(0x20), (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI, REG_DEST} }, - {"ld.d", OP_LI(0x347) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST_E} }, - {"ld.d", OP_REG(0x346) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} }, - {"ld.d", OP_SI(0x23), (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI, REG_DEST_E} }, - {"ld.h", OP_LI(0x343) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"ld.h", OP_REG(0x342) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"ld.h", OP_SI(0x21), (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI, REG_DEST} }, + {"ld", OP_SI(0x22), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} }, + {"ld", OP_LI(0x345) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"ld", OP_REG(0x344) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"ld.b", OP_SI(0x20), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} }, + {"ld.b", OP_LI(0x341) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"ld.b", OP_REG(0x340) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"ld.d", OP_SI(0x23), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST_E} }, + {"ld.d", OP_LI(0x347) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST_E} }, + {"ld.d", OP_REG(0x346) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} }, + {"ld.h", OP_SI(0x21), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} }, + {"ld.h", OP_LI(0x343) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"ld.h", OP_REG(0x342) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, /* Load Unsigned Data Into Register */ - {"ld.ub", OP_LI(0x351) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"ld.ub", OP_REG(0x350) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"ld.ub", OP_SI(0x28), (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI, REG_DEST} }, - {"ld.uh", OP_LI(0x353) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"ld.uh", OP_REG(0x352) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"ld.uh", OP_SI(0x29), (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI, REG_DEST} }, + {"ld.ub", OP_SI(0x28), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} }, + {"ld.ub", OP_LI(0x351) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"ld.ub", OP_REG(0x350) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"ld.uh", OP_SI(0x29), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} }, + {"ld.uh", OP_LI(0x353) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"ld.uh", OP_REG(0x352) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, /* Leftmost one */ @@ -907,27 +969,27 @@ const struct tic80_opcode tic80_opcodes[] = { /* Bitwise logical OR. Note that "or.tt" and "or" are the same instructions. */ + {"or.ff", OP_SI(0x1E), MASK_SI, 0, {SUI, REG_22, REG_DEST} }, {"or.ff", OP_LI(0x33D), MASK_LI, 0, {LUI, REG_22, REG_DEST} }, {"or.ff", OP_REG(0x33C), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - {"or.ff", OP_SI(0x1E), MASK_SI, 0, {SUI, REG_22, REG_DEST} }, + {"or.ft", OP_SI(0x1D), MASK_SI, 0, {SUI, REG_22, REG_DEST} }, {"or.ft", OP_LI(0x33B), MASK_LI, 0, {LUI, REG_22, REG_DEST} }, {"or.ft", OP_REG(0x33A), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - {"or.ft", OP_SI(0x1D), MASK_SI, 0, {SUI, REG_22, REG_DEST} }, + {"or.tf", OP_SI(0x1B), MASK_SI, 0, {SUI, REG_22, REG_DEST} }, {"or.tf", OP_LI(0x337), MASK_LI, 0, {LUI, REG_22, REG_DEST} }, {"or.tf", OP_REG(0x336), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - {"or.tf", OP_SI(0x1B), MASK_SI, 0, {SUI, REG_22, REG_DEST} }, + {"or.tt", OP_SI(0x17), MASK_SI, 0, {SUI, REG_22, REG_DEST} }, {"or.tt", OP_LI(0x32F), MASK_LI, 0, {LUI, REG_22, REG_DEST} }, {"or.tt", OP_REG(0x32E), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - {"or.tt", OP_SI(0x17), MASK_SI, 0, {SUI, REG_22, REG_DEST} }, + {"or", OP_SI(0x17), MASK_SI, 0, {SUI, REG_22, REG_DEST} }, {"or", OP_LI(0x32F), MASK_LI, 0, {LUI, REG_22, REG_DEST} }, {"or", OP_REG(0x32E), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - {"or", OP_SI(0x17), MASK_SI, 0, {SUI, REG_22, REG_DEST} }, /* Read Control Register */ + {"rdcr", OP_SI(0x4), MASK_SI | (0x1F << 22), 0, {CR_SI, REG_DEST} }, {"rdcr", OP_LI(0x309), MASK_LI | (0x1F << 22), 0, {CR_LI, REG_DEST} }, {"rdcr", OP_REG(0x308), MASK_REG | (0x1F << 22), 0, {REG_0, REG_DEST} }, - {"rdcr", OP_SI(0x4), MASK_SI | (0x1F << 22), 0, {CR_SI, REG_DEST} }, /* Rightmost one */ @@ -1030,49 +1092,49 @@ const struct tic80_opcode tic80_opcodes[] = { /* Store Data into Memory */ - {"st", OP_LI(0x365) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"st", OP_REG(0x364) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"st", OP_SI(0x32), (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI, REG_DEST}}, - {"st.b", OP_LI(0x361) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"st.b", OP_REG(0x360) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"st.b", OP_SI(0x30), (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI, REG_DEST}}, - {"st.d", OP_LI(0x367) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST_E} }, - {"st.d", OP_REG(0x366) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} }, - {"st.d", OP_SI(0x33), (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI, REG_DEST_E}}, - {"st.h", OP_LI(0x363) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {LSI_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"st.h", OP_REG(0x362) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, - {"st.h", OP_SI(0x31), (MASK_SI & ~M_SI(1)), 0, {SSI, REG_BASE_M_SI, REG_DEST}}, + {"st", OP_SI(0x32), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} }, + {"st", OP_LI(0x365) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"st", OP_REG(0x364) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"st.b", OP_SI(0x30), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} }, + {"st.b", OP_LI(0x361) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"st.b", OP_REG(0x360) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"st.d", OP_SI(0x33), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST_E} }, + {"st.d", OP_LI(0x367) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST_E} }, + {"st.d", OP_REG(0x366) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST_E} }, + {"st.h", OP_SI(0x31), (MASK_SI & ~M_SI(1)), 0, {OFF_SS_BR, REG_BASE_M_SI, REG_DEST} }, + {"st.h", OP_LI(0x363) | D(0), (MASK_LI & ~M_REG(1)) | D(1), 0, {OFF_SL_BR_SCALED, REG_BASE_M_LI, REG_DEST} }, + {"st.h", OP_REG(0x362) | D(0), (MASK_REG & ~M_REG(1)) | D(1), 0, {REG_SCALED, REG_BASE_M_LI, REG_DEST} }, /* Signed Integer Subtract */ + {"sub", OP_SI(0x5A), MASK_SI, 0, {SSI, REG_22, REG_DEST} }, {"sub", OP_LI(0x3B5), MASK_LI, 0, {LSI, REG_22, REG_DEST} }, {"sub", OP_REG(0x3B4), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - {"sub", OP_SI(0x5A), MASK_SI, 0, {SSI, REG_22, REG_DEST} }, /* Unsigned Integer Subtract */ + {"subu", OP_SI(0x5B), MASK_SI, 0, {SSI, REG_22, REG_DEST} }, {"subu", OP_LI(0x3B7), MASK_LI, 0, {LSI, REG_22, REG_DEST} }, {"subu", OP_REG(0x3B6), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - {"subu", OP_SI(0x5B), MASK_SI, 0, {SSI, REG_22, REG_DEST} }, /* Write Control Register Is a special form of the "swcr" instruction so comes before it in the table. */ + {"wrcr", OP_SI(0x5), MASK_SI | (0x1F << 27), 0, {CR_SI, REG_22} }, {"wrcr", OP_LI(0x30B), MASK_LI | (0x1F << 27), 0, {CR_LI, REG_22} }, {"wrcr", OP_REG(0x30A), MASK_REG | (0x1F << 27), 0, {REG_0, REG_22} }, - {"wrcr", OP_SI(0x5), MASK_SI | (0x1F << 27), 0, {CR_SI, REG_22} }, /* Swap Control Register */ + {"swcr", OP_SI(0x5), MASK_SI, 0, {CR_SI, REG_22, REG_DEST} }, {"swcr", OP_LI(0x30B), MASK_LI, 0, {CR_LI, REG_22, REG_DEST} }, {"swcr", OP_REG(0x30A), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - {"swcr", OP_SI(0x5), MASK_SI, 0, {CR_SI, REG_22, REG_DEST} }, /* Trap */ + {"trap", OP_SI(0x1) | E(0), MASK_SI | E(1), 0, {SUI} }, {"trap", OP_LI(0x303) | E(0), MASK_LI | E(1), 0, {LUI} }, {"trap", OP_REG(0x302) | E(0), MASK_REG | E(1), 0, {REG_0} }, - {"trap", OP_SI(0x1) | E(0), MASK_SI | E(1), 0, {SUI} }, /* Vector Floating-Point Add */ @@ -1141,13 +1203,13 @@ const struct tic80_opcode tic80_opcodes[] = { {"vst.d", OP_V(0x1E) | V_m(0) | V_S(1) | V_p(1), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST_E} }, {"vst.s", OP_V(0x1E) | V_m(0) | V_S(0) | V_p(1), MASK_V | V_m(1) | V_S(1) | V_p(1), TIC80_VECTOR, {REG_DEST} }, + {"xnor", OP_SI(0x19), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, {"xnor", OP_LI(0x333), MASK_LI, 0, {LUBF, REG_22, REG_DEST} }, {"xnor", OP_REG(0x332), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - {"xnor", OP_SI(0x19), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, + {"xor", OP_SI(0x16), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, {"xor", OP_LI(0x32D), MASK_LI, 0, {LUBF, REG_22, REG_DEST} }, {"xor", OP_REG(0x32C), MASK_REG, 0, {REG_0, REG_22, REG_DEST} }, - {"xor", OP_SI(0x16), MASK_SI, 0, {SUBF, REG_22, REG_DEST} }, };