X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=opcodes%2Fv850-opc.c;h=874db1b6ee980ff4aadb91ddc0e266a848fd3986;hb=dc3febfa6ef6fa1bc6a9239f85db6faf6006655c;hp=5376bdc09ad601ed63fca752d85f9ae8d70be4b2;hpb=fa803dc60f0bf01297674c41d001798e18ade4dc;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/v850-opc.c b/opcodes/v850-opc.c index 5376bdc09a..874db1b6ee 100644 --- a/opcodes/v850-opc.c +++ b/opcodes/v850-opc.c @@ -15,9 +15,10 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -#include "ansidecl.h" +#include "sysdep.h" #include "opcode/v850.h" #include +#include "opintl.h" /* regular opcode */ #define OP(x) ((x & 0x3f) << 5) @@ -37,17 +38,32 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* The functions used to insert and extract complicated operands. */ +/* Note: There is a conspiracy between these functions and + v850_insert_operand() in gas/config/tc-v850.c. Error messages + containing the string 'out of range' will be ignored unless a + specific command line option is given to GAS. */ + +static const char * not_valid = N_ ("displacement value is not in range and is not aligned"); +static const char * out_of_range = N_ ("displacement value is out of range"); +static const char * not_aligned = N_ ("displacement value is not aligned"); + +static const char * immediate_out_of_range = N_ ("immediate value is out of range"); + static unsigned long insert_d9 (insn, value, errmsg) unsigned long insn; - long value; - const char **errmsg; + long value; + const char ** errmsg; { if (value > 0xff || value < -0x100) - *errmsg = "branch value out of range"; - - if ((value % 2) != 0) - *errmsg = "branch to odd offset"; + { + if ((value % 2) != 0) + * errmsg = _("branch value not in range and to odd offset"); + else + * errmsg = _("branch value out of range"); + } + else if ((value % 2) != 0) + * errmsg = _("branch to odd offset"); return (insn | ((value & 0x1f0) << 7) | ((value & 0x0e) << 3)); } @@ -55,7 +71,7 @@ insert_d9 (insn, value, errmsg) static unsigned long extract_d9 (insn, invalid) unsigned long insn; - int *invalid; + int * invalid; { unsigned long ret = ((insn & 0xf800) >> 7) | ((insn & 0x0070) >> 3); @@ -68,14 +84,18 @@ extract_d9 (insn, invalid) static unsigned long insert_d22 (insn, value, errmsg) unsigned long insn; - long value; - const char **errmsg; + long value; + const char ** errmsg; { if (value > 0x1fffff || value < -0x200000) - *errmsg = "branch value out of range"; - - if ((value % 2) != 0) - *errmsg = "branch to odd offset"; + { + if ((value % 2) != 0) + * errmsg = _("branch value not in range and to an odd offset"); + else + * errmsg = _("branch value out of range"); + } + else if ((value % 2) != 0) + * errmsg = _("branch to odd offset"); return (insn | ((value & 0xfffe) << 16) | ((value & 0x3f0000) >> 16)); } @@ -83,24 +103,28 @@ insert_d22 (insn, value, errmsg) static unsigned long extract_d22 (insn, invalid) unsigned long insn; - int *invalid; + int * invalid; { - unsigned long ret = ((insn & 0xfffe0000) >> 16) | ((insn & 0x3f) << 16); + signed long ret = ((insn & 0xfffe0000) >> 16) | ((insn & 0x3f) << 16); - return ((ret << 10) >> 10); + return (unsigned long) ((ret << 10) >> 10); } static unsigned long insert_d16_15 (insn, value, errmsg) unsigned long insn; - long value; - const char **errmsg; + long value; + const char ** errmsg; { if (value > 0x7fff || value < -0x8000) - *errmsg = "value out of range"; - - if ((value % 2) != 0) - *errmsg = "load/store half/word at odd offset"; + { + if ((value % 2) != 0) + * errmsg = _(not_valid); + else + * errmsg = _(out_of_range); + } + else if ((value % 2) != 0) + * errmsg = _(not_aligned); return insn | ((value & 0xfffe) << 16); } @@ -118,14 +142,18 @@ extract_d16_15 (insn, invalid) static unsigned long insert_d8_7 (insn, value, errmsg) unsigned long insn; - long value; - const char **errmsg; + long value; + const char ** errmsg; { if (value > 0xff || value < 0) - *errmsg = "short load/store half value out of range"; - - if ((value % 2) != 0) - *errmsg = "short load/store half at odd offset"; + { + if ((value % 2) != 0) + * errmsg = _(not_valid); + else + * errmsg = _(out_of_range); + } + else if ((value % 2) != 0) + * errmsg = _(not_aligned); value >>= 1; @@ -135,7 +163,7 @@ insert_d8_7 (insn, value, errmsg) static unsigned long extract_d8_7 (insn, invalid) unsigned long insn; - int *invalid; + int * invalid; { unsigned long ret = (insn & 0x7f); @@ -145,14 +173,18 @@ extract_d8_7 (insn, invalid) static unsigned long insert_d8_6 (insn, value, errmsg) unsigned long insn; - long value; - const char **errmsg; + long value; + const char ** errmsg; { if (value > 0xff || value < 0) - *errmsg = "short load/store word value out of range"; - - if ((value % 4) != 0) - *errmsg = "short load/store word at odd offset"; + { + if ((value % 4) != 0) + *errmsg = _(not_valid); + else + * errmsg = _(out_of_range); + } + else if ((value % 4) != 0) + * errmsg = _(not_aligned); value >>= 1; @@ -162,15 +194,13 @@ insert_d8_6 (insn, value, errmsg) static unsigned long extract_d8_6 (insn, invalid) unsigned long insn; - int *invalid; + int * invalid; { unsigned long ret = (insn & 0x7e); return ret << 1; } -/* start-sanitize-v850e */ - static unsigned long insert_d5_4 (insn, value, errmsg) unsigned long insn; @@ -178,10 +208,14 @@ insert_d5_4 (insn, value, errmsg) const char ** errmsg; { if (value > 0x1f || value < 0) - *errmsg = "unsigned short load half value out of range"; - - if (value & 1) - *errmsg = "unsigned short load half at odd offset"; + { + if (value & 1) + * errmsg = _(not_valid); + else + *errmsg = _(out_of_range); + } + else if (value & 1) + * errmsg = _(not_aligned); value >>= 1; @@ -205,7 +239,7 @@ insert_d16_16 (insn, value, errmsg) const char ** errmsg; { if (value > 0x7fff || value < -0x8000) - *errmsg = "value out of range"; + * errmsg = _(out_of_range); return (insn | ((value & 0xfffe) << 16) | ((value & 1) << 5)); } @@ -231,7 +265,7 @@ insert_i9 (insn, value, errmsg) const char ** errmsg; { if (value > 0xff || value < -0x100) - *errmsg = "value out of range"; + * errmsg = _(immediate_out_of_range); return insn | ((value & 0x1e0) << 13) | (value & 0x1f); } @@ -258,7 +292,7 @@ insert_u9 (insn, value, errmsg) const char ** errmsg; { if (value > 0x1ff) - *errmsg = "value out of range"; + * errmsg = _(immediate_out_of_range); return insn | ((value & 0x1e0) << 13) | (value & 0x1f); } @@ -284,7 +318,7 @@ insert_spe (insn, value, errmsg) const char ** errmsg; { if (value != 3) - *errmsg = "invalid register for stack adjustment"; + * errmsg = _("invalid register for stack adjustment"); return insn & (~ 0x180000); } @@ -297,9 +331,6 @@ extract_spe (insn, invalid) return 3; } -/* end-sanitize-v850e */ -/* start-sanitize-v850eq */ - static unsigned long insert_i5div (insn, value, errmsg) unsigned long insn; @@ -307,10 +338,14 @@ insert_i5div (insn, value, errmsg) const char ** errmsg; { if (value > 0x1ff) - *errmsg = "value out of range"; - - if (value & 1) - *errmsg = "value must be even"; + { + if (value & 1) + * errmsg = _("immediate value not in range and not even"); + else + * errmsg = _(immediate_out_of_range); + } + else if (value & 1) + * errmsg = _("immediate value must be even"); value = 32 - value; @@ -331,8 +366,6 @@ extract_i5div (insn, invalid) return ret; } -/* end-sanitize-v850eq */ - /* Warning: code in gas/config/tc-v850.c examines the contents of this array. If you change any of the values here, be sure to look for side effects in @@ -414,19 +447,16 @@ const struct v850_operand v850_operands[] = #define D16 (SR2 + 1) { 16, 16, NULL, NULL, V850_OPERAND_SIGNED }, -/* The DISP22 field in a format 4 insn, relaxable. */ +/* The DISP9 field in a format 3 insn, relaxable. */ #define D9_RELAX (D16 + 1) { 9, 0, insert_d9, extract_d9, V850_OPERAND_RELAX | V850_OPERAND_SIGNED | V850_OPERAND_DISP }, -/* The DISP22 field in a format 4 insn. - +/* The DISP22 field in a format 4 insn, relaxable. This _must_ follow D9_RELAX; the assembler assumes that the longer version immediately follows the shorter version for relaxing. */ #define D22 (D9_RELAX + 1) { 22, 0, insert_d22, extract_d22, V850_OPERAND_SIGNED | V850_OPERAND_DISP }, -/* start-sanitize-v850e */ - /* The signed disp4 field in a format 4 insn. */ #define D4 (D22 + 1) { 4, 0, NULL, NULL, 0}, @@ -483,9 +513,6 @@ const struct v850_operand v850_operands[] = #define SP (R2DISPOSE + 1) { 2, 19, insert_spe, extract_spe, V850_OPERAND_REG }, -/* end-sanitize-v850e */ -/* start-sanitize-v850eq */ - /* The IMM5 field in a divide N step instruction. */ #define I5DIV (SP + 1) { 9, 0, insert_i5div, extract_i5div, V850_OPERAND_SIGNED }, @@ -497,8 +524,6 @@ const struct v850_operand v850_operands[] = /* The list of registers in a PUSHML/POPML instruction. */ #define LIST18_L (LIST18_H + 1) { -1, 0xfff8001f, NULL, NULL, V850E_PUSH_POP }, /* The setting of the 4th bit is a flag to disassmble() in v850-dis.c */ - -/* end-sanitize-v850eq */ } ; @@ -531,7 +556,7 @@ const struct v850_operand v850_operands[] = which bits in the actual opcode must match OPCODE. OPERANDS is the list of operands. MEMOP specifies which operand (if any) is a memory operand. - PROCESSOR specifies which CPUs support the opcode. + PROCESSORS specifies which CPU(s) support the opcode. The disassembler reads the table in order and prints the first instruction which matches, so this table is sorted to put more @@ -556,49 +581,28 @@ const struct v850_opcode v850_opcodes[] = { "jmp", one (0x0060), one (0xffe0), {R1}, 1, PROCESSOR_ALL }, /* load/store instructions */ -/* start-sanitize-v850eq */ -{ "sld.bu", one (0x0300), one (0x0780), {D7, EP, R2_NOTR0}, 1, PROCESSOR_V850EQ }, -/* end-sanitize-v850eq */ -/* start-sanitize-v850e */ +{ "sld.bu", one (0x0300), one (0x0780), {D7, EP, R2_NOTR0}, 1, PROCESSOR_V850EA }, { "sld.bu", one (0x0060), one (0x07f0), {D4, EP, R2_NOTR0}, 1, PROCESSOR_V850E }, -/* end-sanitize-v850e */ - -/* start-sanitize-v850eq */ -{ "sld.hu", one (0x0400), one (0x0780), {D8_7, EP, R2_NOTR0}, 1, PROCESSOR_V850EQ }, -/* end-sanitize-v850eq */ -/* start-sanitize-v850e */ + +{ "sld.hu", one (0x0400), one (0x0780), {D8_7, EP, R2_NOTR0}, 1, PROCESSOR_V850EA }, { "sld.hu", one (0x0070), one (0x07f0), {D5_4, EP, R2_NOTR0}, 1, PROCESSOR_V850E }, -/* end-sanitize-v850e */ - -/* start-sanitize-v850eq */ -{ "sld.b", one (0x0060), one (0x07f0), {D4, EP, R2}, 1, PROCESSOR_V850EQ }, -/* end-sanitize-v850eq */ -/* start-sanitize-v850e */ + +{ "sld.b", one (0x0060), one (0x07f0), {D4, EP, R2}, 1, PROCESSOR_V850EA }, { "sld.b", one (0x0300), one (0x0780), {D7, EP, R2}, 1, PROCESSOR_V850E }, -/* end-sanitize-v850e */ { "sld.b", one (0x0300), one (0x0780), {D7, EP, R2}, 1, PROCESSOR_V850 }, -/* start-sanitize-v850eq */ -{ "sld.h", one (0x0070), one (0x07f0), {D5_4, EP, R2}, 1, PROCESSOR_V850EQ }, -/* end-sanitize-v850eq */ -/* start-sanitize-v850e */ +{ "sld.h", one (0x0070), one (0x07f0), {D5_4, EP, R2}, 1, PROCESSOR_V850EA }, { "sld.h", one (0x0400), one (0x0780), {D8_7, EP, R2}, 1, PROCESSOR_V850E }, -/* end-sanitize-v850e */ - { "sld.h", one (0x0400), one (0x0780), {D8_7, EP, R2}, 1, PROCESSOR_V850 }, { "sld.w", one (0x0500), one (0x0781), {D8_6, EP, R2}, 1, PROCESSOR_ALL }, { "sst.b", one (0x0380), one (0x0780), {R2, D7, EP}, 2, PROCESSOR_ALL }, { "sst.h", one (0x0480), one (0x0780), {R2, D8_7, EP}, 2, PROCESSOR_ALL }, { "sst.w", one (0x0501), one (0x0781), {R2, D8_6, EP}, 2, PROCESSOR_ALL }, -/* start-sanitize-v850eq */ -{ "pushml", two (0x07e0, 0x0001), two (0xfff0, 0x0007), {LIST18_L}, 0, PROCESSOR_V850EQ }, -{ "pushmh", two (0x07e0, 0x0003), two (0xfff0, 0x0007), {LIST18_H}, 0, PROCESSOR_V850EQ }, -{ "popml", two (0x07f0, 0x0001), two (0xfff0, 0x0007), {LIST18_L}, 0, PROCESSOR_V850EQ }, -{ "popmh", two (0x07f0, 0x0003), two (0xfff0, 0x0007), {LIST18_H}, 0, PROCESSOR_V850EQ }, -/* end-sanitize-v850eq */ - -/* start-sanitize-v850e */ +{ "pushml", two (0x07e0, 0x0001), two (0xfff0, 0x0007), {LIST18_L}, 0, PROCESSOR_V850EA }, +{ "pushmh", two (0x07e0, 0x0003), two (0xfff0, 0x0007), {LIST18_H}, 0, PROCESSOR_V850EA }, +{ "popml", two (0x07f0, 0x0001), two (0xfff0, 0x0007), {LIST18_L}, 0, PROCESSOR_V850EA }, +{ "popmh", two (0x07f0, 0x0003), two (0xfff0, 0x0007), {LIST18_H}, 0, PROCESSOR_V850EA }, { "prepare", two (0x0780, 0x0003), two (0xffc0, 0x001f), {LIST12, IMM5, SP}, 0, PROCESSOR_NOT_V850 }, { "prepare", two (0x0780, 0x000b), two (0xffc0, 0x001f), {LIST12, IMM5, IMM16}, 0, PROCESSOR_NOT_V850 }, { "prepare", two (0x0780, 0x0013), two (0xffc0, 0x001f), {LIST12, IMM5, IMM16}, 0, PROCESSOR_NOT_V850 }, @@ -606,20 +610,16 @@ const struct v850_opcode v850_opcodes[] = { "prepare", two (0x0780, 0x0001), two (0xffc0, 0x001f), {LIST12, IMM5}, 0, PROCESSOR_NOT_V850 }, { "dispose", one (0x0640), one (0xffc0), {IMM5, LIST12, R2DISPOSE},0, PROCESSOR_NOT_V850 }, { "dispose", two (0x0640, 0x0000), two (0xffc0, 0x001f), {IMM5, LIST12}, 0, PROCESSOR_NOT_V850 }, -/* end-sanitize-v850e */ { "ld.b", two (0x0700, 0x0000), two (0x07e0, 0x0000), {D16, R1, R2}, 1, PROCESSOR_ALL }, { "ld.h", two (0x0720, 0x0000), two (0x07e0, 0x0001), {D16_15, R1, R2}, 1, PROCESSOR_ALL }, { "ld.w", two (0x0720, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2}, 1, PROCESSOR_ALL }, -/* start-sanitize-v850e */ { "ld.bu", two (0x0780, 0x0001), two (0x07c0, 0x0001), {D16_16, R1, R2_NOTR0}, 1, PROCESSOR_NOT_V850 }, { "ld.hu", two (0x07e0, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2_NOTR0}, 1, PROCESSOR_NOT_V850 }, -/* end-sanitize-v850e */ { "st.b", two (0x0740, 0x0000), two (0x07e0, 0x0000), {R2, D16, R1}, 2, PROCESSOR_ALL }, { "st.h", two (0x0760, 0x0000), two (0x07e0, 0x0001), {R2, D16_15, R1}, 2, PROCESSOR_ALL }, { "st.w", two (0x0760, 0x0001), two (0x07e0, 0x0001), {R2, D16_15, R1}, 2, PROCESSOR_ALL }, -/* start-sanitize-v850e */ /* byte swap/extend instructions */ { "zxb", one (0x0080), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, { "zxh", one (0x00c0), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, @@ -633,11 +633,9 @@ const struct v850_opcode v850_opcodes[] = { "switch", one (0x0040), one (0xffe0), {R1}, 1, PROCESSOR_NOT_V850 }, { "callt", one (0x0200), one (0xffc0), {I6}, 0, PROCESSOR_NOT_V850 }, { "ctret", two (0x07e0, 0x0144), two (0xffff, 0xffff), {0}, 0, PROCESSOR_NOT_V850 }, -/* end-sanitize-v850e */ /* arithmetic operation instructions */ { "setf", two (0x07e0, 0x0000), two (0x07f0, 0xffff), {CCCC, R2}, 0, PROCESSOR_ALL }, -/* start-sanitize-v850e */ { "cmov", two (0x07e0, 0x0320), two (0x07e0, 0x07e1), {MOVCC, R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, { "cmov", two (0x07e0, 0x0300), two (0x07e0, 0x07e1), {MOVCC, I5, R2, R3}, 0, PROCESSOR_NOT_V850 }, @@ -650,25 +648,20 @@ const struct v850_opcode v850_opcodes[] = { "divu", two (0x07e0, 0x02c2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, { "divhu", two (0x07e0, 0x0282), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, { "divh", two (0x07e0, 0x0280), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, -/* end-sanitize-v850e */ { "divh", OP (0x02), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, -/* start-sanitize-v850eq */ -{ "divhn", two (0x07e0, 0x0280), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EQ }, -{ "divhun", two (0x07e0, 0x0282), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EQ }, -{ "divn", two (0x07e0, 0x02c0), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EQ }, -{ "divun", two (0x07e0, 0x02c2), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EQ }, -{ "sdivhn", two (0x07e0, 0x0180), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EQ }, -{ "sdivhun", two (0x07e0, 0x0182), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EQ }, -{ "sdivn", two (0x07e0, 0x01c0), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EQ }, -{ "sdivun", two (0x07e0, 0x01c2), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EQ }, -/* end-sanitize-v850eq */ +{ "divhn", two (0x07e0, 0x0280), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EA }, +{ "divhun", two (0x07e0, 0x0282), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EA }, +{ "divn", two (0x07e0, 0x02c0), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EA }, +{ "divun", two (0x07e0, 0x02c2), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EA }, +{ "sdivhn", two (0x07e0, 0x0180), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EA }, +{ "sdivhun", two (0x07e0, 0x0182), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EA }, +{ "sdivn", two (0x07e0, 0x01c0), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EA }, +{ "sdivun", two (0x07e0, 0x01c2), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EA }, { "nop", one (0x00), one (0xffff), {0}, 0, PROCESSOR_ALL }, { "mov", OP (0x10), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL }, -/* start-sanitize-v850e */ { "mov", one (0x0620), one (0xffe0), {IMM32, R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, -/* end-sanitize-v850e */ { "mov", OP (0x00), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, { "movea", OP (0x31), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, { "movhi", OP (0x32), OP_MASK, {I16U, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, @@ -705,9 +698,7 @@ const struct v850_opcode v850_opcodes[] = { "shl", two (0x07e0, 0x00c0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL }, { "shr", OP (0x14), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL }, { "shr", two (0x07e0, 0x0080), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL }, -/* start-sanitize-v850e */ { "sasf", two (0x07e0, 0x0200), two (0x07f0, 0xffff), {CCCC, R2}, 0, PROCESSOR_NOT_V850 }, -/* end-sanitize-v850e */ /* branch instructions */ /* signed integer */ @@ -770,21 +761,13 @@ const struct v850_opcode v850_opcodes[] = /* bit manipulation instructions */ { "set1", two (0x07c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL }, -/* start-sanitize-v850e */ { "set1", two (0x07e0, 0x00e0), two (0x07e0, 0xffff), {R2, R1}, 2, PROCESSOR_NOT_V850 }, -/* end-sanitize-v850e */ { "not1", two (0x47c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL }, -/* start-sanitize-v850e */ { "not1", two (0x07e0, 0x00e2), two (0x07e0, 0xffff), {R2, R1}, 2, PROCESSOR_NOT_V850 }, -/* end-sanitize-v850e */ { "clr1", two (0x87c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL }, -/* start-sanitize-v850e */ { "clr1", two (0x07e0, 0x00e4), two (0x07e0, 0xffff), {R2, R1}, 2, PROCESSOR_NOT_V850 }, -/* end-sanitize-v850e */ { "tst1", two (0xc7c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL }, -/* start-sanitize-v850e */ { "tst1", two (0x07e0, 0x00e6), two (0x07e0, 0xffff), {R2, R1}, 2, PROCESSOR_NOT_V850 }, -/* end-sanitize-v850e */ /* special instructions */ { "di", two (0x07e0, 0x0160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL },