X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=sim%2Faarch64%2FChangeLog;h=1b907b94c9c506d50540aca4a2234089ca5db82d;hb=5fd104addfddb68844fb8df67be832ee98ad9888;hp=e8d66a6a76a9af510f7aea4693fb25cb512b5c62;hpb=742e3a7781c7f29136ccc36673ef2c887ba2860d;p=deliverable%2Fbinutils-gdb.git

diff --git a/sim/aarch64/ChangeLog b/sim/aarch64/ChangeLog
index e8d66a6a76..1b907b94c9 100644
--- a/sim/aarch64/ChangeLog
+++ b/sim/aarch64/ChangeLog
@@ -1,3 +1,69 @@
+2020-02-06  Carlo Bramini  <carlo_bramini@users.sourceforge.net>
+
+	PR sim/25318
+	* simulator.c (blr): Read destination register before calling
+	aarch64_save_LR.
+
+2019-03-28  Andrew Burgess  <andrew.burgess@embecosm.com>
+
+	* cpustate.c: Add 'libiberty.h' include.
+	* interp.c: Add 'sim-assert.h' include.
+
+2017-09-06  John Baldwin  <jhb@FreeBSD.org>
+
+	* configure: Regenerate.
+
+2017-04-22  Jim Wilson  <jim.wilson@linaro.org>
+
+	* simulator.c (vec_load): Add M argument.  Rewrite to iterate over
+	registers based on structure size.
+	(LD4, LD3, LD2, LD1_2, LD1_3, LD1_4): Pass new arg to vec_load.
+	(LD1_1): Replace with call to vec_load.
+	(vec_store): Add new M argument.  Rewrite to iterate over registers
+	based on structure size.
+	(ST4, ST3, ST2, ST1_2, ST1_3, ST1_4): Pass new arg to vec_store.
+	(ST1_1): Replace with call to vec_store.
+
+2017-04-08  Jim Wilson  <jim.wilson@linaro.org>
+
+	* simulator.c (do_vec_FCVTL): New.
+	(do_vec_op1): Call do_vec_FCVTL.
+
+	* simulator.c (do_scalar_FCMGE_zero, do_scalar_FCMLE_zero,
+	do_scalar_FCMGT_zero, do_scalar_FCMEQ_zero, do_scalar_FCMLT_zero): New.
+	(do_scalar_vec): Add calls to new functions.
+
+2017-03-25  Jim Wilson  <jim.wilson@linaro.org>
+
+	* simulator.c (set_flags_for_add32): Cast result to uint32_t in carry
+	flag check.
+
+2017-03-03  Jim Wilson  <jim.wilson@linaro.org>
+
+	* simulator.c (mul64hi): Shift carry left by 32.
+	(smulh): Change signum to negate.  If negate, invert result, and add
+	carry bit if low part of multiply result is zero.
+
+2017-02-25  Jim Wilson  <jim.wilson@linaro.org>
+
+	* simulator.c (do_vec_SMOV_into_scalar): New.
+	(do_vec_UMOV_into_scalar): Renamed from do_vec_MOV_into_scalar.
+	Rewritten.
+	(do_vec_UMOV): Merged into do_vec_UMOV_into_scalar and deleted.
+	(do_vec_op1): Move do_vec_TRN call and do_vec_UZP call.  Add
+	do_vec_SMOV_into_scalar call.  Delete do_vec_MOV_into_scalar and
+	do_vec_UMOV calls.  Add do_vec_UMOV_into_scalar call.
+
+	* simulator.c (popcount): New.
+	(do_vec_CNT): New.
+	(do_vec_op1): Add do_vec_CNT call.
+
+2017-02-19  Jim Wilson  <jim.wilson@linaro.org>
+
+	* simulator.c (do_vec_ADDV): Mov val declaration inside each case,
+	with type set to input type size.
+	(do_vec_xtl): Change bias from 3 to 4 for byte case.
+
 2017-02-14  Jim Wilson  <jim.wilson@linaro.org>
 
 	* simulator.c (do_vec_MLA): Rewrite switch body.