X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=sim%2Fbfin%2Fdv-bfin_rtc.c;h=3180474e9e56c5157ec8b9080c972978be50e21d;hb=3af96c0d99dedab49d2b82b730c74c27ce99bba4;hp=1b201484a7ddd0f4a8ab5d12d4f12704e402a125;hpb=9922f80319007ace0ad526d70019b3b5fee72a8d;p=deliverable%2Fbinutils-gdb.git

diff --git a/sim/bfin/dv-bfin_rtc.c b/sim/bfin/dv-bfin_rtc.c
index 1b201484a7..3180474e9e 100644
--- a/sim/bfin/dv-bfin_rtc.c
+++ b/sim/bfin/dv-bfin_rtc.c
@@ -1,6 +1,6 @@
 /* Blackfin Real Time Clock (RTC) model.
 
-   Copyright (C) 2010-2011 Free Software Foundation, Inc.
+   Copyright (C) 2010-2020 Free Software Foundation, Inc.
    Contributed by Analog Devices, Inc.
 
    This file is part of simulators.
@@ -61,6 +61,10 @@ bfin_rtc_io_write_buffer (struct hw *me, const void *source,
   bu32 *value32p;
   void *valuep;
 
+  /* Invalid access mode is higher priority than missing register.  */
+  if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, true))
+    return 0;
+
   if (nr_bytes == 4)
     value = dv_load_4 (source);
   else
@@ -104,6 +108,10 @@ bfin_rtc_io_read_buffer (struct hw *me, void *dest,
   bu32 *value32p;
   void *valuep;
 
+  /* Invalid access mode is higher priority than missing register.  */
+  if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, false))
+    return 0;
+
   mmr_off = addr - rtc->base;
   valuep = (void *)((unsigned long)rtc + mmr_base() + mmr_off);
   value16p = valuep;