X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=sim%2Fbfin%2Fdv-bfin_uart2.c;h=4d36eff3d4209bb3f80ddfe62ac3d976f9985b36;hb=a4a66f71328fe2cd216cbc1e99285de28bbaed1e;hp=5b379bb3e5ebe1e7a3012a4559f071b08108eb5d;hpb=81d126c3be15c1104b082683104856bede936d47;p=deliverable%2Fbinutils-gdb.git

diff --git a/sim/bfin/dv-bfin_uart2.c b/sim/bfin/dv-bfin_uart2.c
index 5b379bb3e5..4d36eff3d4 100644
--- a/sim/bfin/dv-bfin_uart2.c
+++ b/sim/bfin/dv-bfin_uart2.c
@@ -1,7 +1,7 @@
 /* Blackfin Universal Asynchronous Receiver/Transmitter (UART) model.
    For "new style" UARTs on BF50x/BF54x parts.
 
-   Copyright (C) 2010-2011 Free Software Foundation, Inc.
+   Copyright (C) 2010-2012 Free Software Foundation, Inc.
    Contributed by Analog Devices, Inc.
 
    This file is part of simulators.
@@ -89,7 +89,7 @@ bfin_uart_io_write_buffer (struct hw *me, const void *source,
   switch (mmr_off)
     {
     case mmr_offset(thr):
-      uart->thr = bfin_uart_write_byte (me, value);
+      uart->thr = bfin_uart_write_byte (me, value, uart->mcr);
       if (uart->ier & ETBEI)
 	hw_port_event (me, DV_PORT_TX, 1);
       break;
@@ -97,10 +97,10 @@ bfin_uart_io_write_buffer (struct hw *me, const void *source,
       uart->ier |= value;
       break;
     case mmr_offset(ier_clear):
-      dv_w1c_2 (&uart->ier, value, 0);
+      dv_w1c_2 (&uart->ier, value, -1);
       break;
     case mmr_offset(lsr):
-      dv_w1c_2 (valuep, value, TEMT | THRE | DR);
+      dv_w1c_2 (valuep, value, TFI | BI | FE | PE | OE);
       break;
     case mmr_offset(rbr):
       /* XXX: Writes are ignored ?  */
@@ -142,7 +142,7 @@ bfin_uart_io_read_buffer (struct hw *me, void *dest,
   switch (mmr_off)
     {
     case mmr_offset(rbr):
-      uart->rbr = bfin_uart_get_next_byte (me, uart->rbr, NULL);
+      uart->rbr = bfin_uart_get_next_byte (me, uart->rbr, uart->mcr, NULL);
       dv_store_2 (dest, uart->rbr);
       break;
     case mmr_offset(ier_set):
@@ -151,6 +151,7 @@ bfin_uart_io_read_buffer (struct hw *me, void *dest,
       bfin_uart_reschedule (me);
       break;
     case mmr_offset(lsr):
+      uart->lsr &= ~(DR | THRE | TEMT);
       uart->lsr |= bfin_uart_get_status (me);
     case mmr_offset(thr):
     case mmr_offset(msr):