X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=sim%2Fcommon%2FMake-common.in;h=485b676a12d5de2098f30939b1f8e7085be8c7c3;hb=0e701ac37b0154048977636afe262f55a9150492;hp=fb1cf8f5db02e4fc3799c5dde3928bbbe1e893d4;hpb=22469a10e8be365c0c85af41370cf5aa8e33bb51;p=deliverable%2Fbinutils-gdb.git

diff --git a/sim/common/Make-common.in b/sim/common/Make-common.in
index fb1cf8f5db..485b676a12 100644
--- a/sim/common/Make-common.in
+++ b/sim/common/Make-common.in
@@ -144,6 +144,7 @@ SIM_NEW_COMMON_OBJS = \
 	sim-events.o \
 	sim-fpu.o \
 	sim-io.o \
+	sim-info.o \
 	sim-load.o \
 	sim-memopt.o \
 	sim-module.o \
@@ -237,14 +238,14 @@ targ-map.o: targ-map.c targ-vals.h
 gentmap: Makefile $(srccom)/gentmap.c targ-vals.def
 	$(CC_FOR_BUILD) $(srccom)/gentmap.c -o gentmap $(BUILD_CFLAGS) $(NL_TARGET)
 
-targ-vals.h: gentmap
-	rm -f targ-vals.h
-	./gentmap -h >targ-vals.h
-
-targ-map.c: gentmap
-	rm -f targ-map.c
-	./gentmap -c >targ-map.c
-
+targ-vals.h targ-map.c: stamp-tvals
+stamp-tvals: gentmap
+	rm -f tmp-tvals.h tmp-tmap.c
+	./gentmap -h >tmp-tvals.h
+	$(srcroot)/move-if-change tmp-tvals.h targ-vals.h
+	./gentmap -c >tmp-tmap.c
+	$(srcroot)/move-if-change tmp-tmap.c targ-map.c
+	touch stamp-tvals
 
 #
 # Rules for building sim-* components.  Triggered by listing the corresponding
@@ -300,10 +301,11 @@ sim-bits.o: $(srccom)/sim-bits.c $(sim-bits_h) $(sim-n-bits_h) \
 	$(CC) -c $(srccom)/sim-bits.c $(ALL_CFLAGS)
 
 sim-config.o: $(srccom)/sim-config.c $(sim-config_h) \
-	$(SIM_EXTRA_DEPS)
+	  $(SIM_EXTRA_DEPS)
 	$(CC) -c $(srccom)/sim-config.c $(ALL_CFLAGS)
 
-sim-core.o: $(srccom)/sim-core.c $(sim-core_h) $(sim-n-core_h) \
+sim-core.o: $(srccom)/sim-core.c $(sim_main_headers) \
+	  $(sim-core_h) $(sim-n-core_h) \
 	  $(SIM_EXTRA_DEPS)
 	$(CC) -c $(srccom)/sim-core.c $(ALL_CFLAGS)
 
@@ -332,6 +334,11 @@ sim-hrw.o: $(srccom)/sim-hrw.c $(sim-assert_h) $(sim_core_h) \
 	  $(SIM_EXTRA_DEPS)
 	$(CC) -c $(srccom)/sim-hrw.c $(ALL_CFLAGS)
 
+sim-info.o: $(srccom)/sim-info.c $(sim-assert_h) \
+	  $(srcroot)/include/remote-sim.h \
+	  $(SIM_EXTRA_DEPS)
+	$(CC) -c $(srccom)/sim-info.c $(ALL_CFLAGS)
+
 sim-inline.c: $(srccom)/sim-inline.c
 	rm -f $@ tmp-$@
 	echo "# 1 \"$(srccom)/$@\"" > tmp-$@
@@ -404,12 +411,10 @@ nrun.o: $(srccom)/nrun.c config.h tconfig.h \
 # CGEN support.
 
 cgen-run.o: $(srccom)/cgen-run.c $(sim_main_headers) \
-	  $(srccom)/cgen-mem.h $(srccom)/cgen-ops.h \
-	  $(srccom)/cgen-scache.h
+	  $(srccom)/cgen-mem.h $(srccom)/cgen-ops.h
 	$(CC) -c $(srccom)/cgen-run.c $(ALL_CFLAGS)
 
-cgen-scache.o: $(srccom)/cgen-scache.c $(sim_main_headers) \
-	  $(srccom)/cgen-scache.h
+cgen-scache.o: $(srccom)/cgen-scache.c $(sim_main_headers)
 	$(CC) -c $(srccom)/cgen-scache.c $(ALL_CFLAGS)
 
 cgen-trace.o: $(srccom)/cgen-trace.c $(sim_main_headers) \
@@ -432,6 +437,7 @@ installdirs:
 	$(SHELL) $(srcdir)/../../mkinstalldirs $(bindir)
 
 check:
+	cd ../testsuite && $(MAKE) check
 
 info:
 clean-info:
@@ -448,7 +454,7 @@ TAGS: force
 clean: $(SIM_EXTRA_CLEAN)
 	rm -f *.[oa] *~ core
 	rm -f run libsim.a
-	rm -f gentmap targ-map.c targ-vals.h
+	rm -f gentmap targ-map.c targ-vals.h stamp-tvals
 	if [ ! -f Make-common.in ] ; then \
 		rm -f $(BUILT_SRC_FROM_COMMON) ; \
 	fi
@@ -478,4 +484,53 @@ stamp-h: config.in config.status
 .gdbinit: # config.status $(srccom)/gdbinit.in
 	CONFIG_FILES=$@:../common/gdbinit.in CONFIG_HEADERS= $(SHELL) ./config.status
 
+# start-sanitize-cygnus
+
+# CGEN support
+
+SCHEME = @SCHEME@
+SCHEMEFLAGS = -s
+srccgen = $(srcroot)/cgen
+
+CGEN_VERBOSE = -v
+CGEN_MAIN_SCM = $(srccgen)/object.scm $(srccgen)/utils.scm \
+	$(srccgen)/attr.scm $(srccgen)/enum.scm $(srccgen)/types.scm \
+	$(srccgen)/utils-cgen.scm $(srccgen)/cpu.scm \
+	$(srccgen)/mode.scm $(srccgen)/mach.scm \
+	$(srccgen)/model.scm $(srccgen)/hardware.scm \
+	$(srccgen)/ifield.scm $(srccgen)/iformat.scm \
+	$(srccgen)/operand.scm $(srccgen)/insn.scm \
+	$(srccgen)/cdl-c.scm $(srccgen)/sim.scm
+CGEN_CPU_SCM = $(srccgen)/sim-cpu.scm $(srccgen)/sim-model.scm
+CGEN_DECODE_SCM = $(srccgen)/sim-decode.scm
+
+# Various choices for which cpu specific files to generate.
+CGEN_CPU_EXTR = -E tmp-ext.c1
+CGEN_CPU_READ = -R tmp-read.c1
+CGEN_CPU_SEM = -S tmp-sem.c1
+CGEN_CPU_SEMSW = -W tmp-semsw.c1
+
+# We store the generated files in the source directory until we decide to
+# ship a Scheme interpreter with gdb/binutils.  Maybe we never will.
+
+cgen-arch: force
+	$(SHELL) $(srccom)/cgen.sh arch $(srcdir) \
+		$(SCHEME) $(SCHEMEFLAGS) \
+		$(srccgen) $(CGEN_VERBOSE) \
+		$(arch) "$(FLAGS)" ignored ignored ignored ignored
+
+cgen-cpu: force
+	$(SHELL) $(srccom)/cgen.sh cpu $(srcdir) \
+		$(SCHEME) $(SCHEMEFLAGS) \
+		$(srccgen) $(CGEN_VERBOSE) \
+		$(arch) "$(FLAGS)" $(cpu) $(mach) "$(SUFFIX)" "$(EXTRAFILES)"
+
+cgen-decode: force
+	$(SHELL) $(srccom)/cgen.sh decode $(srcdir) \
+		$(SCHEME) $(SCHEMEFLAGS) \
+		$(srccgen) $(CGEN_VERBOSE) \
+		$(arch) "$(FLAGS)" $(cpu) $(mach) "$(SUFFIX)" ignored
+
+# end-sanitize-cygnus
+
 ## End COMMON_POST_CONFIG_FRAG