X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=sim%2Fcommon%2Fcgen-par.h;h=914f4cc637b8dec4020a21c5bf522240db03c966;hb=a435742a7fb32f6320ce0e6074e2500e28378104;hp=25272a3c5e7a7068b7cfa9eec01ee21dc17aa5ea;hpb=c2c6d25f0d5eea4f834420870021a8c52db24018;p=deliverable%2Fbinutils-gdb.git diff --git a/sim/common/cgen-par.h b/sim/common/cgen-par.h index 25272a3c5e..914f4cc637 100644 --- a/sim/common/cgen-par.h +++ b/sim/common/cgen-par.h @@ -1,22 +1,21 @@ /* Simulator header for cgen parallel support. - Copyright (C) 1999 Free Software Foundation, Inc. + Copyright (C) 1999-2020 Free Software Foundation, Inc. Contributed by Cygnus Solutions. This file is part of the GNU instruction set simulator. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. +the Free Software Foundation; either version 3 of the License, or +(at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. -You should have received a copy of the GNU General Public License along -with this program; if not, write to the Free Software Foundation, Inc., -59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +You should have received a copy of the GNU General Public License +along with this program. If not, see . */ #ifndef CGEN_PAR_H #define CGEN_PAR_H @@ -25,14 +24,22 @@ with this program; if not, write to the Free Software Foundation, Inc., enum cgen_write_queue_kind { CGEN_BI_WRITE, CGEN_QI_WRITE, CGEN_SI_WRITE, CGEN_SF_WRITE, CGEN_PC_WRITE, - CGEN_FN_SI_WRITE, CGEN_FN_DI_WRITE, CGEN_FN_DF_WRITE, - CGEN_MEM_QI_WRITE, CGEN_MEM_HI_WRITE, CGEN_MEM_SI_WRITE, + CGEN_FN_HI_WRITE, CGEN_FN_SI_WRITE, CGEN_FN_SF_WRITE, + CGEN_FN_DI_WRITE, CGEN_FN_DF_WRITE, + CGEN_FN_XI_WRITE, CGEN_FN_PC_WRITE, + CGEN_MEM_QI_WRITE, CGEN_MEM_HI_WRITE, CGEN_MEM_SI_WRITE, CGEN_MEM_DI_WRITE, + CGEN_MEM_DF_WRITE, CGEN_MEM_XI_WRITE, + CGEN_FN_MEM_QI_WRITE, CGEN_FN_MEM_HI_WRITE, CGEN_FN_MEM_SI_WRITE, + CGEN_FN_MEM_DI_WRITE, CGEN_FN_MEM_DF_WRITE, CGEN_FN_MEM_XI_WRITE, CGEN_NUM_WRITE_KINDS }; /* Element of the write queue. */ typedef struct { enum cgen_write_queue_kind kind; /* Used to select union member below. */ + IADDR insn_address; /* Address of the insn performing the write. */ + unsigned32 flags; /* Target specific flags. */ + long word1; /* Target specific field. */ union { struct { BI *target; @@ -53,11 +60,21 @@ typedef struct { struct { USI value; } pc_write; + struct { + UINT regno; + UHI value; + void (*function)(SIM_CPU *, UINT, UHI); + } fn_hi_write; struct { UINT regno; SI value; void (*function)(SIM_CPU *, UINT, USI); } fn_si_write; + struct { + UINT regno; + SF value; + void (*function)(SIM_CPU *, UINT, SF); + } fn_sf_write; struct { UINT regno; DI value; @@ -65,9 +82,18 @@ typedef struct { } fn_di_write; struct { UINT regno; - DI value; - void (*function)(SIM_CPU *, UINT, DI); + DF value; + void (*function)(SIM_CPU *, UINT, DF); } fn_df_write; + struct { + UINT regno; + SI value[4]; + void (*function)(SIM_CPU *, UINT, SI *); + } fn_xi_write; + struct { + USI value; + void (*function)(SIM_CPU *, USI); + } fn_pc_write; struct { SI address; QI value; @@ -80,10 +106,55 @@ typedef struct { SI address; SI value; } mem_si_write; + struct { + SI address; + DI value; + } mem_di_write; + struct { + SI address; + DF value; + } mem_df_write; + struct { + SI address; + SI value[4]; + } mem_xi_write; + struct { + SI address; + QI value; + void (*function)(SIM_CPU *, IADDR, SI, QI); + } fn_mem_qi_write; + struct { + SI address; + HI value; + void (*function)(SIM_CPU *, IADDR, SI, HI); + } fn_mem_hi_write; + struct { + SI address; + SI value; + void (*function)(SIM_CPU *, IADDR, SI, SI); + } fn_mem_si_write; + struct { + SI address; + DI value; + void (*function)(SIM_CPU *, IADDR, SI, DI); + } fn_mem_di_write; + struct { + SI address; + DF value; + void (*function)(SIM_CPU *, IADDR, SI, DF); + } fn_mem_df_write; + struct { + SI address; + SI value[4]; + void (*function)(SIM_CPU *, IADDR, SI, SI *); + } fn_mem_xi_write; } kinds; } CGEN_WRITE_QUEUE_ELEMENT; #define CGEN_WRITE_QUEUE_ELEMENT_KIND(element) ((element)->kind) +#define CGEN_WRITE_QUEUE_ELEMENT_IADDR(element) ((element)->insn_address) +#define CGEN_WRITE_QUEUE_ELEMENT_FLAGS(element) ((element)->flags) +#define CGEN_WRITE_QUEUE_ELEMENT_WORD1(element) ((element)->word1) extern void cgen_write_queue_element_execute ( SIM_CPU *, CGEN_WRITE_QUEUE_ELEMENT * @@ -91,7 +162,7 @@ extern void cgen_write_queue_element_execute ( /* Instance of the queue for parallel write-after support. */ /* FIXME: Should be dynamic? */ -#define CGEN_WRITE_QUEUE_SIZE (4 * 4) /* 4 writes x 4 insns -- for now. */ +#define CGEN_WRITE_QUEUE_SIZE (64 * 4) /* 64 writes x 4 insns -- for now. */ typedef struct { int index; @@ -118,12 +189,26 @@ extern void sim_queue_sf_write (SIM_CPU *, SI *, SF); extern void sim_queue_pc_write (SIM_CPU *, USI); -extern void sim_queue_fn_si_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, USI), UINT, SI); +extern void sim_queue_fn_hi_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, UHI), UINT, UHI); +extern void sim_queue_fn_si_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, USI), UINT, USI); +extern void sim_queue_fn_sf_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, SF), UINT, SF); extern void sim_queue_fn_di_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, DI), UINT, DI); -extern void sim_queue_fn_df_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, DI), UINT, DF); +extern void sim_queue_fn_df_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, DF), UINT, DF); +extern void sim_queue_fn_xi_write (SIM_CPU *, void (*)(SIM_CPU *, UINT, SI *), UINT, SI *); +extern void sim_queue_fn_pc_write (SIM_CPU *, void (*)(SIM_CPU *, USI), USI); extern void sim_queue_mem_qi_write (SIM_CPU *, SI, QI); extern void sim_queue_mem_hi_write (SIM_CPU *, SI, HI); extern void sim_queue_mem_si_write (SIM_CPU *, SI, SI); +extern void sim_queue_mem_di_write (SIM_CPU *, SI, DI); +extern void sim_queue_mem_df_write (SIM_CPU *, SI, DF); +extern void sim_queue_mem_xi_write (SIM_CPU *, SI, SI *); + +extern void sim_queue_fn_mem_qi_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, QI), SI, QI); +extern void sim_queue_fn_mem_hi_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, HI), SI, HI); +extern void sim_queue_fn_mem_si_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, SI), SI, SI); +extern void sim_queue_fn_mem_di_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, DI), SI, DI); +extern void sim_queue_fn_mem_df_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, DF), SI, DF); +extern void sim_queue_fn_mem_xi_write (SIM_CPU *, void (*)(SIM_CPU *, IADDR, SI, SI *), SI, SI *); #endif /* CGEN_PAR_H */