X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=sim%2Fcommon%2Fcgen-trace.c;h=2332df4f3d98f75b2f011de0b0e15b312a037b72;hb=128e85e3ab36b8e30f6612fb50de3cbb4ede6824;hp=db852d5306c60c5b2339f7a2c02456a96b1766d9;hpb=30727aa6d12fb866494020c0b62ab265a2bdcdfe;p=deliverable%2Fbinutils-gdb.git
diff --git a/sim/common/cgen-trace.c b/sim/common/cgen-trace.c
index db852d5306..2332df4f3d 100644
--- a/sim/common/cgen-trace.c
+++ b/sim/common/cgen-trace.c
@@ -1,30 +1,28 @@
/* Tracing support for CGEN-based simulators.
- Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+ Copyright (C) 1996-2016 Free Software Foundation, Inc.
Contributed by Cygnus Support.
This file is part of GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+the Free Software Foundation; either version 3 of the License, or
+(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+You should have received a copy of the GNU General Public License
+along with this program. If not, see . */
+#include "config.h"
#include
#include "dis-asm.h"
#include "bfd.h"
#include "sim-main.h"
-
-#undef min
-#define min(a,b) ((a) < (b) ? (a) : (b))
+#include "sim-fpu.h"
#ifndef SIZE_INSTRUCTION
#define SIZE_INSTRUCTION 16
@@ -51,13 +49,9 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#endif
#ifndef SIZE_TRACE_BUF
-#define SIZE_TRACE_BUF 256
+#define SIZE_TRACE_BUF 1024
#endif
-static void
-disassemble_insn (SIM_CPU *, const CGEN_INSN *,
- const struct argbuf *, IADDR, char *);
-
/* Text is queued in TRACE_BUF because we want to output the insn's cycle
count first but that isn't known until after the insn has executed.
This also handles the queueing of trace results, TRACE_RESULT may be
@@ -69,29 +63,30 @@ static char *bufptr;
/* Non-zero if this is the first insn in a set of parallel insns. */
static int first_insn_p;
-/* For communication between trace_insn and trace_result. */
+/* For communication between cgen_trace_insn and cgen_trace_result. */
static int printed_result_p;
/* Insn and its extracted fields.
- Set by trace_insn, used by trace_insn_fini.
+ Set by cgen_trace_insn, used by cgen_trace_insn_fini.
??? Move to SIM_CPU to support heterogeneous multi-cpu case. */
static const struct cgen_insn *current_insn;
static const struct argbuf *current_abuf;
void
-trace_insn_init (SIM_CPU *cpu, int first_p)
+cgen_trace_insn_init (SIM_CPU *cpu, int first_p)
{
bufptr = trace_buf;
*bufptr = 0;
first_insn_p = first_p;
- /* Set to NULL so trace_insn_fini can know if trace_insn was called. */
+ /* Set to NULL so cgen_trace_insn_fini can know if cgen_trace_insn was
+ called. */
current_insn = NULL;
current_abuf = NULL;
}
void
-trace_insn_fini (SIM_CPU *cpu, const struct argbuf *abuf, int last_p)
+cgen_trace_insn_fini (SIM_CPU *cpu, const struct argbuf *abuf, int last_p)
{
SIM_DESC sd = CPU_STATE (cpu);
@@ -146,7 +141,7 @@ trace_insn_fini (SIM_CPU *cpu, const struct argbuf *abuf, int last_p)
++i, ++opinst)
{
if (CGEN_OPINST_TYPE (opinst) == CGEN_OPINST_OUTPUT)
- trace_result (cpu, current_insn, opinst, indices[i]);
+ cgen_trace_result (cpu, current_insn, opinst, indices[i]);
}
}
}
@@ -161,8 +156,8 @@ trace_insn_fini (SIM_CPU *cpu, const struct argbuf *abuf, int last_p)
}
void
-trace_insn (SIM_CPU *cpu, const struct cgen_insn *opcode,
- const struct argbuf *abuf, IADDR pc)
+cgen_trace_insn (SIM_CPU *cpu, const struct cgen_insn *opcode,
+ const struct argbuf *abuf, IADDR pc)
{
char disasm_buf[50];
@@ -186,7 +181,7 @@ trace_insn (SIM_CPU *cpu, const struct cgen_insn *opcode,
}
void
-trace_extract (SIM_CPU *cpu, IADDR pc, char *name, ...)
+cgen_trace_extract (SIM_CPU *cpu, IADDR pc, char *name, ...)
{
va_list args;
int printed_one_p = 0;
@@ -195,7 +190,7 @@ trace_extract (SIM_CPU *cpu, IADDR pc, char *name, ...)
va_start (args, name);
trace_printf (CPU_STATE (cpu), cpu, "Extract: 0x%.*lx: %s ",
- SIZE_PC, pc, name);
+ SIZE_PC, (unsigned long) pc, name);
do {
int type,ival;
@@ -225,7 +220,7 @@ trace_extract (SIM_CPU *cpu, IADDR pc, char *name, ...)
}
void
-trace_result (SIM_CPU *cpu, char *name, int type, ...)
+cgen_trace_result (SIM_CPU *cpu, char *name, int type, ...)
{
va_list args;
@@ -239,6 +234,19 @@ trace_result (SIM_CPU *cpu, char *name, int type, ...)
default :
cgen_trace_printf (cpu, "%s <- 0x%x", name, va_arg (args, int));
break;
+ case 'f':
+ {
+ DI di;
+ sim_fpu f;
+
+ /* this is separated from previous line for sunos cc */
+ di = va_arg (args, DI);
+ sim_fpu_64to (&f, di);
+
+ cgen_trace_printf (cpu, "%s <- ", name);
+ sim_fpu_printn_fpu (&f, (sim_fpu_print_func *) cgen_trace_printf, 4, cpu);
+ break;
+ }
case 'D' :
{
DI di;
@@ -289,20 +297,12 @@ cgen_trace_printf (SIM_CPU *cpu, char *fmt, ...)
/* sprintf to a "stream" */
int
-sim_disasm_sprintf VPARAMS ((SFILE *f, const char *format, ...))
+sim_disasm_sprintf (SFILE *f, const char *format, ...)
{
-#ifndef __STDC__
- SFILE *f;
- const char *format;
-#endif
int n;
va_list args;
- VA_START (args, format);
-#ifndef __STDC__
- f = va_arg (args, SFILE *);
- format = va_arg (args, char *);
-#endif
+ va_start (args, format);
vsprintf (f->current, format, args);
f->current += n = strlen (f->current);
va_end (args);
@@ -312,12 +312,12 @@ sim_disasm_sprintf VPARAMS ((SFILE *f, const char *format, ...))
/* Memory read support for an opcodes disassembler. */
int
-sim_disasm_read_memory (bfd_vma memaddr, bfd_byte *myaddr, int length,
+sim_disasm_read_memory (bfd_vma memaddr, bfd_byte *myaddr, unsigned int length,
struct disassemble_info *info)
{
SIM_CPU *cpu = (SIM_CPU *) info->application_data;
SIM_DESC sd = CPU_STATE (cpu);
- int length_read;
+ unsigned length_read;
length_read = sim_core_read_buffer (sd, cpu, read_map, myaddr, memaddr,
length);
@@ -354,6 +354,7 @@ sim_cgen_disassemble_insn (SIM_CPU *cpu, const CGEN_INSN *insn,
const ARGBUF *abuf, IADDR pc, char *buf)
{
unsigned int length;
+ unsigned int base_length;
unsigned long insn_value;
struct disassemble_info disasm_info;
SFILE sfile;
@@ -380,7 +381,18 @@ sim_cgen_disassemble_insn (SIM_CPU *cpu, const CGEN_INSN *insn,
length = sim_core_read_buffer (sd, cpu, read_map, &insn_buf, pc,
insn_length);
- switch (min (cd->base_insn_bitsize, insn_bit_length))
+ if (length != insn_length)
+ {
+ sim_io_error (sd, "unable to read address %x", pc);
+ }
+
+ /* If the entire insn will fit into an integer, then do it. Otherwise, just
+ use the bits of the base_insn. */
+ if (insn_bit_length <= 32)
+ base_length = insn_bit_length;
+ else
+ base_length = min (cd->base_insn_bitsize, insn_bit_length);
+ switch (base_length)
{
case 0 : return; /* fake insn, typically "compile" (aka "invalid") */
case 8 : insn_value = insn_buf.bytes[0]; break;