X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=sim%2Fcr16%2Fsimops.c;h=30e4372384da731c94e788cfa6aa51d8889426cc;hb=17fc27167f678285d2f64040837b8cc41b6a664a;hp=f8fee8a0d234ed6c281a7e37f98e4f4b95732148;hpb=c5a570810022466eaa5e077cd1b8aa00d74706f1;p=deliverable%2Fbinutils-gdb.git diff --git a/sim/cr16/simops.c b/sim/cr16/simops.c index f8fee8a0d2..30e4372384 100644 --- a/sim/cr16/simops.c +++ b/sim/cr16/simops.c @@ -1,5 +1,5 @@ /* Simulation code for the CR16 processor. - Copyright (C) 2008-2012 Free Software Foundation, Inc. + Copyright (C) 2008-2020 Free Software Foundation, Inc. Contributed by M Ranga Swami Reddy This file is part of GDB, the GNU debugger. @@ -30,12 +30,25 @@ #ifdef HAVE_STRING_H #include #endif +#ifdef HAVE_TIME_H +#include +#endif +#ifdef HAVE_SYS_TIME_H +#include +#endif -#include "cr16_sim.h" +#include "sim-main.h" #include "simops.h" #include "targ-vals.h" -extern char *strrchr (); +#ifdef TARGET_SYS_utime +#include +#endif +#ifdef TARGET_SYS_wait +#include +#endif + +#define EXCEPTION(sig) sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, sig) enum op_types { OP_VOID, @@ -127,7 +140,7 @@ enum { * LT Less Than Z and N flags are 0 * GE Greater Than or Equal To Z or N flag is 1. */ -int cond_stat(int cc) +static int cond_stat(int cc) { switch (cc) { @@ -157,7 +170,7 @@ int cond_stat(int cc) creg_t -move_to_cr (int cr, creg_t mask, creg_t val, int psw_hw_p) +move_to_cr (SIM_DESC sd, SIM_CPU *cpu, int cr, creg_t mask, creg_t val, int psw_hw_p) { /* A MASK bit is set when the corresponding bit in the CR should be left alone. */ @@ -170,10 +183,10 @@ move_to_cr (int cr, creg_t mask, creg_t val, int psw_hw_p) #if 0 else val &= PSR_MASK; - (*cr16_callback->printf_filtered) - (cr16_callback, + sim_io_printf + (sd, "ERROR at PC 0x%x: ST can only be set when FX is set.\n", PC); - State.exception = SIGILL; + EXCEPTION (SIM_SIGILL); #endif /* keep an up-to-date psw around for tracing. */ State.trace.psw = (State.trace.psw & mask) | val; @@ -189,12 +202,13 @@ move_to_cr (int cr, creg_t mask, creg_t val, int psw_hw_p) } #ifdef DEBUG -static void trace_input_func PARAMS ((char *name, - enum op_types in1, - enum op_types in2, - enum op_types in3)); +static void trace_input_func (SIM_DESC sd, + const char *name, + enum op_types in1, + enum op_types in2, + enum op_types in3); -#define trace_input(name, in1, in2, in3) do { if (cr16_debug) trace_input_func (name, in1, in2, in3); } while (0) +#define trace_input(name, in1, in2, in3) do { if (cr16_debug) trace_input_func (sd, name, in1, in2, in3); } while (0) #ifndef SIZE_INSTRUCTION #define SIZE_INSTRUCTION 8 @@ -221,11 +235,7 @@ static void trace_input_func PARAMS ((char *name, #endif static void -trace_input_func (name, in1, in2, in3) - char *name; - enum op_types in1; - enum op_types in2; - enum op_types in3; +trace_input_func (SIM_DESC sd, const char *name, enum op_types in1, enum op_types in2, enum op_types in3) { char *comma; enum op_types in[3]; @@ -249,7 +259,7 @@ trace_input_func (name, in1, in2, in3) } if ((cr16_debug & DEBUG_LINE_NUMBER) == 0) - (*cr16_callback->printf_filtered) (cr16_callback, + sim_io_printf (sd, "0x%.*x %s: %-*s ", SIZE_PC, (unsigned)PC, type, @@ -258,13 +268,18 @@ trace_input_func (name, in1, in2, in3) else { buf[0] = '\0'; - byte_pc = decode_pc (); - if (text && byte_pc >= text_start && byte_pc < text_end) + byte_pc = PC; + if (STATE_TEXT_SECTION (sd) + && byte_pc >= STATE_TEXT_START (sd) + && byte_pc < STATE_TEXT_END (sd)) { filename = (const char *)0; functionname = (const char *)0; linenumber = 0; - if (bfd_find_nearest_line (prog_bfd, text, (struct bfd_symbol **)0, byte_pc - text_start, + if (bfd_find_nearest_line (STATE_PROG_BFD (sd), + STATE_TEXT_SECTION (sd), + (struct bfd_symbol **)0, + byte_pc - STATE_TEXT_START (sd), &filename, &functionname, &linenumber)) { p = buf; @@ -296,7 +311,7 @@ trace_input_func (name, in1, in2, in3) } } - (*cr16_callback->printf_filtered) (cr16_callback, + sim_io_printf (sd, "0x%.*x %s: %-*.*s %-*s ", SIZE_PC, (unsigned)PC, type, @@ -371,12 +386,12 @@ trace_input_func (name, in1, in2, in3) { *p++ = '\n'; *p = '\0'; - (*cr16_callback->printf_filtered) (cr16_callback, "%s", buf); + sim_io_printf (sd, "%s", buf); } else { *p = '\0'; - (*cr16_callback->printf_filtered) (cr16_callback, "%-*s", SIZE_OPERANDS, buf); + sim_io_printf (sd, "%-*s", SIZE_OPERANDS, buf); p = buf; for (i = 0; i < 3; i++) @@ -385,43 +400,43 @@ trace_input_func (name, in1, in2, in3) switch (in[i]) { case OP_VOID: - (*cr16_callback->printf_filtered) (cr16_callback, "%*s", SIZE_VALUES, ""); + sim_io_printf (sd, "%*s", SIZE_VALUES, ""); break; case OP_REG: - (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "", + sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "", (uint16) GPR (OP[i])); break; case OP_REGP: tmp = (long)((((uint32) GPR (OP[i])) << 16) | ((uint32) GPR (OP[i] + 1))); - (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp); + sim_io_printf (sd, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp); break; case OP_PROC_REG: - (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "", + sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "", (uint16) CREG (OP[i])); break; case OP_CONSTANT16: - (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "", + sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "", (uint16)OP[i]); break; case OP_CONSTANT4: - (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "", + sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "", (uint16)SEXT4(OP[i])); break; case OP_CONSTANT3: - (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "", + sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "", (uint16)SEXT3(OP[i])); break; case OP_MEMREF2: - (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "", + sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "", (uint16)OP[i]); - (*cr16_callback->printf_filtered) (cr16_callback, "%*s0x%.4x", SIZE_VALUES-6, "", + sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "", (uint16)GPR (OP[i + 1])); i++; break; @@ -429,32 +444,33 @@ trace_input_func (name, in1, in2, in3) } } - (*cr16_callback->flush_stdout) (cr16_callback); + sim_io_flush_stdout (sd); } static void -do_trace_output_flush (void) +do_trace_output_flush (SIM_DESC sd) { - (*cr16_callback->flush_stdout) (cr16_callback); + sim_io_flush_stdout (sd); } static void -do_trace_output_finish (void) +do_trace_output_finish (SIM_DESC sd) { - (*cr16_callback->printf_filtered) (cr16_callback, + sim_io_printf (sd, " F0=%d F1=%d C=%d\n", (State.trace.psw & PSR_F_BIT) != 0, (State.trace.psw & PSR_F_BIT) != 0, (State.trace.psw & PSR_C_BIT) != 0); - (*cr16_callback->flush_stdout) (cr16_callback); + sim_io_flush_stdout (sd); } +#if 0 static void -trace_output_40 (uint64 val) +trace_output_40 (SIM_DESC sd, uint64 val) { if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES)) { - (*cr16_callback->printf_filtered) (cr16_callback, + sim_io_printf (sd, " :: %*s0x%.2x%.8lx", SIZE_VALUES - 12, "", @@ -463,55 +479,56 @@ trace_output_40 (uint64 val) do_trace_output_finish (); } } +#endif static void -trace_output_32 (uint32 val) +trace_output_32 (SIM_DESC sd, uint32 val) { if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES)) { - (*cr16_callback->printf_filtered) (cr16_callback, + sim_io_printf (sd, " :: %*s0x%.8x", SIZE_VALUES - 10, "", (int) val); - do_trace_output_finish (); + do_trace_output_finish (sd); } } static void -trace_output_16 (uint16 val) +trace_output_16 (SIM_DESC sd, uint16 val) { if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES)) { - (*cr16_callback->printf_filtered) (cr16_callback, + sim_io_printf (sd, " :: %*s0x%.4x", SIZE_VALUES - 6, "", (int) val); - do_trace_output_finish (); + do_trace_output_finish (sd); } } static void -trace_output_void () +trace_output_void (SIM_DESC sd) { if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES)) { - (*cr16_callback->printf_filtered) (cr16_callback, "\n"); - do_trace_output_flush (); + sim_io_printf (sd, "\n"); + do_trace_output_flush (sd); } } static void -trace_output_flag () +trace_output_flag (SIM_DESC sd) { if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES)) { - (*cr16_callback->printf_filtered) (cr16_callback, + sim_io_printf (sd, " :: %*s", SIZE_VALUES, ""); - do_trace_output_finish (); + do_trace_output_finish (sd); } } @@ -525,7 +542,7 @@ trace_output_flag () /* addub. */ void -OP_2C_8 () +OP_2C_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 tmp; uint8 a = OP[0] & 0xff; @@ -533,128 +550,128 @@ OP_2C_8 () trace_input ("addub", OP_CONSTANT4_1, OP_REG, OP_VOID); tmp = (a + b) & 0xff; SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* addub. */ void -OP_2CB_C () +OP_2CB_C (SIM_DESC sd, SIM_CPU *cpu) { uint16 tmp; uint8 a = ((OP[0]) & 0xff), b = (GPR (OP[1])) & 0xff; trace_input ("addub", OP_CONSTANT16, OP_REG, OP_VOID); tmp = (a + b) & 0xff; SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* addub. */ void -OP_2D_8 () +OP_2D_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (GPR (OP[0])) & 0xff; uint8 b = (GPR (OP[1])) & 0xff; uint16 tmp = (a + b) & 0xff; trace_input ("addub", OP_REG, OP_REG, OP_VOID); SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* adduw. */ void -OP_2E_8 () +OP_2E_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; uint16 b = GPR (OP[1]); uint16 tmp = (a + b); trace_input ("adduw", OP_CONSTANT4_1, OP_REG, OP_VOID); SET_GPR (OP[1], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* adduw. */ void -OP_2EB_C () +OP_2EB_C (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; uint16 b = GPR (OP[1]); uint16 tmp = (a + b); trace_input ("adduw", OP_CONSTANT16, OP_REG, OP_VOID); SET_GPR (OP[1], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* adduw. */ void -OP_2F_8 () +OP_2F_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = GPR (OP[0]); uint16 b = GPR (OP[1]); uint16 tmp = (a + b); trace_input ("adduw", OP_REG, OP_REG, OP_VOID); SET_GPR (OP[1], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* addb. */ void -OP_30_8 () +OP_30_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = OP[0]; uint8 b = (GPR (OP[1]) & 0xff); - trace_input ("addb", OP_CONSTANT4_1, OP_REG, OP_VOID); uint16 tmp = (a + b) & 0xff; + trace_input ("addb", OP_CONSTANT4_1, OP_REG, OP_VOID); SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); SET_PSR_C (tmp > 0xFF); SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* addb. */ void -OP_30B_C () +OP_30B_C (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; uint8 b = (GPR (OP[1]) & 0xff); - trace_input ("addb", OP_CONSTANT16, OP_REG, OP_VOID); uint16 tmp = (a + b) & 0xff; + trace_input ("addb", OP_CONSTANT16, OP_REG, OP_VOID); SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); SET_PSR_C (tmp > 0xFF); SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* addb. */ void -OP_31_8 () +OP_31_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (GPR (OP[0]) & 0xff); uint8 b = (GPR (OP[1]) & 0xff); - trace_input ("addb", OP_REG, OP_REG, OP_VOID); uint16 tmp = (a + b) & 0xff; + trace_input ("addb", OP_REG, OP_REG, OP_VOID); SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); SET_PSR_C (tmp > 0xFF); SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* addw. */ void -OP_32_8 () +OP_32_8 (SIM_DESC sd, SIM_CPU *cpu) { int16 a = OP[0]; uint16 tmp, b = GPR (OP[1]); - trace_input ("addw", OP_CONSTANT4_1, OP_REG, OP_VOID); tmp = (a + b); + trace_input ("addw", OP_CONSTANT4_1, OP_REG, OP_VOID); SET_GPR (OP[1], tmp); SET_PSR_C (tmp > 0xFFFF); SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* addw. */ void -OP_32B_C () +OP_32B_C (SIM_DESC sd, SIM_CPU *cpu) { int16 a = OP[0]; uint16 tmp, b = GPR (OP[1]); @@ -663,12 +680,12 @@ OP_32B_C () SET_GPR (OP[1], tmp); SET_PSR_C (tmp > 0xFFFF); SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* addw. */ void -OP_33_8 () +OP_33_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 tmp, a = (GPR (OP[0])), b = (GPR (OP[1])); trace_input ("addw", OP_REG, OP_REG, OP_VOID); @@ -676,12 +693,12 @@ OP_33_8 () SET_GPR (OP[1], tmp); SET_PSR_C (tmp > 0xFFFF); SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* addcb. */ void -OP_34_8 () +OP_34_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 tmp, a = OP[0] & 0xff, b = (GPR (OP[1])) & 0xff; trace_input ("addcb", OP_CONSTANT4_1, OP_REG, OP_REG); @@ -689,124 +706,124 @@ OP_34_8 () SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); SET_PSR_C (tmp > 0xFF); SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* addcb. */ void -OP_34B_C () +OP_34B_C (SIM_DESC sd, SIM_CPU *cpu) { int8 a = OP[0] & 0xff; uint8 b = (GPR (OP[1])) & 0xff; - trace_input ("addcb", OP_CONSTANT16, OP_REG, OP_VOID); uint8 tmp = (a + b + PSR_C) & 0xff; + trace_input ("addcb", OP_CONSTANT16, OP_REG, OP_VOID); SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); SET_PSR_C (tmp > 0xFF); SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* addcb. */ void -OP_35_8 () +OP_35_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (GPR (OP[0])) & 0xff; uint8 b = (GPR (OP[1])) & 0xff; - trace_input ("addcb", OP_REG, OP_REG, OP_VOID); uint8 tmp = (a + b + PSR_C) & 0xff; + trace_input ("addcb", OP_REG, OP_REG, OP_VOID); SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); SET_PSR_C (tmp > 0xFF); SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* addcw. */ void -OP_36_8 () +OP_36_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; uint16 b = GPR (OP[1]); - trace_input ("addcw", OP_CONSTANT4_1, OP_REG, OP_VOID); uint16 tmp = (a + b + PSR_C); + trace_input ("addcw", OP_CONSTANT4_1, OP_REG, OP_VOID); SET_GPR (OP[1], tmp); SET_PSR_C (tmp > 0xFFFF); SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* addcw. */ void -OP_36B_C () +OP_36B_C (SIM_DESC sd, SIM_CPU *cpu) { int16 a = OP[0]; uint16 b = GPR (OP[1]); - trace_input ("addcw", OP_CONSTANT16, OP_REG, OP_VOID); uint16 tmp = (a + b + PSR_C); + trace_input ("addcw", OP_CONSTANT16, OP_REG, OP_VOID); SET_GPR (OP[1], tmp); SET_PSR_C (tmp > 0xFFFF); SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* addcw. */ void -OP_37_8 () +OP_37_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = GPR (OP[1]); uint16 b = GPR (OP[1]); - trace_input ("addcw", OP_REG, OP_REG, OP_VOID); uint16 tmp = (a + b + PSR_C); + trace_input ("addcw", OP_REG, OP_REG, OP_VOID); SET_GPR (OP[1], tmp); SET_PSR_C (tmp > 0xFFFF); SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* addd. */ void -OP_60_8 () +OP_60_8 (SIM_DESC sd, SIM_CPU *cpu) { int16 a = (OP[0]); uint32 b = GPR32 (OP[1]); - trace_input ("addd", OP_CONSTANT4_1, OP_REGP, OP_VOID); uint32 tmp = (a + b); + trace_input ("addd", OP_CONSTANT4_1, OP_REGP, OP_VOID); SET_GPR32 (OP[1], tmp); SET_PSR_C (tmp > 0xFFFFFFFF); SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000))); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* addd. */ void -OP_60B_C () +OP_60B_C (SIM_DESC sd, SIM_CPU *cpu) { int32 a = (SEXT16(OP[0])); uint32 b = GPR32 (OP[1]); - trace_input ("addd", OP_CONSTANT16, OP_REGP, OP_VOID); uint32 tmp = (a + b); + trace_input ("addd", OP_CONSTANT16, OP_REGP, OP_VOID); SET_GPR32 (OP[1], tmp); SET_PSR_C (tmp > 0xFFFFFFFF); SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000))); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* addd. */ void -OP_61_8 () +OP_61_8 (SIM_DESC sd, SIM_CPU *cpu) { uint32 a = GPR32 (OP[0]); uint32 b = GPR32 (OP[1]); - trace_input ("addd", OP_REGP, OP_REGP, OP_VOID); uint32 tmp = (a + b); + trace_input ("addd", OP_REGP, OP_REGP, OP_VOID); SET_GPR32 (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); SET_PSR_C (tmp > 0xFFFFFFFF); SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000))); } /* addd. */ void -OP_4_8 () +OP_4_8 (SIM_DESC sd, SIM_CPU *cpu) { uint32 a = OP[0]; uint32 b = GPR32 (OP[1]); @@ -816,12 +833,12 @@ OP_4_8 () SET_GPR32 (OP[1], tmp); SET_PSR_C (tmp > 0xFFFFFFFF); SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000))); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* addd. */ void -OP_2_C () +OP_2_C (SIM_DESC sd, SIM_CPU *cpu) { int32 a = OP[0]; uint32 b = GPR32 (OP[1]); @@ -831,147 +848,147 @@ OP_2_C () SET_GPR32 (OP[1], tmp); SET_PSR_C (tmp > 0xFFFFFFFF); SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000))); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* andb. */ void -OP_20_8 () +OP_20_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff; trace_input ("andb", OP_CONSTANT4, OP_REG, OP_VOID); tmp = a & b; SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* andb. */ void -OP_20B_C () +OP_20B_C (SIM_DESC sd, SIM_CPU *cpu) { uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff; trace_input ("andb", OP_CONSTANT16, OP_REG, OP_VOID); tmp = a & b; SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* andb. */ void -OP_21_8 () +OP_21_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff; trace_input ("andb", OP_REG, OP_REG, OP_VOID); tmp = a & b; SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* andw. */ void -OP_22_8 () +OP_22_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 tmp, a = OP[0], b = GPR (OP[1]); trace_input ("andw", OP_CONSTANT4, OP_REG, OP_VOID); tmp = a & b; SET_GPR (OP[1], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* andw. */ void -OP_22B_C () +OP_22B_C (SIM_DESC sd, SIM_CPU *cpu) { uint16 tmp, a = OP[0], b = GPR (OP[1]); trace_input ("andw", OP_CONSTANT16, OP_REG, OP_VOID); tmp = a & b; SET_GPR (OP[1], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* andw. */ void -OP_23_8 () +OP_23_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 tmp, a = GPR (OP[0]), b = GPR (OP[1]); trace_input ("andw", OP_REG, OP_REG, OP_VOID); tmp = a & b; SET_GPR (OP[1], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* andd. */ void -OP_4_C () +OP_4_C (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp, a = OP[0], b = GPR32 (OP[1]); trace_input ("andd", OP_CONSTANT32, OP_REGP, OP_VOID); tmp = a & b; SET_GPR32 (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* andd. */ void -OP_14B_14 () +OP_14B_14 (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp, a = (GPR32 (OP[0])), b = (GPR32 (OP[1])); trace_input ("andd", OP_REGP, OP_REGP, OP_VOID); tmp = a & b; SET_GPR32 (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* ord. */ void -OP_5_C () +OP_5_C (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp, a = (OP[0]), b = GPR32 (OP[1]); trace_input ("ord", OP_CONSTANT32, OP_REG, OP_VOID); tmp = a | b; SET_GPR32 (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* ord. */ void -OP_149_14 () +OP_149_14 (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]); trace_input ("ord", OP_REGP, OP_REGP, OP_VOID); tmp = a | b; SET_GPR32 (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* xord. */ void -OP_6_C () +OP_6_C (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp, a = (OP[0]), b = GPR32 (OP[1]); trace_input ("xord", OP_CONSTANT32, OP_REG, OP_VOID); tmp = a ^ b; SET_GPR32 (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* xord. */ void -OP_14A_14 () +OP_14A_14 (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]); trace_input ("xord", OP_REGP, OP_REGP, OP_VOID); tmp = a ^ b; SET_GPR32 (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* b. */ void -OP_1_4 () +OP_1_4 (SIM_DESC sd, SIM_CPU *cpu) { - uint32 tmp, cc = cond_stat (OP[0]); + uint32 tmp = 0, cc = cond_stat (OP[0]); trace_input ("b", OP_CONSTANT4, OP_DISPE9, OP_VOID); if (cc) { @@ -984,23 +1001,21 @@ OP_1_4 () if ((tmp < 0x000000) || (tmp > 0xFFFFFF)) { - State.exception = SIG_CR16_BUS; - State.pc_changed = 1; /* Don't increment the PC. */ - trace_output_void (); - return; + trace_output_void (sd); + EXCEPTION (SIM_SIGBUS); } else JMP (tmp); } sign_flag = 0; /* Reset sign_flag. */ - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* b. */ void -OP_18_8 () +OP_18_8 (SIM_DESC sd, SIM_CPU *cpu) { - uint32 tmp, cc = cond_stat (OP[0]); + uint32 tmp = 0, cc = cond_stat (OP[0]); trace_input ("b", OP_CONSTANT4, OP_DISP17, OP_VOID); if (cc) { @@ -1013,23 +1028,21 @@ OP_18_8 () if ((tmp < 0x000000) || (tmp > 0xFFFFFF)) { - State.exception = SIG_CR16_BUS; - State.pc_changed = 1; /* Don't increment the PC. */ - trace_output_void (); - return; + trace_output_void (sd); + EXCEPTION (SIM_SIGBUS); } else JMP (tmp); } sign_flag = 0; /* Reset sign_flag. */ - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* b. */ void -OP_10_10 () +OP_10_10 (SIM_DESC sd, SIM_CPU *cpu) { - uint32 tmp, cc = cond_stat (OP[0]); + uint32 tmp = 0, cc = cond_stat (OP[0]); trace_input ("b", OP_CONSTANT4, OP_DISP25, OP_VOID); if (cc) { @@ -1042,21 +1055,19 @@ OP_10_10 () if ((tmp < 0x000000) || (tmp > 0xFFFFFF)) { - State.exception = SIG_CR16_BUS; - State.pc_changed = 1; /* Don't increment the PC. */ - trace_output_void (); - return; + trace_output_void (sd); + EXCEPTION (SIM_SIGBUS); } else JMP (tmp); } sign_flag = 0; /* Reset sign_flag. */ - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* bal. */ void -OP_C0_8 () +OP_C0_8 (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp; trace_input ("bal", OP_REG, OP_DISP17, OP_VOID); @@ -1072,21 +1083,19 @@ OP_C0_8 () if ((tmp < 0x000000) || (tmp > 0xFFFFFF)) { - State.exception = SIG_CR16_BUS; - State.pc_changed = 1; /* Don't increment the PC. */ - trace_output_void (); - return; + trace_output_void (sd); + EXCEPTION (SIM_SIGBUS); } else JMP (tmp); sign_flag = 0; /* Reset sign_flag. */ - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* bal. */ void -OP_102_14 () +OP_102_14 (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp; trace_input ("bal", OP_REGP, OP_DISP25, OP_VOID); @@ -1101,20 +1110,18 @@ OP_102_14 () if ((tmp < 0x000000) || (tmp > 0xFFFFFF)) { - State.exception = SIG_CR16_BUS; - State.pc_changed = 1; /* Don't increment the PC. */ - trace_output_void (); - return; + trace_output_void (sd); + EXCEPTION (SIM_SIGBUS); } else JMP (tmp); sign_flag = 0; /* Reset sign_flag. */ - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* jal. */ void -OP_148_14 () +OP_148_14 (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp; trace_input ("jal", OP_REGP, OP_REGP, OP_VOID); @@ -1126,21 +1133,19 @@ OP_148_14 () if ((tmp < 0x0) || (tmp > 0xFFFFFF)) { - State.exception = SIG_CR16_BUS; - State.pc_changed = 1; /* Don't increment the PC. */ - trace_output_void (); - return; + trace_output_void (sd); + EXCEPTION (SIM_SIGBUS); } else JMP (tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* jal. */ void -OP_D_C () +OP_D_C (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp; trace_input ("jal", OP_REGP, OP_VOID, OP_VOID); @@ -1152,21 +1157,19 @@ OP_D_C () if ((tmp < 0x0) || (tmp > 0xFFFFFF)) { - State.exception = SIG_CR16_BUS; - State.pc_changed = 1; /* Don't increment the PC. */ - trace_output_void (); - return; + trace_output_void (sd); + EXCEPTION (SIM_SIGBUS); } else JMP (tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* beq0b. */ void -OP_C_8 () +OP_C_8 (SIM_DESC sd, SIM_CPU *cpu) { uint32 addr; uint8 a = (GPR (OP[0]) & 0xFF); @@ -1182,12 +1185,12 @@ OP_C_8 () JMP (addr); } sign_flag = 0; /* Reset sign_flag. */ - trace_output_void (); + trace_output_void (sd); } /* bne0b. */ void -OP_D_8 () +OP_D_8 (SIM_DESC sd, SIM_CPU *cpu) { uint32 addr; uint8 a = (GPR (OP[0]) & 0xFF); @@ -1203,12 +1206,12 @@ OP_D_8 () JMP (addr); } sign_flag = 0; /* Reset sign_flag. */ - trace_output_void (); + trace_output_void (sd); } /* beq0w. */ void -OP_E_8() +OP_E_8 (SIM_DESC sd, SIM_CPU *cpu) { uint32 addr; uint16 a = GPR (OP[0]); @@ -1224,12 +1227,12 @@ OP_E_8() JMP (addr); } sign_flag = 0; /* Reset sign_flag. */ - trace_output_void (); + trace_output_void (sd); } /* bne0w. */ void -OP_F_8 () +OP_F_8 (SIM_DESC sd, SIM_CPU *cpu) { uint32 addr; uint16 a = GPR (OP[0]); @@ -1245,401 +1248,401 @@ OP_F_8 () JMP (addr); } sign_flag = 0; /* Reset sign_flag. */ - trace_output_void (); + trace_output_void (sd); } /* jeq. */ void -OP_A0_C () +OP_A0_C (SIM_DESC sd, SIM_CPU *cpu) { - uint32 tmp; + uint32 tmp = 0; trace_input ("jeq", OP_REGP, OP_VOID, OP_VOID); if ((PSR_Z) == 1) { tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits. */ JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit. */ } - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* jne. */ void -OP_A1_C () +OP_A1_C (SIM_DESC sd, SIM_CPU *cpu) { - uint32 tmp; + uint32 tmp = 0; trace_input ("jne", OP_REGP, OP_VOID, OP_VOID); if ((PSR_Z) == 0) { tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits. */ JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit. */ } - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* jcs. */ void -OP_A2_C () +OP_A2_C (SIM_DESC sd, SIM_CPU *cpu) { - uint32 tmp; + uint32 tmp = 0; trace_input ("jcs", OP_REGP, OP_VOID, OP_VOID); if ((PSR_C) == 1) { tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ } - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* jcc. */ void -OP_A3_C () +OP_A3_C (SIM_DESC sd, SIM_CPU *cpu) { - uint32 tmp; + uint32 tmp = 0; trace_input ("jcc", OP_REGP, OP_VOID, OP_VOID); if ((PSR_C) == 0) { tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ } - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* jhi. */ void -OP_A4_C () +OP_A4_C (SIM_DESC sd, SIM_CPU *cpu) { - uint32 tmp; + uint32 tmp = 0; trace_input ("jhi", OP_REGP, OP_VOID, OP_VOID); if ((PSR_L) == 1) { tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ } - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* jls. */ void -OP_A5_C () +OP_A5_C (SIM_DESC sd, SIM_CPU *cpu) { - uint32 tmp; + uint32 tmp = 0; trace_input ("jls", OP_REGP, OP_VOID, OP_VOID); if ((PSR_L) == 0) { tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ } - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* jgt. */ void -OP_A6_C () +OP_A6_C (SIM_DESC sd, SIM_CPU *cpu) { - uint32 tmp; + uint32 tmp = 0; trace_input ("jgt", OP_REGP, OP_VOID, OP_VOID); if ((PSR_N) == 1) { tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ } - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* jle. */ void -OP_A7_C () +OP_A7_C (SIM_DESC sd, SIM_CPU *cpu) { - uint32 tmp; + uint32 tmp = 0; trace_input ("jle", OP_REGP, OP_VOID, OP_VOID); if ((PSR_N) == 0) { tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ } - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* jfs. */ void -OP_A8_C () +OP_A8_C (SIM_DESC sd, SIM_CPU *cpu) { - uint32 tmp; + uint32 tmp = 0; trace_input ("jfs", OP_REGP, OP_VOID, OP_VOID); if ((PSR_F) == 1) { tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ } - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* jfc. */ void -OP_A9_C () +OP_A9_C (SIM_DESC sd, SIM_CPU *cpu) { - uint32 tmp; + uint32 tmp = 0; trace_input ("jfc", OP_REGP, OP_VOID, OP_VOID); if ((PSR_F) == 0) { tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ } - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* jlo. */ void -OP_AA_C () +OP_AA_C (SIM_DESC sd, SIM_CPU *cpu) { - uint32 tmp; + uint32 tmp = 0; trace_input ("jlo", OP_REGP, OP_VOID, OP_VOID); if (((PSR_Z) == 0) & ((PSR_L) == 0)) { tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ } - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* jhs. */ void -OP_AB_C () +OP_AB_C (SIM_DESC sd, SIM_CPU *cpu) { - uint32 tmp; + uint32 tmp = 0; trace_input ("jhs", OP_REGP, OP_VOID, OP_VOID); if (((PSR_Z) == 1) | ((PSR_L) == 1)) { tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ } - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* jlt. */ void -OP_AC_C () +OP_AC_C (SIM_DESC sd, SIM_CPU *cpu) { - uint32 tmp; + uint32 tmp = 0; trace_input ("jlt", OP_REGP, OP_VOID, OP_VOID); if (((PSR_Z) == 0) & ((PSR_N) == 0)) { tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ } - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* jge. */ void -OP_AD_C () +OP_AD_C (SIM_DESC sd, SIM_CPU *cpu) { - uint32 tmp; + uint32 tmp = 0; trace_input ("jge", OP_REGP, OP_VOID, OP_VOID); if (((PSR_Z) == 1) | ((PSR_N) == 1)) { tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ } - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* jump. */ void -OP_AE_C () +OP_AE_C (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp; trace_input ("jump", OP_REGP, OP_VOID, OP_VOID); tmp = GPR32 (OP[0]) /*& 0x3fffff*/; /* Use only 0 - 22 bits */ JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* jusr. */ void -OP_AF_C () +OP_AF_C (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp; trace_input ("jusr", OP_REGP, OP_VOID, OP_VOID); tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ SET_PSR_U(1); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* seq. */ void -OP_80_C () +OP_80_C (SIM_DESC sd, SIM_CPU *cpu) { trace_input ("seq", OP_REG, OP_VOID, OP_VOID); if ((PSR_Z) == 1) SET_GPR (OP[0], 1); else SET_GPR (OP[0], 0); - trace_output_void (); + trace_output_void (sd); } /* sne. */ void -OP_81_C () +OP_81_C (SIM_DESC sd, SIM_CPU *cpu) { trace_input ("sne", OP_REG, OP_VOID, OP_VOID); if ((PSR_Z) == 0) SET_GPR (OP[0], 1); else SET_GPR (OP[0], 0); - trace_output_void (); + trace_output_void (sd); } /* scs. */ void -OP_82_C () +OP_82_C (SIM_DESC sd, SIM_CPU *cpu) { trace_input ("scs", OP_REG, OP_VOID, OP_VOID); if ((PSR_C) == 1) SET_GPR (OP[0], 1); else SET_GPR (OP[0], 0); - trace_output_void (); + trace_output_void (sd); } /* scc. */ void -OP_83_C () +OP_83_C (SIM_DESC sd, SIM_CPU *cpu) { trace_input ("scc", OP_REG, OP_VOID, OP_VOID); if ((PSR_C) == 0) SET_GPR (OP[0], 1); else SET_GPR (OP[0], 0); - trace_output_void (); + trace_output_void (sd); } /* shi. */ void -OP_84_C () +OP_84_C (SIM_DESC sd, SIM_CPU *cpu) { trace_input ("shi", OP_REG, OP_VOID, OP_VOID); if ((PSR_L) == 1) SET_GPR (OP[0], 1); else SET_GPR (OP[0], 0); - trace_output_void (); + trace_output_void (sd); } /* sls. */ void -OP_85_C () +OP_85_C (SIM_DESC sd, SIM_CPU *cpu) { trace_input ("sls", OP_REG, OP_VOID, OP_VOID); if ((PSR_L) == 0) SET_GPR (OP[0], 1); else SET_GPR (OP[0], 0); - trace_output_void (); + trace_output_void (sd); } /* sgt. */ void -OP_86_C () +OP_86_C (SIM_DESC sd, SIM_CPU *cpu) { trace_input ("sgt", OP_REG, OP_VOID, OP_VOID); if ((PSR_N) == 1) SET_GPR (OP[0], 1); else SET_GPR (OP[0], 0); - trace_output_void (); + trace_output_void (sd); } /* sle. */ void -OP_87_C () +OP_87_C (SIM_DESC sd, SIM_CPU *cpu) { trace_input ("sle", OP_REG, OP_VOID, OP_VOID); if ((PSR_N) == 0) SET_GPR (OP[0], 1); else SET_GPR (OP[0], 0); - trace_output_void (); + trace_output_void (sd); } /* sfs. */ void -OP_88_C () +OP_88_C (SIM_DESC sd, SIM_CPU *cpu) { trace_input ("sfs", OP_REG, OP_VOID, OP_VOID); if ((PSR_F) == 1) SET_GPR (OP[0], 1); else SET_GPR (OP[0], 0); - trace_output_void (); + trace_output_void (sd); } /* sfc. */ void -OP_89_C () +OP_89_C (SIM_DESC sd, SIM_CPU *cpu) { trace_input ("sfc", OP_REG, OP_VOID, OP_VOID); if ((PSR_F) == 0) SET_GPR (OP[0], 1); else SET_GPR (OP[0], 0); - trace_output_void (); + trace_output_void (sd); } /* slo. */ void -OP_8A_C () +OP_8A_C (SIM_DESC sd, SIM_CPU *cpu) { trace_input ("slo", OP_REG, OP_VOID, OP_VOID); if (((PSR_Z) == 0) & ((PSR_L) == 0)) SET_GPR (OP[0], 1); else SET_GPR (OP[0], 0); - trace_output_void (); + trace_output_void (sd); } /* shs. */ void -OP_8B_C () +OP_8B_C (SIM_DESC sd, SIM_CPU *cpu) { trace_input ("shs", OP_REG, OP_VOID, OP_VOID); if ( ((PSR_Z) == 1) | ((PSR_L) == 1)) SET_GPR (OP[0], 1); else SET_GPR (OP[0], 0); - trace_output_void (); + trace_output_void (sd); } /* slt. */ void -OP_8C_C () +OP_8C_C (SIM_DESC sd, SIM_CPU *cpu) { trace_input ("slt", OP_REG, OP_VOID, OP_VOID); if (((PSR_Z) == 0) & ((PSR_N) == 0)) SET_GPR (OP[0], 1); else SET_GPR (OP[0], 0); - trace_output_void (); + trace_output_void (sd); } /* sge. */ void -OP_8D_C () +OP_8D_C (SIM_DESC sd, SIM_CPU *cpu) { trace_input ("sge", OP_REG, OP_VOID, OP_VOID); if (((PSR_Z) == 1) | ((PSR_N) == 1)) SET_GPR (OP[0], 1); else SET_GPR (OP[0], 0); - trace_output_void (); + trace_output_void (sd); } /* cbitb. */ void -OP_D7_9 () +OP_D7_9 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = OP[0] & 0xff; uint32 addr = OP[1], tmp; @@ -1648,12 +1651,12 @@ OP_D7_9 () SET_PSR_F (tmp & (1 << a)); tmp = tmp & ~(1 << a); SB (addr, tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* cbitb. */ void -OP_107_14 () +OP_107_14 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = OP[0] & 0xff; uint32 addr = OP[1], tmp; @@ -1662,12 +1665,12 @@ OP_107_14 () SET_PSR_F (tmp & (1 << a)); tmp = tmp & ~(1 << a); SB (addr, tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* cbitb. */ void -OP_68_8 () +OP_68_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; uint32 addr = (GPR (OP[2])) + OP[1], tmp; @@ -1676,12 +1679,12 @@ OP_68_8 () SET_PSR_F (tmp & (1 << a)); tmp = tmp & ~(1 << a); SB (addr, tmp); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* cbitb. */ void -OP_1AA_A () +OP_1AA_A (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; @@ -1690,12 +1693,12 @@ OP_1AA_A () SET_PSR_F (tmp & (1 << a)); tmp = tmp & ~(1 << a); SB (addr, tmp); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* cbitb. */ void -OP_104_14 () +OP_104_14 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; uint32 addr = (GPR (OP[2])) + OP[1], tmp; @@ -1704,12 +1707,12 @@ OP_104_14 () SET_PSR_F (tmp & (1 << a)); tmp = tmp & ~(1 << a); SB (addr, tmp); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* cbitb. */ void -OP_D4_9 () +OP_D4_9 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; @@ -1718,12 +1721,12 @@ OP_D4_9 () SET_PSR_F (tmp & (1 << a)); tmp = tmp & ~(1 << a); SB (addr, tmp); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* cbitb. */ void -OP_D6_9 () +OP_D6_9 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; @@ -1732,13 +1735,13 @@ OP_D6_9 () SET_PSR_F (tmp & (1 << a)); tmp = tmp & ~(1 << a); SB (addr, tmp); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* cbitb. */ void -OP_105_14 () +OP_105_14 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; @@ -1747,12 +1750,12 @@ OP_105_14 () SET_PSR_F (tmp & (1 << a)); tmp = tmp & ~(1 << a); SB (addr, tmp); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* cbitb. */ void -OP_106_14 () +OP_106_14 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; @@ -1761,13 +1764,13 @@ OP_106_14 () SET_PSR_F (tmp & (1 << a)); tmp = tmp & ~(1 << a); SB (addr, tmp); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* cbitw. */ void -OP_6F_8 () +OP_6F_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; uint32 addr = OP[1], tmp; @@ -1776,12 +1779,12 @@ OP_6F_8 () SET_PSR_F (tmp & (1 << a)); tmp = tmp & ~(1 << a); SW (addr, tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* cbitw. */ void -OP_117_14 () +OP_117_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; uint32 addr = OP[1], tmp; @@ -1790,12 +1793,12 @@ OP_117_14 () SET_PSR_F (tmp & (1 << a)); tmp = tmp & ~(1 << a); SW (addr, tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* cbitw. */ void -OP_36_7 () +OP_36_7 (SIM_DESC sd, SIM_CPU *cpu) { uint32 addr; uint16 a = (OP[0]), tmp; @@ -1810,13 +1813,13 @@ OP_36_7 () SET_PSR_F (tmp & (1 << a)); tmp = tmp & ~(1 << a); SW (addr, tmp); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* cbitw. */ void -OP_1AB_A () +OP_1AB_A (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (OP[0]); uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; @@ -1825,12 +1828,12 @@ OP_1AB_A () SET_PSR_F (tmp & (1 << a)); tmp = tmp & ~(1 << a); SW (addr, tmp); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* cbitw. */ void -OP_114_14 () +OP_114_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (OP[0]); uint32 addr = (GPR (OP[2])) + OP[1], tmp; @@ -1839,13 +1842,13 @@ OP_114_14 () SET_PSR_F (tmp & (1 << a)); tmp = tmp & ~(1 << a); SW (addr, tmp); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* cbitw. */ void -OP_6E_8 () +OP_6E_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (OP[0]); uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; @@ -1854,12 +1857,12 @@ OP_6E_8 () SET_PSR_F (tmp & (1 << a)); tmp = tmp & ~(1 << a); SW (addr, tmp); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* cbitw. */ void -OP_69_8 () +OP_69_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (OP[0]); uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; @@ -1868,13 +1871,13 @@ OP_69_8 () SET_PSR_F (tmp & (1 << a)); tmp = tmp & ~(1 << a); SW (addr, tmp); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* cbitw. */ void -OP_115_14 () +OP_115_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (OP[0]); uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; @@ -1883,12 +1886,12 @@ OP_115_14 () SET_PSR_F (tmp & (1 << a)); tmp = tmp & ~(1 << a); SW (addr, tmp); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* cbitw. */ void -OP_116_14 () +OP_116_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (OP[0]); uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; @@ -1897,12 +1900,12 @@ OP_116_14 () SET_PSR_F (tmp & (1 << a)); tmp = tmp & ~(1 << a); SW (addr, tmp); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* sbitb. */ void -OP_E7_9 () +OP_E7_9 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = OP[0] & 0xff; uint32 addr = OP[1], tmp; @@ -1911,12 +1914,12 @@ OP_E7_9 () SET_PSR_F (tmp & (1 << a)); tmp = tmp | (1 << a); SB (addr, tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* sbitb. */ void -OP_10B_14 () +OP_10B_14 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = OP[0] & 0xff; uint32 addr = OP[1], tmp; @@ -1925,12 +1928,12 @@ OP_10B_14 () SET_PSR_F (tmp & (1 << a)); tmp = tmp | (1 << a); SB (addr, tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* sbitb. */ void -OP_70_8 () +OP_70_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = OP[0] & 0xff; uint32 addr = (GPR (OP[2])) + OP[1], tmp; @@ -1939,12 +1942,12 @@ OP_70_8 () SET_PSR_F (tmp & (1 << a)); tmp = tmp | (1 << a); SB (addr, tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* sbitb. */ void -OP_1CA_A () +OP_1CA_A (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = OP[0] & 0xff; uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; @@ -1953,12 +1956,12 @@ OP_1CA_A () SET_PSR_F (tmp & (1 << a)); tmp = tmp | (1 << a); SB (addr, tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* sbitb. */ void -OP_108_14 () +OP_108_14 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = OP[0] & 0xff; uint32 addr = (GPR (OP[2])) + OP[1], tmp; @@ -1967,13 +1970,13 @@ OP_108_14 () SET_PSR_F (tmp & (1 << a)); tmp = tmp | (1 << a); SB (addr, tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* sbitb. */ void -OP_E4_9 () +OP_E4_9 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = OP[0] & 0xff; uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; @@ -1982,12 +1985,12 @@ OP_E4_9 () SET_PSR_F (tmp & (1 << a)); tmp = tmp | (1 << a); SB (addr, tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* sbitb. */ void -OP_E6_9 () +OP_E6_9 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = OP[0] & 0xff; uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; @@ -1996,13 +1999,13 @@ OP_E6_9 () SET_PSR_F (tmp & (1 << a)); tmp = tmp | (1 << a); SB (addr, tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* sbitb. */ void -OP_109_14 () +OP_109_14 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = OP[0] & 0xff; uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; @@ -2011,13 +2014,13 @@ OP_109_14 () SET_PSR_F (tmp & (1 << a)); tmp = tmp | (1 << a); SB (addr, tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* sbitb. */ void -OP_10A_14 () +OP_10A_14 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = OP[0] & 0xff; uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; @@ -2026,13 +2029,13 @@ OP_10A_14 () SET_PSR_F (tmp & (1 << a)); tmp = tmp | (1 << a); SB (addr, tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* sbitw. */ void -OP_77_8 () +OP_77_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; uint32 addr = OP[1], tmp; @@ -2041,12 +2044,12 @@ OP_77_8 () SET_PSR_F (tmp & (1 << a)); tmp = tmp | (1 << a); SW (addr, tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* sbitw. */ void -OP_11B_14 () +OP_11B_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; uint32 addr = OP[1], tmp; @@ -2055,12 +2058,12 @@ OP_11B_14 () SET_PSR_F (tmp & (1 << a)); tmp = tmp | (1 << a); SW (addr, tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* sbitw. */ void -OP_3A_7 () +OP_3A_7 (SIM_DESC sd, SIM_CPU *cpu) { uint32 addr; uint16 a = (OP[0]), tmp; @@ -2075,12 +2078,12 @@ OP_3A_7 () SET_PSR_F (tmp & (1 << a)); tmp = tmp | (1 << a); SW (addr, tmp); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* sbitw. */ void -OP_1CB_A () +OP_1CB_A (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (OP[0]); uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; @@ -2089,12 +2092,12 @@ OP_1CB_A () SET_PSR_F (tmp & (1 << a)); tmp = tmp | (1 << a); SW (addr, tmp); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* sbitw. */ void -OP_118_14 () +OP_118_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (OP[0]); uint32 addr = (GPR (OP[2])) + OP[1], tmp; @@ -2103,12 +2106,12 @@ OP_118_14 () SET_PSR_F (tmp & (1 << a)); tmp = tmp | (1 << a); SW (addr, tmp); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* sbitw. */ void -OP_76_8 () +OP_76_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (OP[0]); uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; @@ -2117,12 +2120,12 @@ OP_76_8 () SET_PSR_F (tmp & (1 << a)); tmp = tmp | (1 << a); SW (addr, tmp); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* sbitw. */ void -OP_71_8 () +OP_71_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (OP[0]); uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; @@ -2131,12 +2134,12 @@ OP_71_8 () SET_PSR_F (tmp & (1 << a)); tmp = tmp | (1 << a); SW (addr, tmp); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* sbitw. */ void -OP_119_14 () +OP_119_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (OP[0]); uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; @@ -2145,12 +2148,12 @@ OP_119_14 () SET_PSR_F (tmp & (1 << a)); tmp = tmp | (1 << a); SW (addr, tmp); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* sbitw. */ void -OP_11A_14 () +OP_11A_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (OP[0]); uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; @@ -2159,147 +2162,147 @@ OP_11A_14 () SET_PSR_F (tmp & (1 << a)); tmp = tmp | (1 << a); SW (addr, tmp); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* tbitb. */ void -OP_F7_9 () +OP_F7_9 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = OP[0] & 0xff; uint32 addr = OP[1], tmp; trace_input ("tbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID); tmp = RB (addr); SET_PSR_F (tmp & (1 << a)); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* tbitb. */ void -OP_10F_14 () +OP_10F_14 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = OP[0] & 0xff; uint32 addr = OP[1], tmp; trace_input ("tbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID); tmp = RB (addr); SET_PSR_F (tmp & (1 << a)); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* tbitb. */ void -OP_78_8 () +OP_78_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; uint32 addr = (GPR (OP[2])) + OP[1], tmp; trace_input ("tbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID); tmp = RB (addr); SET_PSR_F (tmp & (1 << a)); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* tbitb. */ void -OP_1EA_A () +OP_1EA_A (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID); tmp = RB (addr); SET_PSR_F (tmp & (1 << a)); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* tbitb. */ void -OP_10C_14 () +OP_10C_14 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; uint32 addr = (GPR (OP[2])) + OP[1], tmp; trace_input ("tbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID); tmp = RB (addr); SET_PSR_F (tmp & (1 << a)); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* tbitb. */ void -OP_F4_9 () +OP_F4_9 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID); tmp = RB (addr); SET_PSR_F (tmp & (1 << a)); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* tbitb. */ void -OP_F6_9 () +OP_F6_9 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; trace_input ("tbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID); tmp = RB (addr); SET_PSR_F (tmp & (1 << a)); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* tbitb. */ void -OP_10D_14 () +OP_10D_14 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; trace_input ("tbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID); tmp = RB (addr); SET_PSR_F (tmp & (1 << a)); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* tbitb. */ void -OP_10E_14 () +OP_10E_14 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID); tmp = RB (addr); SET_PSR_F (tmp & (1 << a)); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* tbitw. */ void -OP_7F_8 () +OP_7F_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; uint32 addr = OP[1], tmp; trace_input ("tbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID); tmp = RW (addr); SET_PSR_F (tmp & (1 << a)); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* tbitw. */ void -OP_11F_14 () +OP_11F_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; uint32 addr = OP[1], tmp; trace_input ("tbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID); tmp = RW (addr); SET_PSR_F (tmp & (1 << a)); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* tbitw. */ void -OP_3E_7 () +OP_3E_7 (SIM_DESC sd, SIM_CPU *cpu) { uint32 addr; uint16 a = (OP[0]), tmp; @@ -2312,109 +2315,109 @@ OP_3E_7 () tmp = RW (addr); SET_PSR_F (tmp & (1 << a)); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* tbitw. */ void -OP_1EB_A () +OP_1EB_A (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (OP[0]); uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID); tmp = RW (addr); SET_PSR_F (tmp & (1 << a)); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* tbitw. */ void -OP_11C_14 () +OP_11C_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (OP[0]); uint32 addr = (GPR (OP[2])) + OP[1], tmp; trace_input ("tbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID); tmp = RW (addr); SET_PSR_F (tmp & (1 << a)); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* tbitw. */ void -OP_7E_8 () +OP_7E_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (OP[0]); uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID); tmp = RW (addr); SET_PSR_F (tmp & (1 << a)); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* tbitw. */ void -OP_79_8 () +OP_79_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (OP[0]); uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; trace_input ("tbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID); tmp = RW (addr); SET_PSR_F (tmp & (1 << a)); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* tbitw. */ void -OP_11D_14 () +OP_11D_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (OP[0]); uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; trace_input ("tbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID); tmp = RW (addr); SET_PSR_F (tmp & (1 << a)); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* tbitw. */ void -OP_11E_14 () +OP_11E_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (OP[0]); uint32 addr = (GPR32 (OP[2])) + OP[1], tmp; trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID); tmp = RW (addr); SET_PSR_F (tmp & (1 << a)); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* tbit. */ void -OP_6_8 () +OP_6_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; uint16 b = (GPR (OP[1])); trace_input ("tbit", OP_CONSTANT4, OP_REG, OP_VOID); SET_PSR_F (b & (1 << a)); - trace_output_16 (b); + trace_output_16 (sd, b); } /* tbit. */ void -OP_7_8 () +OP_7_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = GPR (OP[0]); uint16 b = (GPR (OP[1])); trace_input ("tbit", OP_REG, OP_REG, OP_VOID); SET_PSR_F (b & (1 << a)); - trace_output_16 (b); + trace_output_16 (sd, b); } /* cmpb. */ void -OP_50_8 () +OP_50_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xFF; uint8 b = (GPR (OP[1])) & 0xFF; @@ -2422,12 +2425,12 @@ OP_50_8 () SET_PSR_Z (a == b); SET_PSR_N ((int8)a > (int8)b); SET_PSR_L (a > b); - trace_output_flag (); + trace_output_flag (sd); } /* cmpb. */ void -OP_50B_C () +OP_50B_C (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xFF; uint8 b = (GPR (OP[1])) & 0xFF; @@ -2435,12 +2438,12 @@ OP_50B_C () SET_PSR_Z (a == b); SET_PSR_N ((int8)a > (int8)b); SET_PSR_L (a > b); - trace_output_flag (); + trace_output_flag (sd); } /* cmpb. */ void -OP_51_8 () +OP_51_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (GPR (OP[0])) & 0xFF; uint8 b = (GPR (OP[1])) & 0xFF; @@ -2448,12 +2451,12 @@ OP_51_8 () SET_PSR_Z (a == b); SET_PSR_N ((int8)a > (int8)b); SET_PSR_L (a > b); - trace_output_flag (); + trace_output_flag (sd); } /* cmpw. */ void -OP_52_8 () +OP_52_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (OP[0]); uint16 b = GPR (OP[1]); @@ -2461,12 +2464,12 @@ OP_52_8 () SET_PSR_Z (a == b); SET_PSR_N ((int16)a > (int16)b); SET_PSR_L (a > b); - trace_output_flag (); + trace_output_flag (sd); } /* cmpw. */ void -OP_52B_C () +OP_52B_C (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (OP[0]); uint16 b = GPR (OP[1]); @@ -2474,12 +2477,12 @@ OP_52B_C () SET_PSR_Z (a == b); SET_PSR_N ((int16)a > (int16)b); SET_PSR_L (a > b); - trace_output_flag (); + trace_output_flag (sd); } /* cmpw. */ void -OP_53_8 () +OP_53_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = GPR (OP[0]) ; uint16 b = GPR (OP[1]) ; @@ -2487,12 +2490,12 @@ OP_53_8 () SET_PSR_Z (a == b); SET_PSR_N ((int16)a > (int16)b); SET_PSR_L (a > b); - trace_output_flag (); + trace_output_flag (sd); } /* cmpd. */ void -OP_56_8 () +OP_56_8 (SIM_DESC sd, SIM_CPU *cpu) { uint32 a = (OP[0]); uint32 b = GPR32 (OP[1]); @@ -2500,12 +2503,12 @@ OP_56_8 () SET_PSR_Z (a == b); SET_PSR_N ((int32)a > (int32)b); SET_PSR_L (a > b); - trace_output_flag (); + trace_output_flag (sd); } /* cmpd. */ void -OP_56B_C () +OP_56B_C (SIM_DESC sd, SIM_CPU *cpu) { uint32 a = (SEXT16(OP[0])); uint32 b = GPR32 (OP[1]); @@ -2513,12 +2516,12 @@ OP_56B_C () SET_PSR_Z (a == b); SET_PSR_N ((int32)a > (int32)b); SET_PSR_L (a > b); - trace_output_flag (); + trace_output_flag (sd); } /* cmpd. */ void -OP_57_8 () +OP_57_8 (SIM_DESC sd, SIM_CPU *cpu) { uint32 a = GPR32 (OP[0]) ; uint32 b = GPR32 (OP[1]) ; @@ -2526,12 +2529,12 @@ OP_57_8 () SET_PSR_Z (a == b); SET_PSR_N ((int32)a > (int32)b); SET_PSR_L (a > b); - trace_output_flag (); + trace_output_flag (sd); } /* cmpd. */ void -OP_9_C() +OP_9_C (SIM_DESC sd, SIM_CPU *cpu) { uint32 a = (OP[0]); uint32 b = GPR32 (OP[1]); @@ -2539,178 +2542,176 @@ OP_9_C() SET_PSR_Z (a == b); SET_PSR_N ((int32)a > (int32)b); SET_PSR_L (a > b); - trace_output_flag (); + trace_output_flag (sd); } /* movb. */ void -OP_58_8 () +OP_58_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 tmp = OP[0] & 0xFF; - trace_input ("movb", OP_CONSTANT4, OP_REG, OP_VOID); uint16 a = (GPR (OP[1])) & 0xFF00; + trace_input ("movb", OP_CONSTANT4, OP_REG, OP_VOID); SET_GPR (OP[1], (a | tmp)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* movb. */ void -OP_58B_C () +OP_58B_C (SIM_DESC sd, SIM_CPU *cpu) { uint8 tmp = OP[0] & 0xFF; - trace_input ("movb", OP_CONSTANT16, OP_REG, OP_VOID); uint16 a = (GPR (OP[1])) & 0xFF00; + trace_input ("movb", OP_CONSTANT16, OP_REG, OP_VOID); SET_GPR (OP[1], (a | tmp)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* movb. */ void -OP_59_8 () +OP_59_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 tmp = (GPR (OP[0])) & 0xFF; - trace_input ("movb", OP_REG, OP_REG, OP_VOID); uint16 a = (GPR (OP[1])) & 0xFF00; + trace_input ("movb", OP_REG, OP_REG, OP_VOID); SET_GPR (OP[1], (a | tmp)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* movw. */ void -OP_5A_8 () +OP_5A_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 tmp = OP[0]; trace_input ("movw", OP_CONSTANT4_1, OP_REG, OP_VOID); SET_GPR (OP[1], (tmp & 0xffff)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* movw. */ void -OP_5AB_C () +OP_5AB_C (SIM_DESC sd, SIM_CPU *cpu) { int16 tmp = OP[0]; trace_input ("movw", OP_CONSTANT16, OP_REG, OP_VOID); SET_GPR (OP[1], (tmp & 0xffff)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* movw. */ void -OP_5B_8 () +OP_5B_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 tmp = GPR (OP[0]); - trace_input ("movw", OP_REG, OP_REGP, OP_VOID); uint32 a = GPR32 (OP[1]); + trace_input ("movw", OP_REG, OP_REGP, OP_VOID); a = (a & 0xffff0000) | tmp; SET_GPR32 (OP[1], a); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* movxb. */ void -OP_5C_8 () +OP_5C_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 tmp = (GPR (OP[0])) & 0xFF; trace_input ("movxb", OP_REG, OP_REG, OP_VOID); SET_GPR (OP[1], ((SEXT8(tmp)) & 0xffff)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* movzb. */ void -OP_5D_8 () +OP_5D_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 tmp = (GPR (OP[0])) & 0xFF; trace_input ("movzb", OP_REG, OP_REG, OP_VOID); SET_GPR (OP[1], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* movxw. */ void -OP_5E_8 () +OP_5E_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 tmp = GPR (OP[0]); trace_input ("movxw", OP_REG, OP_REGP, OP_VOID); SET_GPR32 (OP[1], SEXT16(tmp)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* movzw. */ void -OP_5F_8 () +OP_5F_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 tmp = GPR (OP[0]); trace_input ("movzw", OP_REG, OP_REGP, OP_VOID); SET_GPR32 (OP[1], (tmp & 0x0000FFFF)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* movd. */ void -OP_54_8 () +OP_54_8 (SIM_DESC sd, SIM_CPU *cpu) { int32 tmp = OP[0]; trace_input ("movd", OP_CONSTANT4, OP_REGP, OP_VOID); SET_GPR32 (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* movd. */ void -OP_54B_C () +OP_54B_C (SIM_DESC sd, SIM_CPU *cpu) { int32 tmp = SEXT16(OP[0]); trace_input ("movd", OP_CONSTANT16, OP_REGP, OP_VOID); SET_GPR32 (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* movd. */ void -OP_55_8 () +OP_55_8 (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp = GPR32 (OP[0]); trace_input ("movd", OP_REGP, OP_REGP, OP_VOID); SET_GPR32 (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* movd. */ void -OP_5_8 () +OP_5_8 (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp = OP[0]; trace_input ("movd", OP_CONSTANT20, OP_REGP, OP_VOID); SET_GPR32 (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* movd. */ void -OP_7_C () +OP_7_C (SIM_DESC sd, SIM_CPU *cpu) { int32 tmp = OP[0]; trace_input ("movd", OP_CONSTANT32, OP_REGP, OP_VOID); SET_GPR32 (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* loadm. */ void -OP_14_D () +OP_14_D (SIM_DESC sd, SIM_CPU *cpu) { uint32 addr = GPR (0); uint16 count = OP[0], reg = 2, tmp; trace_input ("loadm", OP_CONSTANT4, OP_VOID, OP_VOID); if ((addr & 1)) { - State.exception = SIG_CR16_BUS; - State.pc_changed = 1; /* Don't increment the PC. */ - trace_output_void (); - return; + trace_output_void (sd); + EXCEPTION (SIM_SIGBUS); } while (count) @@ -2724,23 +2725,21 @@ OP_14_D () }; SET_GPR (0, addr); - trace_output_void (); + trace_output_void (sd); } /* loadmp. */ void -OP_15_D () +OP_15_D (SIM_DESC sd, SIM_CPU *cpu) { uint32 addr = GPR32 (0); uint16 count = OP[0], reg = 2, tmp; trace_input ("loadm", OP_CONSTANT4, OP_VOID, OP_VOID); if ((addr & 1)) { - State.exception = SIG_CR16_BUS; - State.pc_changed = 1; /* Don't increment the PC. */ - trace_output_void (); - return; + trace_output_void (sd); + EXCEPTION (SIM_SIGBUS); } while (count) @@ -2754,13 +2753,13 @@ OP_15_D () }; SET_GPR32 (0, addr); - trace_output_void (); + trace_output_void (sd); } /* loadb. */ void -OP_88_8 () +OP_88_8 (SIM_DESC sd, SIM_CPU *cpu) { /* loadb ABS20, REG * ADDR = zext24(abs20) | remap (ie 0xF00000) @@ -2776,12 +2775,12 @@ OP_88_8 () if (addr > 0xEFFFF) addr |= 0xF00000; tmp = (RB (addr)); SET_GPR (OP[1], (a | tmp)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadb. */ void -OP_127_14 () +OP_127_14 (SIM_DESC sd, SIM_CPU *cpu) { /* loadb ABS24, REG * ADDR = abs24 @@ -2792,12 +2791,12 @@ OP_127_14 () trace_input ("loadb", OP_ABS24, OP_REG, OP_VOID); tmp = (RB (addr)); SET_GPR (OP[1], (a | tmp)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadb. */ void -OP_45_7 () +OP_45_7 (SIM_DESC sd, SIM_CPU *cpu) { /* loadb [Rindex]ABS20 REG * ADDR = Rindex + zext24(disp20) @@ -2814,13 +2813,13 @@ OP_45_7 () tmp = (RB (addr)); SET_GPR (OP[2], (a | tmp)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadb. */ void -OP_B_4 () +OP_B_4 (SIM_DESC sd, SIM_CPU *cpu) { /* loadb DIPS4(REGP) REG * ADDR = RPBASE + zext24(DISP4) @@ -2830,12 +2829,12 @@ OP_B_4 () trace_input ("loadb", OP_RP_BASE_DISP4, OP_REG, OP_VOID); tmp = (RB (addr)); SET_GPR (OP[2], (a | tmp)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadb. */ void -OP_BE_8 () +OP_BE_8 (SIM_DESC sd, SIM_CPU *cpu) { /* loadb [Rindex]disp0(RPbasex) REG * ADDR = Rpbasex + Rindex @@ -2854,12 +2853,12 @@ OP_BE_8 () tmp = (RB (addr)); SET_GPR (OP[3], (a | tmp)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadb. */ void -OP_219_A () +OP_219_A (SIM_DESC sd, SIM_CPU *cpu) { /* loadb [Rindex]disp14(RPbasex) REG * ADDR = Rpbasex + Rindex + zext24(disp14) @@ -2878,13 +2877,13 @@ OP_219_A () trace_input ("loadb", OP_RP_INDEX_DISP14, OP_REG, OP_VOID); tmp = (RB (addr)); SET_GPR (OP[3], (a | tmp)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadb. */ void -OP_184_14 () +OP_184_14 (SIM_DESC sd, SIM_CPU *cpu) { /* loadb DISPE20(REG) REG * zext24(Rbase) + zext24(dispe20) @@ -2895,12 +2894,12 @@ OP_184_14 () trace_input ("loadb", OP_R_BASE_DISPE20, OP_REG, OP_VOID); tmp = (RB (addr)); SET_GPR (OP[2], (a | tmp)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadb. */ void -OP_124_14 () +OP_124_14 (SIM_DESC sd, SIM_CPU *cpu) { /* loadb DISP20(REG) REG * ADDR = zext24(Rbase) + zext24(disp20) @@ -2911,12 +2910,12 @@ OP_124_14 () trace_input ("loadb", OP_R_BASE_DISP20, OP_REG, OP_VOID); tmp = (RB (addr)); SET_GPR (OP[2], (a | tmp)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadb. */ void -OP_BF_8 () +OP_BF_8 (SIM_DESC sd, SIM_CPU *cpu) { /* loadb disp16(REGP) REG * ADDR = RPbase + zext24(disp16) @@ -2927,12 +2926,12 @@ OP_BF_8 () trace_input ("loadb", OP_RP_BASE_DISP16, OP_REG, OP_VOID); tmp = (RB (addr)); SET_GPR (OP[2], (a | tmp)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadb. */ void -OP_125_14 () +OP_125_14 (SIM_DESC sd, SIM_CPU *cpu) { /* loadb disp20(REGP) REG * ADDR = RPbase + zext24(disp20) @@ -2942,13 +2941,13 @@ OP_125_14 () trace_input ("loadb", OP_RP_BASE_DISP20, OP_REG, OP_VOID); tmp = (RB (addr)); SET_GPR (OP[2], (a | tmp)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadb. */ void -OP_185_14 () +OP_185_14 (SIM_DESC sd, SIM_CPU *cpu) { /* loadb -disp20(REGP) REG * ADDR = RPbase + zext24(-disp20) @@ -2958,12 +2957,12 @@ OP_185_14 () trace_input ("loadb", OP_RP_BASE_DISPE20, OP_REG, OP_VOID); tmp = (RB (addr)); SET_GPR (OP[2], (a | tmp)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadb. */ void -OP_126_14 () +OP_126_14 (SIM_DESC sd, SIM_CPU *cpu) { /* loadb [Rindex]disp20(RPbasexb) REG * ADDR = RPbasex + Rindex + zext24(disp20) @@ -2982,13 +2981,13 @@ OP_126_14 () tmp = (RB (addr)); SET_GPR (OP[3], (a | tmp)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadw. */ void -OP_89_8 () +OP_89_8 (SIM_DESC sd, SIM_CPU *cpu) { /* loadw ABS20, REG * ADDR = zext24(abs20) | remap @@ -3004,13 +3003,13 @@ OP_89_8 () if (addr > 0xEFFFF) addr |= 0xF00000; tmp = (RW (addr)); SET_GPR (OP[1], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadw. */ void -OP_12F_14 () +OP_12F_14 (SIM_DESC sd, SIM_CPU *cpu) { /* loadw ABS24, REG * ADDR = abs24 @@ -3020,12 +3019,12 @@ OP_12F_14 () trace_input ("loadw", OP_ABS24, OP_REG, OP_VOID); tmp = (RW (addr)); SET_GPR (OP[1], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadw. */ void -OP_47_7 () +OP_47_7 (SIM_DESC sd, SIM_CPU *cpu) { /* loadw [Rindex]ABS20 REG * ADDR = Rindex + zext24(disp20) @@ -3042,13 +3041,13 @@ OP_47_7 () tmp = (RW (addr)); SET_GPR (OP[2], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadw. */ void -OP_9_4 () +OP_9_4 (SIM_DESC sd, SIM_CPU *cpu) { /* loadw DIPS4(REGP) REGP * ADDR = RPBASE + zext24(DISP4) @@ -3066,13 +3065,13 @@ OP_9_4 () else SET_GPR (OP[2], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadw. */ void -OP_9E_8 () +OP_9E_8 (SIM_DESC sd, SIM_CPU *cpu) { /* loadw [Rindex]disp0(RPbasex) REG * ADDR = Rpbasex + Rindex @@ -3091,13 +3090,13 @@ OP_9E_8 () tmp = RW (addr); SET_GPR (OP[3], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadw. */ void -OP_21B_A () +OP_21B_A (SIM_DESC sd, SIM_CPU *cpu) { /* loadw [Rindex]disp14(RPbasex) REG * ADDR = Rpbasex + Rindex + zext24(disp14) @@ -3115,12 +3114,12 @@ OP_21B_A () tmp = (RW (addr)); SET_GPR (OP[3], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadw. */ void -OP_18C_14 () +OP_18C_14 (SIM_DESC sd, SIM_CPU *cpu) { /* loadw dispe20(REG) REGP * REGP = [DISPE20+[REG]] */ @@ -3138,13 +3137,13 @@ OP_18C_14 () else SET_GPR (OP[2], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadw. */ void -OP_12C_14 () +OP_12C_14 (SIM_DESC sd, SIM_CPU *cpu) { /* loadw DISP20(REG) REGP * ADDR = zext24(Rbase) + zext24(disp20) @@ -3163,12 +3162,12 @@ OP_12C_14 () else SET_GPR (OP[2], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadw. */ void -OP_9F_8 () +OP_9F_8 (SIM_DESC sd, SIM_CPU *cpu) { /* loadw disp16(REGP) REGP * ADDR = RPbase + zext24(disp16) @@ -3186,12 +3185,12 @@ OP_9F_8 () else SET_GPR (OP[2], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadw. */ void -OP_12D_14 () +OP_12D_14 (SIM_DESC sd, SIM_CPU *cpu) { /* loadw disp20(REGP) REGP * ADDR = RPbase + zext24(disp20) @@ -3209,12 +3208,12 @@ OP_12D_14 () else SET_GPR (OP[2], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadw. */ void -OP_18D_14 () +OP_18D_14 (SIM_DESC sd, SIM_CPU *cpu) { /* loadw -disp20(REGP) REG * ADDR = RPbase + zext24(-disp20) @@ -3233,13 +3232,13 @@ OP_18D_14 () else SET_GPR (OP[2], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadw. */ void -OP_12E_14 () +OP_12E_14 (SIM_DESC sd, SIM_CPU *cpu) { /* loadw [Rindex]disp20(RPbasexb) REG * ADDR = RPbasex + Rindex + zext24(disp20) @@ -3256,13 +3255,13 @@ OP_12E_14 () tmp = (RW (addr)); SET_GPR (OP[3], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* loadd. */ void -OP_87_8 () +OP_87_8 (SIM_DESC sd, SIM_CPU *cpu) { /* loadd ABS20, REGP * ADDR = zext24(abs20) | remap @@ -3279,12 +3278,12 @@ OP_87_8 () tmp = RLW (addr); tmp = ((tmp << 16) & 0xffff)| ((tmp >> 16) & 0xffff); SET_GPR32 (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* loadd. */ void -OP_12B_14 () +OP_12B_14 (SIM_DESC sd, SIM_CPU *cpu) { /* loadd ABS24, REGP * ADDR = abs24 @@ -3296,13 +3295,13 @@ OP_12B_14 () tmp = RLW (addr); tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); SET_GPR32 (OP[1],tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* loadd. */ void -OP_46_7 () +OP_46_7 (SIM_DESC sd, SIM_CPU *cpu) { /* loadd [Rindex]ABS20 REGP * ADDR = Rindex + zext24(disp20) @@ -3319,13 +3318,13 @@ OP_46_7 () tmp = RLW (addr); tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); SET_GPR32 (OP[2], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* loadd. */ void -OP_A_4 () +OP_A_4 (SIM_DESC sd, SIM_CPU *cpu) { /* loadd dips4(regp) REGP * ADDR = Rpbase + zext24(disp4) @@ -3336,13 +3335,13 @@ OP_A_4 () tmp = RLW (addr); tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); SET_GPR32 (OP[2], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* loadd. */ void -OP_AE_8 () +OP_AE_8 (SIM_DESC sd, SIM_CPU *cpu) { /* loadd [Rindex]disp0(RPbasex) REGP * ADDR = Rpbasex + Rindex @@ -3359,13 +3358,13 @@ OP_AE_8 () tmp = RLW (addr); tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); SET_GPR32 (OP[3], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* loadd. */ void -OP_21A_A () +OP_21A_A (SIM_DESC sd, SIM_CPU *cpu) { /* loadd [Rindex]disp14(RPbasex) REGP * ADDR = Rpbasex + Rindex + zext24(disp14) @@ -3382,13 +3381,13 @@ OP_21A_A () tmp = RLW (addr); tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); SET_GPR (OP[3],tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* loadd. */ void -OP_188_14 () +OP_188_14 (SIM_DESC sd, SIM_CPU *cpu) { /* loadd dispe20(REG) REG * zext24(Rbase) + zext24(dispe20) @@ -3399,13 +3398,13 @@ OP_188_14 () tmp = RLW (addr); tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); SET_GPR32 (OP[2], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* loadd. */ void -OP_128_14 () +OP_128_14 (SIM_DESC sd, SIM_CPU *cpu) { /* loadd DISP20(REG) REG * ADDR = zext24(Rbase) + zext24(disp20) @@ -3416,12 +3415,12 @@ OP_128_14 () tmp = RLW (addr); tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); SET_GPR32 (OP[2], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* loadd. */ void -OP_AF_8 () +OP_AF_8 (SIM_DESC sd, SIM_CPU *cpu) { /* loadd disp16(REGP) REGP * ADDR = RPbase + zext24(disp16) @@ -3431,13 +3430,13 @@ OP_AF_8 () tmp = RLW (addr); tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); SET_GPR32 (OP[2], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* loadd. */ void -OP_129_14 () +OP_129_14 (SIM_DESC sd, SIM_CPU *cpu) { /* loadd disp20(REGP) REGP * ADDR = RPbase + zext24(disp20) @@ -3447,12 +3446,12 @@ OP_129_14 () tmp = RLW (addr); tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); SET_GPR32 (OP[2], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* loadd. */ void -OP_189_14 () +OP_189_14 (SIM_DESC sd, SIM_CPU *cpu) { /* loadd -disp20(REGP) REGP * ADDR = RPbase + zext24(-disp20) @@ -3463,12 +3462,12 @@ OP_189_14 () tmp = RLW (addr); tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); SET_GPR32 (OP[2], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* loadd. */ void -OP_12A_14 () +OP_12A_14 (SIM_DESC sd, SIM_CPU *cpu) { /* loadd [Rindex]disp20(RPbasexb) REGP * ADDR = RPbasex + Rindex + zext24(disp20) @@ -3485,13 +3484,13 @@ OP_12A_14 () tmp = RLW (addr); tmp = ((tmp << 16) & 0xffff)| ((tmp >> 16) & 0xffff); SET_GPR32 (OP[3], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* storb. */ void -OP_C8_8 () +OP_C8_8 (SIM_DESC sd, SIM_CPU *cpu) { /* storb REG, ABS20 * ADDR = zext24(abs20) | remap @@ -3505,12 +3504,12 @@ OP_C8_8 () uint32 addr = OP[1]; trace_input ("storb", OP_REG, OP_ABS20_OUTPUT, OP_VOID); SB (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storb. */ void -OP_137_14 () +OP_137_14 (SIM_DESC sd, SIM_CPU *cpu) { /* storb REG, ABS24 * ADDR = abs24 @@ -3520,12 +3519,12 @@ OP_137_14 () uint32 addr = OP[1]; trace_input ("storb", OP_REG, OP_ABS24_OUTPUT, OP_VOID); SB (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storb. */ void -OP_65_7 () +OP_65_7 (SIM_DESC sd, SIM_CPU *cpu) { /* storb REG, [Rindex]ABS20 * ADDR = Rindex + zext24(disp20) @@ -3541,27 +3540,27 @@ OP_65_7 () addr = (GPR32 (13)) + OP[2]; SB (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storb. */ void -OP_F_4 () +OP_F_4 (SIM_DESC sd, SIM_CPU *cpu) { /* storb REG, DIPS4(REGP) * ADDR = RPBASE + zext24(DISP4) * [ADDR] = REG. */ uint16 a = ((GPR (OP[0])) & 0xff); + uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("storb", OP_REG, OP_RP_BASE_DISPE4, OP_VOID); - uint32 addr = (GPR32 (OP[2])) + OP[1]; SB (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storb. */ void -OP_FE_8 () +OP_FE_8 (SIM_DESC sd, SIM_CPU *cpu) { /* storb [Rindex]disp0(RPbasex) REG * ADDR = Rpbasex + Rindex @@ -3577,140 +3576,140 @@ OP_FE_8 () addr = (GPR32 (13)) + (GPR32 (OP[3])) + OP[2]; SB (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storb. */ void -OP_319_A () +OP_319_A (SIM_DESC sd, SIM_CPU *cpu) { /* storb REG, [Rindex]disp14(RPbasex) * ADDR = Rpbasex + Rindex + zext24(disp14) * [ADDR] = REGR */ uint8 a = ((GPR (OP[0])) & 0xff); - trace_input ("storb", OP_REG, OP_RP_INDEX_DISP14, OP_VOID); uint32 addr = (GPR32 (OP[2])) + OP[1]; + trace_input ("storb", OP_REG, OP_RP_INDEX_DISP14, OP_VOID); SB (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storb. */ void -OP_194_14 () +OP_194_14 (SIM_DESC sd, SIM_CPU *cpu) { /* storb REG, DISPE20(REG) * zext24(Rbase) + zext24(dispe20) * [ADDR] = REG */ uint8 a = ((GPR (OP[0])) & 0xff); - trace_input ("storb", OP_REG, OP_R_BASE_DISPE20, OP_VOID); uint32 addr = OP[1] + (GPR (OP[2])); + trace_input ("storb", OP_REG, OP_R_BASE_DISPE20, OP_VOID); SB (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storb. */ void -OP_134_14 () +OP_134_14 (SIM_DESC sd, SIM_CPU *cpu) { /* storb REG, DISP20(REG) * ADDR = zext24(Rbase) + zext24(disp20) * [ADDR] = REG */ uint8 a = (GPR (OP[0]) & 0xff); + uint32 addr = OP[1] + (GPR (OP[2])); trace_input ("storb", OP_REG, OP_R_BASE_DISPS20, OP_VOID); - uint32 addr = OP[1] + (GPR (OP[2])); SB (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storb. */ void -OP_FF_8 () +OP_FF_8 (SIM_DESC sd, SIM_CPU *cpu) { /* storb REG, disp16(REGP) * ADDR = RPbase + zext24(disp16) * [ADDR] = REGP */ uint8 a = ((GPR (OP[0])) & 0xff); - trace_input ("storb", OP_REG, OP_RP_BASE_DISP16, OP_VOID); uint32 addr = (GPR32 (OP[2])) + OP[1]; + trace_input ("storb", OP_REG, OP_RP_BASE_DISP16, OP_VOID); SB (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storb. */ void -OP_135_14 () +OP_135_14 (SIM_DESC sd, SIM_CPU *cpu) { /* storb REG, disp20(REGP) * ADDR = RPbase + zext24(disp20) * [ADDR] = REGP */ uint8 a = ((GPR (OP[0])) & 0xff); - trace_input ("storb", OP_REG, OP_RP_BASE_DISPS20, OP_VOID); uint32 addr = (GPR32 (OP[2])) + OP[1]; + trace_input ("storb", OP_REG, OP_RP_BASE_DISPS20, OP_VOID); SB (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storb. */ void -OP_195_14 () +OP_195_14 (SIM_DESC sd, SIM_CPU *cpu) { /* storb REG, -disp20(REGP) * ADDR = RPbase + zext24(-disp20) * [ADDR] = REGP */ uint8 a = (GPR (OP[0]) & 0xff); - trace_input ("storb", OP_REG, OP_RP_BASE_DISPE20, OP_VOID); uint32 addr = (GPR32 (OP[2])) + OP[1]; + trace_input ("storb", OP_REG, OP_RP_BASE_DISPE20, OP_VOID); SB (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storb. */ void -OP_136_14 () +OP_136_14 (SIM_DESC sd, SIM_CPU *cpu) { /* storb REG, [Rindex]disp20(RPbase) * ADDR = RPbasex + Rindex + zext24(disp20) * [ADDR] = REGP */ uint8 a = (GPR (OP[0])) & 0xff; - trace_input ("storb", OP_REG, OP_RP_INDEX_DISPS20, OP_VOID); uint32 addr = (GPR32 (OP[2])) + OP[1]; + trace_input ("storb", OP_REG, OP_RP_INDEX_DISPS20, OP_VOID); SB (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* STR_IMM instructions. */ /* storb . */ void -OP_81_8 () +OP_81_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; - trace_input ("storb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID); uint32 addr = OP[1]; + trace_input ("storb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID); SB (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storb. */ void -OP_123_14 () +OP_123_14 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; - trace_input ("storb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID); uint32 addr = OP[1]; + trace_input ("storb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID); SB (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storb. */ void -OP_42_7 () +OP_42_7 (SIM_DESC sd, SIM_CPU *cpu) { uint32 addr; uint8 a = (OP[0]) & 0xff; @@ -3722,101 +3721,101 @@ OP_42_7 () addr = (GPR32 (13)) + OP[2]; SB (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storb. */ void -OP_218_A () +OP_218_A (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; - trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISP14, OP_VOID); uint32 addr = (GPR32 (OP[2])) + OP[1]; + trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISP14, OP_VOID); SB (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storb. */ void -OP_82_8 () +OP_82_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; - trace_input ("storb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID); uint32 addr = (GPR32 (OP[2])) + OP[1]; + trace_input ("storb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID); SB (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storb. */ void -OP_120_14 () +OP_120_14 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; - trace_input ("storb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID); uint32 addr = (GPR (OP[2])) + OP[1]; + trace_input ("storb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID); SB (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storb. */ void -OP_83_8 () +OP_83_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; - trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID); uint32 addr = (GPR32 (OP[2])) + OP[1]; + trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID); SB (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storb. */ void -OP_121_14 () +OP_121_14 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; - trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID); uint32 addr = (GPR32 (OP[2])) + OP[1]; + trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID); SB (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storb. */ void -OP_122_14 () +OP_122_14 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (OP[0]) & 0xff; - trace_input ("storb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID); uint32 addr = (GPR32 (OP[2])) + OP[1]; + trace_input ("storb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID); SB (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* endif for STR_IMM. */ /* storw . */ void -OP_C9_8 () +OP_C9_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = GPR (OP[0]); - trace_input ("storw", OP_REG, OP_ABS20_OUTPUT, OP_VOID); uint32 addr = OP[1]; + trace_input ("storw", OP_REG, OP_ABS20_OUTPUT, OP_VOID); SW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storw. */ void -OP_13F_14 () +OP_13F_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = GPR (OP[0]); - trace_input ("storw", OP_REG, OP_ABS24_OUTPUT, OP_VOID); uint32 addr = OP[1]; + trace_input ("storw", OP_REG, OP_ABS24_OUTPUT, OP_VOID); SW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storw. */ void -OP_67_7 () +OP_67_7 (SIM_DESC sd, SIM_CPU *cpu) { uint32 addr; uint16 a = GPR (OP[0]); @@ -3828,135 +3827,135 @@ OP_67_7 () addr = (GPR32 (13)) + OP[2]; SW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storw. */ void -OP_D_4 () +OP_D_4 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (GPR (OP[0])); + uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("storw", OP_REGP, OP_RP_BASE_DISPE4, OP_VOID); - uint32 addr = (GPR32 (OP[2])) + OP[1]; SW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storw. */ void -OP_DE_8 () +OP_DE_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = GPR (OP[0]); - trace_input ("storw", OP_REG, OP_RP_INDEX_DISP0, OP_VOID); uint32 addr = (GPR32 (OP[2])) + OP[1]; + trace_input ("storw", OP_REG, OP_RP_INDEX_DISP0, OP_VOID); SW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storw. */ void -OP_31B_A () +OP_31B_A (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = GPR (OP[0]); - trace_input ("storw", OP_REG, OP_RP_INDEX_DISP14, OP_VOID); uint32 addr = (GPR32 (OP[2])) + OP[1]; + trace_input ("storw", OP_REG, OP_RP_INDEX_DISP14, OP_VOID); SW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storw. */ void -OP_19C_14 () +OP_19C_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (GPR (OP[0])); + uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("storw", OP_REGP, OP_RP_BASE_DISPE20, OP_VOID); - uint32 addr = (GPR32 (OP[2])) + OP[1]; SW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storw. */ void -OP_13C_14 () +OP_13C_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (GPR (OP[0])); + uint32 addr = (GPR (OP[2])) + OP[1]; trace_input ("storw", OP_REG, OP_R_BASE_DISPS20, OP_VOID); - uint32 addr = (GPR (OP[2])) + OP[1]; SW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storw. */ void -OP_DF_8 () +OP_DF_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (GPR (OP[0])); + uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("storw", OP_REG, OP_RP_BASE_DISP16, OP_VOID); - uint32 addr = (GPR32 (OP[2])) + OP[1]; SW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storw. */ void -OP_13D_14 () +OP_13D_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (GPR (OP[0])); + uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("storw", OP_REG, OP_RP_BASE_DISPS20, OP_VOID); - uint32 addr = (GPR32 (OP[2])) + OP[1]; SW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storw. */ void -OP_19D_14 () +OP_19D_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (GPR (OP[0])); + uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("storw", OP_REG, OP_RP_BASE_DISPE20, OP_VOID); - uint32 addr = (GPR32 (OP[2])) + OP[1]; SW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storw. */ void -OP_13E_14 () +OP_13E_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (GPR (OP[0])); + uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("storw", OP_REG, OP_RP_INDEX_DISPS20, OP_VOID); - uint32 addr = (GPR32 (OP[2])) + OP[1]; SW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* STORE-w IMM instruction *****/ /* storw . */ void -OP_C1_8 () +OP_C1_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; + uint32 addr = OP[1]; trace_input ("storw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID); - uint32 addr = OP[1]; SW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storw. */ void -OP_133_14 () +OP_133_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; + uint32 addr = OP[1]; trace_input ("storw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID); - uint32 addr = OP[1]; SW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storw. */ void -OP_62_7 () +OP_62_7 (SIM_DESC sd, SIM_CPU *cpu) { uint32 addr; uint16 a = OP[0]; @@ -3968,102 +3967,102 @@ OP_62_7 () addr = (GPR32 (13)) + OP[2]; SW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storw. */ void -OP_318_A () +OP_318_A (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; + uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISP14, OP_VOID); - uint32 addr = (GPR32 (OP[2])) + OP[1]; SW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storw. */ void -OP_C2_8 () +OP_C2_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; + uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("storw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID); - uint32 addr = (GPR32 (OP[2])) + OP[1]; SW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storw. */ void -OP_130_14 () +OP_130_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; + uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("storw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID); - uint32 addr = (GPR32 (OP[2])) + OP[1]; SW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storw. */ void -OP_C3_8 () +OP_C3_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; + uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID); - uint32 addr = (GPR32 (OP[2])) + OP[1]; SW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storw. */ void -OP_131_14 () +OP_131_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; + uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID); - uint32 addr = (GPR32 (OP[2])) + OP[1]; SW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* storw. */ void -OP_132_14 () +OP_132_14 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; + uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("storw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID); - uint32 addr = (GPR32 (OP[2])) + OP[1]; SW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* stord. */ void -OP_C7_8 () +OP_C7_8 (SIM_DESC sd, SIM_CPU *cpu) { uint32 a = GPR32 (OP[0]); + uint32 addr = OP[1]; trace_input ("stord", OP_REGP, OP_ABS20_OUTPUT, OP_VOID); - uint32 addr = OP[1]; SLW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* stord. */ void -OP_13B_14 () +OP_13B_14 (SIM_DESC sd, SIM_CPU *cpu) { uint32 a = GPR32 (OP[0]); + uint32 addr = OP[1]; trace_input ("stord", OP_REGP, OP_ABS24_OUTPUT, OP_VOID); - uint32 addr = OP[1]; SLW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* stord. */ void -OP_66_7 () +OP_66_7 (SIM_DESC sd, SIM_CPU *cpu) { uint32 addr, a = GPR32 (OP[0]); trace_input ("stord", OP_REGP, OP_R_INDEX8_ABS20, OP_VOID); @@ -4074,111 +4073,111 @@ OP_66_7 () addr = (GPR32 (13)) + OP[2]; SLW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* stord. */ void -OP_E_4 () +OP_E_4 (SIM_DESC sd, SIM_CPU *cpu) { uint32 a = GPR32 (OP[0]); + uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("stord", OP_REGP, OP_RP_BASE_DISPE4, OP_VOID); - uint32 addr = (GPR32 (OP[2])) + OP[1]; SLW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* stord. */ void -OP_EE_8 () +OP_EE_8 (SIM_DESC sd, SIM_CPU *cpu) { uint32 a = GPR32 (OP[0]); + uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("stord", OP_REGP, OP_RP_INDEX_DISP0, OP_VOID); - uint32 addr = (GPR32 (OP[2])) + OP[1]; SLW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* stord. */ void -OP_31A_A () +OP_31A_A (SIM_DESC sd, SIM_CPU *cpu) { uint32 a = GPR32 (OP[0]); + uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("stord", OP_REGP, OP_RP_INDEX_DISP14, OP_VOID); - uint32 addr = (GPR32 (OP[2])) + OP[1]; SLW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* stord. */ void -OP_198_14 () +OP_198_14 (SIM_DESC sd, SIM_CPU *cpu) { uint32 a = GPR32 (OP[0]); + uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("stord", OP_REGP, OP_R_BASE_DISPE20, OP_VOID); - uint32 addr = (GPR32 (OP[2])) + OP[1]; SLW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* stord. */ void -OP_138_14 () +OP_138_14 (SIM_DESC sd, SIM_CPU *cpu) { uint32 a = GPR32 (OP[0]); + uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("stord", OP_REGP, OP_R_BASE_DISPS20, OP_VOID); - uint32 addr = (GPR32 (OP[2])) + OP[1]; SLW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* stord. */ void -OP_EF_8 () +OP_EF_8 (SIM_DESC sd, SIM_CPU *cpu) { uint32 a = GPR32 (OP[0]); + uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("stord", OP_REGP, OP_RP_BASE_DISP16, OP_VOID); - uint32 addr = (GPR32 (OP[2])) + OP[1]; SLW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* stord. */ void -OP_139_14 () +OP_139_14 (SIM_DESC sd, SIM_CPU *cpu) { uint32 a = GPR32 (OP[0]); + uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("stord", OP_REGP, OP_RP_BASE_DISPS20, OP_VOID); - uint32 addr = (GPR32 (OP[2])) + OP[1]; SLW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* stord. */ void -OP_199_14 () +OP_199_14 (SIM_DESC sd, SIM_CPU *cpu) { uint32 a = GPR32 (OP[0]); + uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("stord", OP_REGP, OP_RP_BASE_DISPE20, OP_VOID); - uint32 addr = (GPR32 (OP[2])) + OP[1]; SLW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* stord. */ void -OP_13A_14 () +OP_13A_14 (SIM_DESC sd, SIM_CPU *cpu) { uint32 a = GPR32 (OP[0]); + uint32 addr = (GPR32 (OP[2])) + OP[1]; trace_input ("stord", OP_REGP, OP_RP_INDEX_DISPS20, OP_VOID); - uint32 addr = (GPR32 (OP[2])) + OP[1]; SLW (addr, a); - trace_output_32 (addr); + trace_output_32 (sd, addr); } /* macqu. */ void -OP_14D_14 () +OP_14D_14 (SIM_DESC sd, SIM_CPU *cpu) { int32 tmp; int16 src1, src2; @@ -4188,12 +4187,12 @@ OP_14D_14 () tmp = src1 * src2; /*REVISIT FOR SATURATION and Q FORMAT. */ SET_GPR32 (OP[2], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* macuw. */ void -OP_14E_14 () +OP_14E_14 (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp; uint16 src1, src2; @@ -4203,12 +4202,12 @@ OP_14E_14 () tmp = src1 * src2; /*REVISIT FOR SATURATION. */ SET_GPR32 (OP[2], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* macsw. */ void -OP_14F_14 () +OP_14F_14 (SIM_DESC sd, SIM_CPU *cpu) { int32 tmp; int16 src1, src2; @@ -4218,13 +4217,13 @@ OP_14F_14 () tmp = src1 * src2; /*REVISIT FOR SATURATION. */ SET_GPR32 (OP[2], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* mulb. */ void -OP_64_8 () +OP_64_8 (SIM_DESC sd, SIM_CPU *cpu) { int16 tmp; int8 a = (OP[0]) & 0xff; @@ -4232,38 +4231,38 @@ OP_64_8 () trace_input ("mulb", OP_CONSTANT4_1, OP_REG, OP_VOID); tmp = (a * b) & 0xff; SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* mulb. */ void -OP_64B_C () +OP_64B_C (SIM_DESC sd, SIM_CPU *cpu) { int16 tmp; int8 a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff; trace_input ("mulb", OP_CONSTANT4, OP_REG, OP_VOID); tmp = (a * b) & 0xff; SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* mulb. */ void -OP_65_8 () +OP_65_8 (SIM_DESC sd, SIM_CPU *cpu) { int16 tmp; int8 a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff; trace_input ("mulb", OP_REG, OP_REG, OP_VOID); tmp = (a * b) & 0xff; SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* mulw. */ void -OP_66_8 () +OP_66_8 (SIM_DESC sd, SIM_CPU *cpu) { int32 tmp; uint16 a = OP[0]; @@ -4271,80 +4270,79 @@ OP_66_8 () trace_input ("mulw", OP_CONSTANT4_1, OP_REG, OP_VOID); tmp = (a * b) & 0xffff; SET_GPR (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* mulw. */ void -OP_66B_C () +OP_66B_C (SIM_DESC sd, SIM_CPU *cpu) { int32 tmp; int16 a = OP[0], b = (GPR (OP[1])); trace_input ("mulw", OP_CONSTANT4, OP_REG, OP_VOID); tmp = (a * b) & 0xffff; SET_GPR (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* mulw. */ void -OP_67_8 () +OP_67_8 (SIM_DESC sd, SIM_CPU *cpu) { int32 tmp; int16 a = (GPR (OP[0])), b = (GPR (OP[1])); trace_input ("mulw", OP_REG, OP_REG, OP_VOID); tmp = (a * b) & 0xffff; SET_GPR (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* mulsb. */ void -OP_B_8 () +OP_B_8 (SIM_DESC sd, SIM_CPU *cpu) { int16 tmp; int8 a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff; trace_input ("mulsb", OP_REG, OP_REG, OP_VOID); tmp = a * b; SET_GPR (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* mulsw. */ void -OP_62_8 () +OP_62_8 (SIM_DESC sd, SIM_CPU *cpu) { int32 tmp; int16 a = (GPR (OP[0])), b = (GPR (OP[1])); trace_input ("mulsw", OP_REG, OP_REGP, OP_VOID); tmp = a * b; SET_GPR32 (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* muluw. */ void -OP_63_8 () +OP_63_8 (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp; uint16 a = (GPR (OP[0])), b = (GPR (OP[1])); trace_input ("muluw", OP_REG, OP_REGP, OP_VOID); tmp = a * b; SET_GPR32 (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* nop. */ void -OP_2C00_10 () +OP_2C00_10 (SIM_DESC sd, SIM_CPU *cpu) { trace_input ("nop", OP_VOID, OP_VOID, OP_VOID); #if 0 - State.exception = SIGTRAP; ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */ switch (State.ins_type) { @@ -4353,83 +4351,83 @@ OP_2C00_10 () break; } - + EXCEPTION (SIM_SIGTRAP); #endif - trace_output_void (); + trace_output_void (sd); } /* orb. */ void -OP_24_8 () +OP_24_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff; trace_input ("orb", OP_CONSTANT4, OP_REG, OP_VOID); tmp = a | b; SET_GPR (OP[1], ((GPR (OP[1]) | tmp))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* orb. */ void -OP_24B_C () +OP_24B_C (SIM_DESC sd, SIM_CPU *cpu) { uint8 tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff; trace_input ("orb", OP_CONSTANT16, OP_REG, OP_VOID); tmp = a | b; SET_GPR (OP[1], ((GPR (OP[1]) | tmp))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* orb. */ void -OP_25_8 () +OP_25_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff; trace_input ("orb", OP_REG, OP_REG, OP_VOID); tmp = a | b; SET_GPR (OP[1], ((GPR (OP[1]) | tmp))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* orw. */ void -OP_26_8 () +OP_26_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 tmp, a = (OP[0]), b = (GPR (OP[1])); trace_input ("orw", OP_CONSTANT4, OP_REG, OP_VOID); tmp = a | b; SET_GPR (OP[1], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* orw. */ void -OP_26B_C () +OP_26B_C (SIM_DESC sd, SIM_CPU *cpu) { uint16 tmp, a = (OP[0]), b = (GPR (OP[1])); trace_input ("orw", OP_CONSTANT16, OP_REG, OP_VOID); tmp = a | b; SET_GPR (OP[1], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* orw. */ void -OP_27_8 () +OP_27_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 tmp, a = (GPR (OP[0])), b = (GPR (OP[1])); trace_input ("orw", OP_REG, OP_REG, OP_VOID); tmp = a | b; SET_GPR (OP[1], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* lshb. */ void -OP_13_9 () +OP_13_9 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; uint16 tmp, b = (GPR (OP[1])) & 0xFF; @@ -4444,12 +4442,12 @@ OP_13_9 () sign_flag = 0; /* Reset sign_flag. */ SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* lshb. */ void -OP_44_8 () +OP_44_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (GPR (OP[0])) & 0xff; uint16 tmp, b = (GPR (OP[1])) & 0xFF; @@ -4470,12 +4468,12 @@ OP_44_8 () sign_flag = 0; /* Reset sign_flag. */ SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* lshw. */ void -OP_46_8 () +OP_46_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 tmp, b = GPR (OP[1]); int16 a = GPR (OP[0]); @@ -4496,12 +4494,12 @@ OP_46_8 () sign_flag = 0; /* Reset sign_flag. */ SET_GPR (OP[1], (tmp & 0xffff)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* lshw. */ void -OP_49_8 () +OP_49_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 tmp, b = GPR (OP[1]); uint16 a = OP[0]; @@ -4515,12 +4513,12 @@ OP_49_8 () sign_flag = 0; /* Reset sign_flag. */ SET_GPR (OP[1], (tmp & 0xffff)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* lshd. */ void -OP_25_7 () +OP_25_7 (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp, b = GPR32 (OP[1]); uint16 a = OP[0]; @@ -4535,12 +4533,12 @@ OP_25_7 () sign_flag = 0; /* Reset sign flag. */ SET_GPR32 (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* lshd. */ void -OP_47_8 () +OP_47_8 (SIM_DESC sd, SIM_CPU *cpu) { uint32 tmp, b = GPR32 (OP[1]); uint16 a = GPR (OP[0]); @@ -4561,12 +4559,12 @@ OP_47_8 () sign_flag = 0; /* Reset sign flag. */ SET_GPR32 (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* ashub. */ void -OP_80_9 () +OP_80_9 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; int8 tmp, b = (GPR (OP[1])) & 0xFF; @@ -4581,12 +4579,12 @@ OP_80_9 () sign_flag = 0; /* Reset sign flag. */ SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xff00))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* ashub. */ void -OP_81_9 () +OP_81_9 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; int8 tmp, b = (GPR (OP[1])) & 0xFF; @@ -4601,13 +4599,13 @@ OP_81_9 () sign_flag = 0; /* Reset sign flag. */ SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* ashub. */ void -OP_41_8 () +OP_41_8 (SIM_DESC sd, SIM_CPU *cpu) { int16 a = (GPR (OP[0])); int8 tmp, b = (GPR (OP[1])) & 0xFF; @@ -4630,13 +4628,13 @@ OP_41_8 () sign_flag = 0; /* Reset sign flag. */ SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* ashuw. */ void -OP_42_8 () +OP_42_8 (SIM_DESC sd, SIM_CPU *cpu) { int16 tmp, b = GPR (OP[1]); uint16 a = OP[0]; @@ -4651,12 +4649,12 @@ OP_42_8 () sign_flag = 0; /* Reset sign flag. */ SET_GPR (OP[1], (tmp & 0xffff)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* ashuw. */ void -OP_43_8 () +OP_43_8 (SIM_DESC sd, SIM_CPU *cpu) { int16 tmp, b = GPR (OP[1]); uint16 a = OP[0]; @@ -4670,12 +4668,12 @@ OP_43_8 () sign_flag = 0; /* Reset sign flag. */ SET_GPR (OP[1], (tmp & 0xffff)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* ashuw. */ void -OP_45_8 () +OP_45_8 (SIM_DESC sd, SIM_CPU *cpu) { int16 tmp; int16 a = GPR (OP[0]), b = GPR (OP[1]); @@ -4697,12 +4695,12 @@ OP_45_8 () sign_flag = 0; /* Reset sign flag. */ SET_GPR (OP[1], (tmp & 0xffff)); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* ashud. */ void -OP_26_7 () +OP_26_7 (SIM_DESC sd, SIM_CPU *cpu) { int32 tmp,b = GPR32 (OP[1]); uint32 a = OP[0]; @@ -4716,12 +4714,12 @@ OP_26_7 () sign_flag = 0; /* Reset sign flag. */ SET_GPR32 (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* ashud. */ void -OP_27_7 () +OP_27_7 (SIM_DESC sd, SIM_CPU *cpu) { int32 tmp; int32 a = OP[0], b = GPR32 (OP[1]); @@ -4735,12 +4733,12 @@ OP_27_7 () sign_flag = 0; /* Reset sign flag. */ SET_GPR32 (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* ashud. */ void -OP_48_8 () +OP_48_8 (SIM_DESC sd, SIM_CPU *cpu) { int32 tmp; int32 a = GPR32 (OP[0]), b = GPR32 (OP[1]); @@ -4761,23 +4759,21 @@ OP_48_8 () sign_flag = 0; /* Reset sign flag. */ SET_GPR32 (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* storm. */ void -OP_16_D () +OP_16_D (SIM_DESC sd, SIM_CPU *cpu) { uint32 addr = GPR (1); uint16 count = OP[0], reg = 2; trace_input ("storm", OP_CONSTANT4, OP_VOID, OP_VOID); if ((addr & 1)) { - State.exception = SIG_CR16_BUS; - State.pc_changed = 1; /* Don't increment the PC. */ - trace_output_void (); - return; + trace_output_void (sd); + EXCEPTION (SIM_SIGBUS); } while (count) @@ -4791,23 +4787,21 @@ OP_16_D () SET_GPR (1, addr); - trace_output_void (); + trace_output_void (sd); } /* stormp. */ void -OP_17_D () +OP_17_D (SIM_DESC sd, SIM_CPU *cpu) { uint32 addr = GPR32 (6); uint16 count = OP[0], reg = 2; trace_input ("stormp", OP_CONSTANT4, OP_VOID, OP_VOID); if ((addr & 1)) { - State.exception = SIG_CR16_BUS; - State.pc_changed = 1; /* Don't increment the PC. */ - trace_output_void (); - return; + trace_output_void (sd); + EXCEPTION (SIM_SIGBUS); } while (count) @@ -4820,12 +4814,12 @@ OP_17_D () }; SET_GPR32 (6, addr); - trace_output_void (); + trace_output_void (sd); } /* subb. */ void -OP_38_8 () +OP_38_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = OP[0]; uint8 b = (GPR (OP[1])) & 0xff; @@ -4836,12 +4830,12 @@ OP_38_8 () SET_PSR_C (tmp > 0xff); SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* subb. */ void -OP_38B_C () +OP_38B_C (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = OP[0] & 0xFF; uint8 b = (GPR (OP[1])) & 0xFF; @@ -4852,12 +4846,12 @@ OP_38B_C () SET_PSR_C (tmp > 0xff); SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* subb. */ void -OP_39_8 () +OP_39_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = (GPR (OP[0])) & 0xFF; uint8 b = (GPR (OP[1])) & 0xFF; @@ -4868,12 +4862,12 @@ OP_39_8 () SET_PSR_C (tmp > 0xff); SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* subw. */ void -OP_3A_8 () +OP_3A_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; uint16 b = GPR (OP[1]); @@ -4884,12 +4878,12 @@ OP_3A_8 () SET_PSR_C (tmp > 0xffff); SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); SET_GPR (OP[1], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* subw. */ void -OP_3AB_C () +OP_3AB_C (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; uint16 b = GPR (OP[1]); @@ -4900,12 +4894,12 @@ OP_3AB_C () SET_PSR_C (tmp > 0xffff); SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); SET_GPR (OP[1], tmp & 0xffff); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* subw. */ void -OP_3B_8 () +OP_3B_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = GPR (OP[0]); uint16 b = GPR (OP[1]); @@ -4916,12 +4910,12 @@ OP_3B_8 () SET_PSR_C (tmp > 0xffff); SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); SET_GPR (OP[1], tmp & 0xffff); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* subcb. */ void -OP_3C_8 () +OP_3C_8 (SIM_DESC sd, SIM_CPU *cpu) { uint8 a = OP[0]; uint8 b = (GPR (OP[1])) & 0xff; @@ -4934,12 +4928,12 @@ OP_3C_8 () SET_PSR_C (tmp > 0xff); SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); SET_GPR (OP[1], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* subcb. */ void -OP_3CB_C () +OP_3CB_C (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0]; uint16 b = (GPR (OP[1])) & 0xff; @@ -4952,12 +4946,12 @@ OP_3CB_C () SET_PSR_C (tmp > 0xff); SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); SET_GPR (OP[1], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* subcb. */ void -OP_3D_8 () +OP_3D_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (GPR (OP[0])) & 0xff; uint16 b = (GPR (OP[1])) & 0xff; @@ -4969,12 +4963,12 @@ OP_3D_8 () SET_PSR_C (tmp > 0xff); SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); SET_GPR (OP[1], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* subcw. */ void -OP_3E_8 () +OP_3E_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = OP[0], b = (GPR (OP[1])); uint16 tmp1 = a + (PSR_C); @@ -4985,12 +4979,12 @@ OP_3E_8 () SET_PSR_C (tmp > 0xffff); SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); SET_GPR (OP[1], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* subcw. */ void -OP_3EB_C () +OP_3EB_C (SIM_DESC sd, SIM_CPU *cpu) { int16 a = OP[0]; uint16 b = GPR (OP[1]); @@ -5002,12 +4996,12 @@ OP_3EB_C () SET_PSR_C (tmp > 0xffff); SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); SET_GPR (OP[1], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* subcw. */ void -OP_3F_8 () +OP_3F_8 (SIM_DESC sd, SIM_CPU *cpu) { uint16 a = (GPR (OP[0])), b = (GPR (OP[1])); uint16 tmp1 = a + (PSR_C); @@ -5018,12 +5012,12 @@ OP_3F_8 () SET_PSR_C (tmp > 0xffff); SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); SET_GPR (OP[1], tmp); - trace_output_16 (tmp); + trace_output_16 (sd, tmp); } /* subd. */ void -OP_3_C () +OP_3_C (SIM_DESC sd, SIM_CPU *cpu) { int32 a = OP[0]; uint32 b = GPR32 (OP[1]); @@ -5035,12 +5029,12 @@ OP_3_C () SET_PSR_F (((a & 0x80000000) != (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000))); SET_GPR32 (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* subd. */ void -OP_14C_14 () +OP_14C_14 (SIM_DESC sd, SIM_CPU *cpu) { uint32 a = GPR32 (OP[0]); uint32 b = GPR32 (OP[1]); @@ -5052,13 +5046,16 @@ OP_14C_14 () SET_PSR_F (((a & 0x80000000) != (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000))); SET_GPR32 (OP[1], tmp); - trace_output_32 (tmp); + trace_output_32 (sd, tmp); } /* excp. */ void -OP_C_C () +OP_C_C (SIM_DESC sd, SIM_CPU *cpu) { + host_callback *cb = STATE_CALLBACK (sd); + uint32 tmp; + uint16 a; trace_input ("excp", OP_CONSTANT4, OP_VOID, OP_VOID); switch (OP[0]) { @@ -5082,25 +5079,25 @@ OP_C_C () if (first_time) { first_time = 0; - (*cr16_callback->printf_filtered) (cr16_callback, "Trap # PC "); + sim_io_printf (sd, "Trap # PC "); for (i = 0; i < 16; i++) - (*cr16_callback->printf_filtered) (cr16_callback, " %sr%d", (i > 9) ? "" : " ", i); - (*cr16_callback->printf_filtered) (cr16_callback, " a0 a1 f0 f1 c\n"); + sim_io_printf (sd, " %sr%d", (i > 9) ? "" : " ", i); + sim_io_printf (sd, " a0 a1 f0 f1 c\n"); } - (*cr16_callback->printf_filtered) (cr16_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC); + sim_io_printf (sd, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC); for (i = 0; i < 16; i++) - (*cr16_callback->printf_filtered) (cr16_callback, " %.4x", (int) GPR (i)); + sim_io_printf (sd, " %.4x", (int) GPR (i)); for (i = 0; i < 2; i++) - (*cr16_callback->printf_filtered) (cr16_callback, " %.2x%.8lx", + sim_io_printf (sd, " %.2x%.8lx", ((int)(ACC (i) >> 32) & 0xff), ((unsigned long) ACC (i)) & 0xffffffff); - (*cr16_callback->printf_filtered) (cr16_callback, " %d %d %d\n", + sim_io_printf (sd, " %d %d %d\n", PSR_F != 0, PSR_F != 0, PSR_C != 0); - (*cr16_callback->flush_stdout) (cr16_callback); + sim_io_flush_stdout (sd); break; } #endif @@ -5126,7 +5123,7 @@ OP_C_C () /* Turn a pointer in a register into a pointer into real memory. */ -#define MEMPTR(x) ((char *)(dmem_addr(x))) +#define MEMPTR(x) sim_core_trans_addr (sd, cpu, read_map, x) switch (FUNC) { @@ -5135,7 +5132,7 @@ OP_C_C () case TARGET_SYS_fork: trace_input ("", OP_VOID, OP_VOID, OP_VOID); RETVAL (fork ()); - trace_output_16 (result); + trace_output_16 (sd, result); break; #endif @@ -5143,15 +5140,15 @@ OP_C_C () case TARGET_SYS_getpid: trace_input ("", OP_VOID, OP_VOID, OP_VOID); RETVAL (getpid ()); - trace_output_16 (result); + trace_output_16 (sd, result); break; case TARGET_SYS_kill: trace_input ("", OP_REG, OP_REG, OP_VOID); if (PARM1 == getpid ()) { - trace_output_void (); - State.exception = PARM2; + trace_output_void (sd); + EXCEPTION (PARM2); } else { @@ -5261,15 +5258,15 @@ OP_C_C () if (os_sig == -1) { - trace_output_void (); - (*cr16_callback->printf_filtered) (cr16_callback, "Unknown signal %d\n", PARM2); - (*cr16_callback->flush_stdout) (cr16_callback); - State.exception = SIGILL; + trace_output_void (sd); + sim_io_printf (sd, "Unknown signal %d\n", PARM2); + sim_io_flush_stdout (sd); + EXCEPTION (SIM_SIGILL); } else { RETVAL (kill (PARM1, PARM2)); - trace_output_16 (result); + trace_output_16 (sd, result); } } break; @@ -5279,7 +5276,7 @@ OP_C_C () trace_input ("", OP_VOID, OP_VOID, OP_VOID); RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2<<16|PARM3), (char **)MEMPTR (PARM4))); - trace_output_16 (result); + trace_output_16 (sd, result); break; #endif @@ -5287,7 +5284,7 @@ OP_C_C () case TARGET_SYS_execv: trace_input ("", OP_VOID, OP_VOID, OP_VOID); RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL)); - trace_output_16 (result); + trace_output_16 (sd, result); break; #endif @@ -5303,7 +5300,7 @@ OP_C_C () SW (buf, host_fd[0]); buf += sizeof(uint16); SW (buf, host_fd[1]); - trace_output_16 (result); + trace_output_16 (sd, result); } break; #endif @@ -5316,7 +5313,7 @@ OP_C_C () RETVAL (wait (&status)); if (PARM1) SW (PARM1, status); - trace_output_16 (result); + trace_output_16 (sd, result); } break; #endif @@ -5324,80 +5321,77 @@ OP_C_C () case TARGET_SYS_getpid: trace_input ("", OP_VOID, OP_VOID, OP_VOID); RETVAL (1); - trace_output_16 (result); + trace_output_16 (sd, result); break; case TARGET_SYS_kill: trace_input ("", OP_REG, OP_REG, OP_VOID); - trace_output_void (); - State.exception = PARM2; + trace_output_void (sd); + EXCEPTION (PARM2); break; #endif case TARGET_SYS_read: trace_input ("", OP_REG, OP_MEMREF, OP_REG); - RETVAL (cr16_callback->read (cr16_callback, PARM1, - MEMPTR (((unsigned long)PARM3 << 16) - |((unsigned long)PARM2)), PARM4)); - trace_output_16 (result); + RETVAL (cb->read (cb, PARM1, + MEMPTR (((unsigned long)PARM3 << 16) + | ((unsigned long)PARM2)), PARM4)); + trace_output_16 (sd, result); break; case TARGET_SYS_write: trace_input ("", OP_REG, OP_MEMREF, OP_REG); - RETVAL ((int)cr16_callback->write (cr16_callback, PARM1, - MEMPTR (((unsigned long)PARM3 << 16) | PARM2), PARM4)); - trace_output_16 (result); + RETVAL ((int)cb->write (cb, PARM1, + MEMPTR (((unsigned long)PARM3 << 16) + | PARM2), PARM4)); + trace_output_16 (sd, result); break; case TARGET_SYS_lseek: trace_input ("", OP_REG, OP_REGP, OP_REG); - RETVAL32 (cr16_callback->lseek (cr16_callback, PARM1, - ((((long) PARM3) << 16) | PARM2), - PARM4)); - trace_output_32 (result); + RETVAL32 (cb->lseek (cb, PARM1, ((((long) PARM3) << 16) | PARM2), + PARM4)); + trace_output_32 (sd, result); break; case TARGET_SYS_close: trace_input ("", OP_REG, OP_VOID, OP_VOID); - RETVAL (cr16_callback->close (cr16_callback, PARM1)); - trace_output_16 (result); + RETVAL (cb->close (cb, PARM1)); + trace_output_16 (sd, result); break; case TARGET_SYS_open: trace_input ("", OP_MEMREF, OP_REG, OP_VOID); - RETVAL32 (cr16_callback->open (cr16_callback, - MEMPTR ((((unsigned long)PARM2)<<16)|PARM1), - PARM3)); - trace_output_32 (result); + RETVAL32 (cb->open (cb, MEMPTR ((((unsigned long)PARM2) << 16) + | PARM1), PARM3)); + trace_output_32 (sd, result); break; #ifdef TARGET_SYS_rename case TARGET_SYS_rename: trace_input ("", OP_MEMREF, OP_MEMREF, OP_VOID); - RETVAL (cr16_callback->rename (cr16_callback, - MEMPTR ((((unsigned long)PARM2)<<16) |PARM1), - MEMPTR ((((unsigned long)PARM4)<<16) |PARM3))); - trace_output_16 (result); + RETVAL (cb->rename (cb, MEMPTR ((((unsigned long)PARM2) << 16) | PARM1), + MEMPTR ((((unsigned long)PARM4) << 16) | PARM3))); + trace_output_16 (sd, result); break; #endif case 0x408: /* REVISIT: Added a dummy getenv call. */ trace_input ("", OP_MEMREF, OP_MEMREF, OP_VOID); - RETVAL32(NULL); - trace_output_32 (result); + RETVAL32 (0); + trace_output_32 (sd, result); break; case TARGET_SYS_exit: trace_input ("", OP_VOID, OP_VOID, OP_VOID); - State.exception = SIG_CR16_EXIT; - trace_output_void (); + trace_output_void (sd); + sim_engine_halt (sd, cpu, NULL, PC, sim_exited, GPR (2)); break; case TARGET_SYS_unlink: trace_input ("", OP_MEMREF, OP_VOID, OP_VOID); - RETVAL (cr16_callback->unlink (cr16_callback, - MEMPTR (((unsigned long)PARM2<<16)|PARM1))); - trace_output_16 (result); + RETVAL (cb->unlink (cb, MEMPTR (((unsigned long)PARM2 << 16) | PARM1))); + trace_output_16 (sd, result); break; @@ -5428,7 +5422,7 @@ OP_C_C () SLW (buf+28, host_stat.st_mtime); SLW (buf+36, host_stat.st_ctime); } - trace_output_16 (result); + trace_output_16 (sd, result); break; #endif @@ -5436,14 +5430,14 @@ OP_C_C () case TARGET_SYS_chown: trace_input ("", OP_VOID, OP_VOID, OP_VOID); RETVAL (chown (MEMPTR (PARM1), PARM2, PARM3)); - trace_output_16 (result); + trace_output_16 (sd, result); break; #endif case TARGET_SYS_chmod: trace_input ("", OP_VOID, OP_VOID, OP_VOID); RETVAL (chmod (MEMPTR (PARM1), PARM2)); - trace_output_16 (result); + trace_output_16 (sd, result); break; #ifdef TARGET_SYS_utime @@ -5452,7 +5446,7 @@ OP_C_C () /* Cast the second argument to void *, to avoid type mismatch if a prototype is present. */ RETVAL (utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2))); - trace_output_16 (result); + trace_output_16 (sd, result); break; #endif @@ -5460,16 +5454,31 @@ OP_C_C () case TARGET_SYS_time: trace_input ("