X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=sim%2Fcris%2Fcpuv10.h;h=5675d0afba97aef1371382e63ce91acde75052a4;hb=05e682e3be7e3d9d63ec358dcf8943fd200545cb;hp=3700dd5f77b741dc99ea17c0ea3c8d97095a2520;hpb=c9b3544acea166649878ad4a7afc502cf44a2c5a;p=deliverable%2Fbinutils-gdb.git

diff --git a/sim/cris/cpuv10.h b/sim/cris/cpuv10.h
index 3700dd5f77..5675d0afba 100644
--- a/sim/cris/cpuv10.h
+++ b/sim/cris/cpuv10.h
@@ -2,7 +2,7 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996-2007 Free Software Foundation, Inc.
+Copyright 1996-2020 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
@@ -17,8 +17,7 @@ This file is part of the GNU simulators.
    License for more details.
 
    You should have received a copy of the GNU General Public License along
-   with this program; if not, write to the Free Software Foundation, Inc.,
-   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+   with this program; if not, see <http://www.gnu.org/licenses/>.
 
 */
 
@@ -32,6 +31,12 @@ This file is part of the GNU simulators.
 /* Maximum number of instructions that can be executed in parallel.  */
 #define MAX_PARALLEL_INSNS 1
 
+/* The size of an "int" needed to hold an instruction word.
+   This is usually 32 bits, but some architectures needs 64 bits.  */
+typedef CGEN_INSN_INT CGEN_INSN_WORD;
+
+#include "cgen-engine.h"
+
 /* CPU state information.  */
 typedef struct {
   /* Hardware elements.  */
@@ -278,7 +283,7 @@ typedef struct {
 union sem_fields {
   struct { /* no operands */
     int empty;
-  } fmt_empty;
+  } sfmt_empty;
   struct { /*  */
     UINT f_u4;
   } sfmt_break;
@@ -346,44 +351,44 @@ union sem_fields {
     INT f_s6;
     UINT f_operand2;
     unsigned char in_Rd;
-    unsigned char out_h_gr_SI_index_of__DFLT_Rd;
+    unsigned char out_h_gr_SI_index_of__INT_Rd;
   } sfmt_andq;
   struct { /*  */
     INT f_indir_pc__dword;
     UINT f_operand2;
     unsigned char in_Rd;
-    unsigned char out_h_gr_SI_index_of__DFLT_Rd;
+    unsigned char out_h_gr_SI_index_of__INT_Rd;
   } sfmt_addcdr;
   struct { /*  */
     INT f_indir_pc__word;
     UINT f_operand2;
     unsigned char in_Rd;
-    unsigned char out_h_gr_SI_index_of__DFLT_Rd;
+    unsigned char out_h_gr_SI_index_of__INT_Rd;
   } sfmt_addcwr;
   struct { /*  */
     INT f_indir_pc__byte;
     UINT f_operand2;
     unsigned char in_Rd;
-    unsigned char out_h_gr_SI_index_of__DFLT_Rd;
+    unsigned char out_h_gr_SI_index_of__INT_Rd;
   } sfmt_addcbr;
   struct { /*  */
     UINT f_operand1;
     UINT f_operand2;
     unsigned char in_Ps;
-    unsigned char out_h_gr_SI_index_of__DFLT_Rs;
+    unsigned char out_h_gr_SI_index_of__INT_Rs;
   } sfmt_move_spr_rv10;
   struct { /*  */
     UINT f_operand2;
     UINT f_u6;
     unsigned char in_Rd;
-    unsigned char out_h_gr_SI_index_of__DFLT_Rd;
+    unsigned char out_h_gr_SI_index_of__INT_Rd;
   } sfmt_addq;
   struct { /*  */
     UINT f_operand1;
     UINT f_operand2;
     unsigned char in_Rd;
     unsigned char in_Rs;
-    unsigned char out_h_gr_SI_index_of__DFLT_Rd;
+    unsigned char out_h_gr_SI_index_of__INT_Rd;
   } sfmt_add_b_r;
   struct { /*  */
     UINT f_operand1;
@@ -425,7 +430,7 @@ union sem_fields {
     unsigned char in_Rd;
     unsigned char in_Rs;
     unsigned char out_Rs;
-    unsigned char out_h_gr_SI_if__SI_andif__DFLT_prefix_set_not__DFLT_inc_index_of__DFLT_Rs_index_of__DFLT_Rd;
+    unsigned char out_h_gr_SI_if__SI_andif__DFLT_prefix_set_not__UINT_inc_index_of__INT_Rs_index_of__INT_Rd;
   } sfmt_add_m_b_m;
   struct { /*  */
     UINT f_memmode;
@@ -590,7 +595,7 @@ struct scache {
   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
-  f_s6 = EXTRACT_LSB0_INT (insn, 16, 5, 6); \
+  f_s6 = EXTRACT_LSB0_SINT (insn, 16, 5, 6); \
 
 #define EXTRACT_IFMT_MOVECBR_VARS \
   UINT f_operand2; \
@@ -918,7 +923,7 @@ struct scache {
   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
   f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \
-  f_disp9_hi = EXTRACT_LSB0_INT (insn, 16, 0, 1); \
+  f_disp9_hi = EXTRACT_LSB0_SINT (insn, 16, 0, 1); \
   f_disp9_lo = EXTRACT_LSB0_UINT (insn, 16, 7, 7); \
 {\
   SI tmp_abslo;\
@@ -941,7 +946,7 @@ struct scache {
   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
   f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \
-  f_disp9_hi = EXTRACT_LSB0_INT (insn, 16, 0, 1); \
+  f_disp9_hi = EXTRACT_LSB0_SINT (insn, 16, 0, 1); \
   f_disp9_lo = EXTRACT_LSB0_UINT (insn, 16, 7, 7); \
 {\
   SI tmp_abslo;\
@@ -1052,7 +1057,7 @@ struct scache {
   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
   f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \
-  f_s8 = EXTRACT_LSB0_INT (insn, 16, 7, 8); \
+  f_s8 = EXTRACT_LSB0_SINT (insn, 16, 7, 8); \
 
 #define EXTRACT_IFMT_BDAPQPC_VARS \
   UINT f_operand2; \
@@ -1065,7 +1070,7 @@ struct scache {
   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
   f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \
-  f_s8 = EXTRACT_LSB0_INT (insn, 16, 7, 8); \
+  f_s8 = EXTRACT_LSB0_SINT (insn, 16, 7, 8); \
 
 /* Collection of various things for the trace handler to use.  */