X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=sim%2Fcris%2Fcpuv32.h;h=2b443bc0a50a5de59a6084bda36c69d0e8d5011a;hb=05e682e3be7e3d9d63ec358dcf8943fd200545cb;hp=93c942519ac540b15731e4b30b54168d506107b1;hpb=cf2bf87e2161ad7fb1a4fe4abc3e3b70bcaae4b5;p=deliverable%2Fbinutils-gdb.git

diff --git a/sim/cris/cpuv32.h b/sim/cris/cpuv32.h
index 93c942519a..2b443bc0a5 100644
--- a/sim/cris/cpuv32.h
+++ b/sim/cris/cpuv32.h
@@ -2,23 +2,22 @@
 
 THIS FILE IS MACHINE GENERATED WITH CGEN.
 
-Copyright 1996-2005 Free Software Foundation, Inc.
+Copyright 1996-2020 Free Software Foundation, Inc.
 
 This file is part of the GNU simulators.
 
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+   This file is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
 
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU General Public License for more details.
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
 
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, see <http://www.gnu.org/licenses/>.
 
 */
 
@@ -32,6 +31,12 @@ with this program; if not, write to the Free Software Foundation, Inc.,
 /* Maximum number of instructions that can be executed in parallel.  */
 #define MAX_PARALLEL_INSNS 1
 
+/* The size of an "int" needed to hold an instruction word.
+   This is usually 32 bits, but some architectures needs 64 bits.  */
+typedef CGEN_INSN_INT CGEN_INSN_WORD;
+
+#include "cgen-engine.h"
+
 /* CPU state information.  */
 typedef struct {
   /* Hardware elements.  */
@@ -409,7 +414,7 @@ typedef struct {
 union sem_fields {
   struct { /* no operands */
     int empty;
-  } fmt_empty;
+  } sfmt_empty;
   struct { /*  */
     UINT f_u4;
   } sfmt_break;
@@ -452,7 +457,7 @@ union sem_fields {
     INT f_indir_pc__dword;
     UINT f_operand2;
     unsigned char out_Pd;
-  } sfmt_move_c_sprv32_p0;
+  } sfmt_move_c_sprv32_p2;
   struct { /*  */
     INT f_s6;
     UINT f_operand2;
@@ -486,38 +491,38 @@ union sem_fields {
     INT f_s6;
     UINT f_operand2;
     unsigned char in_Rd;
-    unsigned char out_h_gr_SI_index_of__DFLT_Rd;
+    unsigned char out_h_gr_SI_index_of__INT_Rd;
   } sfmt_andq;
   struct { /*  */
     INT f_indir_pc__dword;
     UINT f_operand2;
     unsigned char in_Rd;
-    unsigned char out_h_gr_SI_index_of__DFLT_Rd;
+    unsigned char out_h_gr_SI_index_of__INT_Rd;
   } sfmt_addcdr;
   struct { /*  */
     INT f_indir_pc__word;
     UINT f_operand2;
     unsigned char in_Rd;
-    unsigned char out_h_gr_SI_index_of__DFLT_Rd;
+    unsigned char out_h_gr_SI_index_of__INT_Rd;
   } sfmt_addcwr;
   struct { /*  */
     INT f_indir_pc__byte;
     UINT f_operand2;
     unsigned char in_Rd;
-    unsigned char out_h_gr_SI_index_of__DFLT_Rd;
+    unsigned char out_h_gr_SI_index_of__INT_Rd;
   } sfmt_addcbr;
   struct { /*  */
     UINT f_operand2;
     UINT f_u6;
     unsigned char in_Rd;
-    unsigned char out_h_gr_SI_index_of__DFLT_Rd;
+    unsigned char out_h_gr_SI_index_of__INT_Rd;
   } sfmt_addq;
   struct { /*  */
     UINT f_operand1;
     UINT f_operand2;
     unsigned char in_Ps;
     unsigned char in_Rs;
-    unsigned char out_h_gr_SI_index_of__DFLT_Rs;
+    unsigned char out_h_gr_SI_index_of__INT_Rs;
   } sfmt_mcp;
   struct { /*  */
     UINT f_operand1;
@@ -558,7 +563,7 @@ union sem_fields {
     unsigned char in_Rd;
     unsigned char in_Rs;
     unsigned char out_Rs;
-    unsigned char out_h_gr_SI_index_of__DFLT_Rd;
+    unsigned char out_h_gr_SI_index_of__INT_Rd;
   } sfmt_addc_m;
   struct { /*  */
     UINT f_memmode;
@@ -567,7 +572,7 @@ union sem_fields {
     unsigned char in_Rd;
     unsigned char in_Rs;
     unsigned char out_Rs;
-    unsigned char out_h_gr_SI_if__SI_andif__DFLT_prefix_set_not__DFLT_inc_index_of__DFLT_Rs_index_of__DFLT_Rd;
+    unsigned char out_h_gr_SI_if__SI_andif__DFLT_prefix_set_not__UINT_inc_index_of__INT_Rs_index_of__INT_Rd;
   } sfmt_add_m_b_m;
   struct { /*  */
     UINT f_memmode;
@@ -703,7 +708,7 @@ struct scache {
   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
   f_opcode = EXTRACT_LSB0_UINT (insn, 16, 9, 4); \
-  f_s6 = EXTRACT_LSB0_INT (insn, 16, 5, 6); \
+  f_s6 = EXTRACT_LSB0_SINT (insn, 16, 5, 6); \
 
 #define EXTRACT_IFMT_MOVECBR_VARS \
   UINT f_operand2; \
@@ -882,7 +887,7 @@ struct scache {
   f_size = EXTRACT_LSB0_UINT (insn, 16, 5, 2); \
   f_operand1 = EXTRACT_LSB0_UINT (insn, 16, 3, 4); \
 
-#define EXTRACT_IFMT_MOVE_C_SPRV32_P0_VARS \
+#define EXTRACT_IFMT_MOVE_C_SPRV32_P2_VARS \
   INT f_indir_pc__dword; \
   UINT f_operand2; \
   UINT f_mode; \
@@ -892,7 +897,7 @@ struct scache {
   /* Contents of trailing part of insn.  */ \
   UINT word_1; \
   unsigned int length;
-#define EXTRACT_IFMT_MOVE_C_SPRV32_P0_CODE \
+#define EXTRACT_IFMT_MOVE_C_SPRV32_P2_CODE \
   length = 6; \
   word_1 = GETIMEMUSI (current_cpu, pc + 2); \
   f_indir_pc__dword = (0|(EXTRACT_LSB0_UINT (word_1, 32, 31, 32) << 0)); \
@@ -1076,7 +1081,7 @@ struct scache {
   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
   f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \
-  f_disp9_hi = EXTRACT_LSB0_INT (insn, 16, 0, 1); \
+  f_disp9_hi = EXTRACT_LSB0_SINT (insn, 16, 0, 1); \
   f_disp9_lo = EXTRACT_LSB0_UINT (insn, 16, 7, 7); \
 {\
   SI tmp_abslo;\
@@ -1099,7 +1104,7 @@ struct scache {
   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
   f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \
-  f_disp9_hi = EXTRACT_LSB0_INT (insn, 16, 0, 1); \
+  f_disp9_hi = EXTRACT_LSB0_SINT (insn, 16, 0, 1); \
   f_disp9_lo = EXTRACT_LSB0_UINT (insn, 16, 7, 7); \
 {\
   SI tmp_abslo;\
@@ -1245,7 +1250,7 @@ struct scache {
   f_operand2 = EXTRACT_LSB0_UINT (insn, 16, 15, 4); \
   f_mode = EXTRACT_LSB0_UINT (insn, 16, 11, 2); \
   f_opcode_hi = EXTRACT_LSB0_UINT (insn, 16, 9, 2); \
-  f_s8 = EXTRACT_LSB0_INT (insn, 16, 7, 8); \
+  f_s8 = EXTRACT_LSB0_SINT (insn, 16, 7, 8); \
 
 #define EXTRACT_IFMT_FIDXI_VARS \
   UINT f_operand2; \