X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=sim%2Fcris%2Fcrisv10f.c;h=273293c48b319a03af030be2ff056b5c33acab26;hb=17fc27167f678285d2f64040837b8cc41b6a664a;hp=67cd1429995a8cf0aae25e04a071c8f38939a03f;hpb=c5a570810022466eaa5e077cd1b8aa00d74706f1;p=deliverable%2Fbinutils-gdb.git

diff --git a/sim/cris/crisv10f.c b/sim/cris/crisv10f.c
index 67cd142999..273293c48b 100644
--- a/sim/cris/crisv10f.c
+++ b/sim/cris/crisv10f.c
@@ -1,5 +1,5 @@
 /* CRIS v10 simulator support code
-   Copyright (C) 2004-2012 Free Software Foundation, Inc.
+   Copyright (C) 2004-2020 Free Software Foundation, Inc.
    Contributed by Axis Communications.
 
 This file is part of the GNU simulators.
@@ -86,7 +86,7 @@ MY (deliver_interrupt) (SIM_CPU *current_cpu,
 			    GET_H_SR (H_SR_PRE_V32_IBR) + vec * 4, 4) == 0)
     {
       /* Nothing to do actually; either abort or send a signal.  */
-      sim_core_signal (sd, current_cpu, CIA_GET (current_cpu), 0, 4,
+      sim_core_signal (sd, current_cpu, CPU_PC_GET (current_cpu), 0, 4,
 		       GET_H_SR (H_SR_PRE_V32_IBR) + vec * 4,
 		       read_transfer, sim_core_unmapped_signal);
       return 0;