X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=sim%2Fcris%2Fcrisv10f.c;h=273293c48b319a03af030be2ff056b5c33acab26;hb=17fc27167f678285d2f64040837b8cc41b6a664a;hp=976badb56838e82dec3367d1fe93af841529b895;hpb=01f0fe5e0450edf168c1f612feb93cf588e4e7ea;p=deliverable%2Fbinutils-gdb.git

diff --git a/sim/cris/crisv10f.c b/sim/cris/crisv10f.c
index 976badb568..273293c48b 100644
--- a/sim/cris/crisv10f.c
+++ b/sim/cris/crisv10f.c
@@ -1,28 +1,28 @@
 /* CRIS v10 simulator support code
-   Copyright (C) 2004, 2005, 2006 Free Software Foundation, Inc.
+   Copyright (C) 2004-2020 Free Software Foundation, Inc.
    Contributed by Axis Communications.
 
 This file is part of the GNU simulators.
 
 This program is free software; you can redistribute it and/or modify
 it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
+the Free Software Foundation; either version 3 of the License, or
+(at your option) any later version.
 
 This program is distributed in the hope that it will be useful,
 but WITHOUT ANY WARRANTY; without even the implied warranty of
 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License along
-with this program; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+You should have received a copy of the GNU General Public License
+along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
 
 /* The infrastructure is based on that of i960.c.  */
 
 #define WANT_CPU_CRISV10F
 
 #define BASENUM 10
+#define CRIS_TLS_REGISTER 14
 #include "cris-tmpl.c"
 
 #if WITH_PROFILE_MODEL_P
@@ -86,7 +86,7 @@ MY (deliver_interrupt) (SIM_CPU *current_cpu,
 			    GET_H_SR (H_SR_PRE_V32_IBR) + vec * 4, 4) == 0)
     {
       /* Nothing to do actually; either abort or send a signal.  */
-      sim_core_signal (sd, current_cpu, CIA_GET (current_cpu), 0, 4,
+      sim_core_signal (sd, current_cpu, CPU_PC_GET (current_cpu), 0, 4,
 		       GET_H_SR (H_SR_PRE_V32_IBR) + vec * 4,
 		       read_transfer, sim_core_unmapped_signal);
       return 0;