X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=sim%2Fd10v%2FChangeLog;h=4294cd7f421f94c9de568834ba63b663c8d539dc;hb=b41dff6b54bc5c79a6435beb8c877839c631831d;hp=a2dade37ef7b9ad351b7c6acb390ae18bd452313;hpb=30d8198448410e80d56780c308eb788676377dd8;p=deliverable%2Fbinutils-gdb.git diff --git a/sim/d10v/ChangeLog b/sim/d10v/ChangeLog index a2dade37ef..4294cd7f42 100644 --- a/sim/d10v/ChangeLog +++ b/sim/d10v/ChangeLog @@ -1,3 +1,260 @@ +Wed Feb 11 16:53:49 1998 Andrew Cagney + + * simops.c (OP_5F00): Call error instead of abort for unknown + syscalls. + + * d10v_sim.h (enum): Define DPSW_CR. + + * simops.c (move_to_cr): Mask out hardwired zero bits in DPSW. + +Tue Feb 10 18:28:38 1998 Andrew Cagney + + * interp.c (sim_write_phys): Delete. + (sim_load): Call sim_load_file with sim_write and LMA. + +Mon Feb 9 12:05:01 1998 Andrew Cagney + + * interp.c: Rewrite xfer_mem so that it translates addresses as - + 0x00... - DMAP translated memory, 0x01... IMAP translated memory, + 0x10... - on-chip data, 0x11... - on-chip insn, 0x12... - unified + memory. + (pc_addr): Delete. + (imem_addr): New function - translate IMEM address. + (sim_resume): Use imem_addr to translate insn address, abort if + translation failed. + (sim_create_inferior): Write ARGV to memory using sim_write. Pass + argc/argv using r0/r1 not r2/r3. + (sim_size): Do not initialize IMAP/DMAP here. + (sim_open): Call sim_create_inferior and sim_size to initialize + the system. + (sim_create_inferior): Initialize IMAP/DMAP to hardware reset + defaults. + (init_system): Delete. + (xfer_mem, sim_fetch_register, sim_store_register): Do not call + init_system. + (decode_pc): Check prog_bfd is defined before looking up .text + section. + +Sun Feb 1 16:47:51 1998 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Sat Jan 31 18:15:41 1998 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Sun Jan 25 22:23:01 1998 Michael Meissner + + * interp.c (sim_stop_reason): Exit status is now in r0, not r2. + +Sat Jan 24 19:00:30 1998 Michael Meissner + + * d10v_sim.h (DEBUG_TRAP): New debug flag. + + * simops.c (OP_5F00): If DEBUG_TRAP is on, turn traps 0-14 into + printing the registers. + +Thu Jan 22 17:54:01 1998 Michael Meissner + + * simops.c (op_types): New ABI, args are r0..r3, system call # is + in r4. + (trace_{in,out}put_func): Ditto. + (OP_4900): Ditto. + (OP_24800000): Ditto. + (OP_4D00): Ditto. + (OP_5F00): Ditto. + +Thu Jan 22 14:30:36 1998 Fred Fish + + * interp.c (UMEM_SEGMENTS): New define, set to 128. + (sim_size): Use UMEM_SEGMENTS rather than hardwired constant. + (sim_close): Reset prog_bfd to NULL after closing it. Also + reset prog_bfd_was_opened_p after closing prog_bfd. + (sim_load): Reset prog_bfd_was_opened_p after closing prog_bfd. + (sim_create_inferior): Get start address from abfd not prog_bfd. + (xfer_mem): Do bounds checking on addresses and return zero length + read/write on bad addresses, rather than aborting. Prepare to + be able to handle xfers that cross segment boundaries, but not + yet implemented. Only emit debug message when d10v_debug is + set as well as DEBUG being defined. + +Mon Jan 19 22:26:29 1998 Doug Evans + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Mon Dec 15 23:17:11 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Ditto. + +Tue Dec 9 10:28:31 1997 Andrew Cagney + + * d10v_sim.h (RPT_S): Index cregs with RPT_S_CR not RPT_E_CR. + (BPSW): Ditto for BPSW_CR and not PSW_CR. + + * simops.c (OP_5F40): JMP to BPC instead of assigning PC directly. + +Mon Dec 8 12:58:33 1997 Andrew Cagney + + * simops.c (OP_5F00): From Martin Hunt . Change + reserved trap from 0 to 15. Add trap emulation code for 0-14. + + * interp.c (sim_resume): From Martin Hunt . Check + IBA for SDBT. + + * d10v_sim.h (AE_VECTOR_START, RIE_VECTOR_START, + SDBT_VECTOR_START, TRAP_VECTOR_START): Define. + + * simops.c (OP_5F00): For "trap", mask out all but SM bit in PSW, + use move_to_cr. + (OP_5F00): For "trap", update BPSW with move_to_cr. + +Fri Dec 5 15:31:17 1997 Andrew Cagney + + * d10v_sim.h (enum): Enumerate CR register names. + (enum): Enumerate PSW bit values. + (PSW): Obtain value uing move_from_cr. + (MOD_S, MOD_E, BPSW): Make r-values. + (move_from_cr, move_to_cr): Declare functions. + + * interp.c (sim_fetch_register, sim_store_register): Use + move_from_cr and move_to_cr for CR register transfers. + + * simops.c (move_from_cr, move_to_cr): New functions. + (OP_5F40): Move BPSW to PSW using move_to_cr and move_from_cr. + (OP_5600): For "mvtc", use function move_to_cr. + (OP_5200): For "mvfc", use function move_from_cr. + +Fri Dec 5 13:33:14 1997 Andrew Cagney + + * simops.c (OP_5600): For "mvtc" MOD_E and MOD_S, ensure that the + LSbit is zero. + +Thu Dec 4 09:21:05 1997 Doug Evans + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Thu Dec 4 16:51:02 1997 Andrew Cagney + + * d10v_sim.h (struct _state): Add DM - PSW debug mask. + + * simops.c (OP_5600): For "mvtc", save PSW.DM. + (OP_5200): Ditto for "mvfc". + +Wed Dec 3 17:27:06 1997 Andrew Cagney + + * d10v_sim.h (SEXT56): Define. + + * simops.c (OP_4201): For "rac", sign extend 56 bit value before + it is shifted. + + * d10v_sim.h (MAX32, MIN32, MASK32, MASK40): Re-define using + SIGNED64 macro. + +Tue Dec 2 15:38:34 1997 Fred Fish + + * interp.c (sim_resume): Call do_2_short with LEFT_FIRST or + RIGHT_FIRST, as appropriate, instead of hardcoded ints that + don't match enum values. + +Tue Dec 2 15:01:08 1997 Andrew Cagney + + * simops.c (OP_3A00): For "macu", perform multiply stage using 32 + bit rather than 16 bit precision. + (OP_3C00): For "mulxu", store unsigned product in ACC. + (OP_3800): For "msbu", subtract unsigned product from ACC, + (OP_0): For "sub", compute carry by comparing inputs. + +Tue Dec 2 11:04:37 1997 Andrew Cagney + + * simops.c (OP_1000): For "sub2w", compute carry by comparing + inputs. + +Mon Nov 17 20:57:21 1997 Andrew Cagney + + * simops.c (OP_1): Use 32 bit unsigned arithmetic for subtract, + carry indicated by value > 0xffff. + +Fri Nov 14 12:51:20 1997 Andrew Cagney + + * interp.c (sim_resume): Don't set up SIGINT handler using signal, + handled by client. + (sim_resume): Fix race condition of a direct assignment to + stop_simulator, conditionally call sim_stop. + (sim_stop_reason): Check stop_simulator returning SIGINT. Clear + stop_simulator ready for next sim_resume call. + (sim_ctrl_c): Delete function. + +Thu Nov 13 19:29:34 1997 Andrew Cagney + + * interp.c (sim_resume): For "REP", only check/update the PC when + a branch instruction has not been executed. + +Mon Nov 10 17:50:18 1997 Andrew Cagney + + * simops.c (OP_4201): "rachi". Sign extend bit 40 of ACC. Sign + extend bit 44 all constants. + (OP_4201): Replace GCC specific 0x..LL with SIGNED64 macro. + +Fri Oct 24 10:26:29 1997 Andrew Cagney + + * d10v_sim.h: Include sim-types.h. + (uint8, in816, uiny16, int32, uint32, int64, uint64): Typedef + using unsigned8 et.al. from sim-types.h. + (SEXT32, SEXT40, SEXT44, SEXT60): Replace GCC specific 0x..LL with + SIGNED64 macro. + +Wed Oct 22 14:43:00 1997 Andrew Cagney + + * interp.c (sim_write_phys): New function, write to physical + instead of virtual memory. + + * interp.c (sim_load): Pass lma_p and sim_write_phys to + sim_load_file. + +Mon Oct 13 10:55:07 1997 Fred Fish + + * simops.c (OP_6A01): Change OP_POSTDEC to OP_POSTINC and move + exception generation code to OP_6E01. + (OP_6E01): Change OP_POSTINC to OP_POSTDEC and insert exception + generation code. + +Sat Oct 11 09:02:08 1997 Fred Fish + + * simops.c (OP_6401): postdecrement on r15 is OK, remove exception. + (OP_6601): Ditto. + +Fri Oct 3 09:28:00 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Sat Sep 27 12:51:34 1997 Fred Fish + + * interp.c (pc_addr): Discard upper bit(s) of PC in case + IMAP1 selects unified memory. + * d10v_sim.h (INC_ADDR): Align MOD_E to increment before testing + for end condition. + +Wed Sep 24 17:38:57 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Tue Sep 23 11:04:38 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Mon Sep 22 11:46:20 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Fri Sep 19 17:45:25 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Mon Sep 15 17:36:15 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + Wed Sep 10 22:30:24 1997 Martin M. Hunt * interp.c (sim_resume): Increment PC at end of rep