X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=sim%2Fd10v%2Fsimops.c;h=dc0750338d24d2be30d2302656fa6a1949d5662a;hb=19431a02809968af77b87776ecd346574f7c0f87;hp=50f62305a6ad141d95f702ad2a421ff33d3283d0;hpb=11ec4de6695cf9144016b26b6ca193c6bcfa6504;p=deliverable%2Fbinutils-gdb.git

diff --git a/sim/d10v/simops.c b/sim/d10v/simops.c
index 50f62305a6..dc0750338d 100644
--- a/sim/d10v/simops.c
+++ b/sim/d10v/simops.c
@@ -1,13 +1,18 @@
+#include "config.h"
+
 #include <signal.h>
 #include <errno.h>
 #include <sys/types.h>
 #include <sys/stat.h>
+#ifdef HAVE_UNISTD_H
 #include <unistd.h>
+#endif
 
 #include "d10v_sim.h"
 #include "simops.h"
 #include "sys/syscall.h"
-#include "bfd.h"
+
+extern char *strrchr ();
 
 enum op_types {
   OP_VOID,
@@ -32,12 +37,83 @@ enum op_types {
   OP_POSTDEC,
   OP_POSTINC,
   OP_PREDEC,
+  OP_R0,
+  OP_R1,
   OP_R2,
-  OP_R3,
-  OP_R4,
-  OP_R2R3
+  OP_R0R1
 };
 
+
+void
+move_to_cr (int cr, reg_t val)
+{
+  switch (cr)
+    {
+    case PSW_CR:
+      State.SM = (val & PSW_SM_BIT) != 0;
+      State.EA = (val & PSW_EA_BIT) != 0;
+      State.DB = (val & PSW_DB_BIT) != 0;
+      State.DM = (val & PSW_DM_BIT) != 0;
+      State.IE = (val & PSW_IE_BIT) != 0;
+      State.RP = (val & PSW_RP_BIT) != 0;
+      State.MD = (val & PSW_MD_BIT) != 0;
+      State.FX = (val & PSW_FX_BIT) != 0;
+      State.ST = (val & PSW_ST_BIT) != 0;
+      State.F0 = (val & PSW_F0_BIT) != 0;
+      State.F1 = (val & PSW_F1_BIT) != 0;
+      State.C =  (val & PSW_C_BIT) != 0;
+      if (State.ST && !State.FX)
+	{
+	  (*d10v_callback->printf_filtered)
+	    (d10v_callback,
+	     "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
+	     PC<<2);
+	  State.exception = SIGILL;
+	}
+      State.cregs[cr] = (val & ~0x4032);
+      break;
+    case BPSW_CR:
+    case DPSW_CR:
+      State.cregs[cr] = (val & ~0x4032);
+      break;
+    case MOD_S_CR:
+    case MOD_E_CR:
+      State.cregs[cr] = (val & ~0x1);
+      break;
+    default:
+      State.cregs[cr] = val;
+      break;
+    }
+}
+
+reg_t
+move_from_cr (int cr)
+{
+  reg_t val = 0;
+  switch (cr)
+    {
+    case PSW_CR:
+      if (State.SM) val |= PSW_SM_BIT;
+      if (State.EA) val |= PSW_EA_BIT;
+      if (State.DB) val |= PSW_DB_BIT;
+      if (State.DM) val |= PSW_DM_BIT;
+      if (State.IE) val |= PSW_IE_BIT;
+      if (State.RP) val |= PSW_RP_BIT;
+      if (State.MD) val |= PSW_MD_BIT;
+      if (State.FX) val |= PSW_FX_BIT;
+      if (State.ST) val |= PSW_ST_BIT;
+      if (State.F0) val |= PSW_F0_BIT;
+      if (State.F1) val |= PSW_F1_BIT;
+      if (State.C) val |= PSW_C_BIT;
+      break;
+    default:
+      val = State.cregs[cr];
+      break;
+    }
+  return val;
+}
+
+
 #ifdef DEBUG
 static void trace_input_func PARAMS ((char *name,
 				      enum op_types in1,
@@ -50,12 +126,6 @@ static void trace_output_func PARAMS ((enum op_types result));
 
 #define trace_output(result) do { if (d10v_debug) trace_output_func (result); } while (0)
 
-static int init_text_p = 0;
-static asection *text;
-static bfd_vma text_start;
-static bfd_vma text_end;
-extern bfd *exec_bfd;
-
 #ifndef SIZE_INSTRUCTION
 #define SIZE_INSTRUCTION 8
 #endif
@@ -94,7 +164,6 @@ trace_input_func (name, in1, in2, in3)
   char *p;
   long tmp;
   char *type;
-  asection *s;
   const char *filename;
   const char *functionname;
   unsigned int linenumber;
@@ -111,6 +180,10 @@ trace_input_func (name, in1, in2, in3)
     case INS_RIGHT:		type = " R"; break;
     case INS_LEFT_PARALLEL:	type = "*L"; break;
     case INS_RIGHT_PARALLEL:	type = "*R"; break;
+    case INS_LEFT_COND_TEST:	type = "?L"; break;
+    case INS_RIGHT_COND_TEST:	type = "?R"; break;
+    case INS_LEFT_COND_EXE:	type = "&L"; break;
+    case INS_RIGHT_COND_EXE:	type = "&R"; break;
     case INS_LONG:		type = " B"; break;
     }
 
@@ -123,27 +196,14 @@ trace_input_func (name, in1, in2, in3)
 
   else
     {
-      if (!init_text_p)
-	{
-	  init_text_p = 1;
-	  for (s = exec_bfd->sections; s; s = s->next)
-	    if (strcmp (bfd_get_section_name (exec_bfd, s), ".text") == 0)
-	      {
-		text = s;
-		text_start = bfd_get_section_vma (exec_bfd, s);
-		text_end = text_start + bfd_section_size (exec_bfd, s);
-		break;
-	      }
-	}
-
       buf[0] = '\0';
-      byte_pc = (bfd_vma)PC << 2;
+      byte_pc = decode_pc ();
       if (text && byte_pc >= text_start && byte_pc < text_end)
 	{
 	  filename = (const char *)0;
 	  functionname = (const char *)0;
 	  linenumber = 0;
-	  if (bfd_find_nearest_line (exec_bfd, text, (struct symbol_cache_entry **)0, byte_pc - text_start,
+	  if (bfd_find_nearest_line (prog_bfd, text, (struct symbol_cache_entry **)0, byte_pc - text_start,
 				     &filename, &functionname, &linenumber))
 	    {
 	      p = buf;
@@ -165,7 +225,7 @@ trace_input_func (name, in1, in2, in3)
 		}
 	      else if (filename)
 		{
-		  char *q = (char *) strrchr (filename, '/');
+		  char *q = strrchr (filename, '/');
 		  sprintf (p, "%s ", (q) ? q+1 : filename);
 		  p += strlen (p);
 		}
@@ -193,9 +253,10 @@ trace_input_func (name, in1, in2, in3)
       switch (in[i])
 	{
 	case OP_VOID:
+	case OP_R0:
+	case OP_R1:
 	case OP_R2:
-	case OP_R3:
-	case OP_R4:
+	case OP_R0R1:
 	  break;
 
 	case OP_REG:
@@ -392,23 +453,33 @@ trace_input_func (name, in1, in2, in3)
 						 (uint16)State.regs[OP[++i]]);
 	      break;
 
-	    case OP_R2:
+	    case OP_R0:
 	      (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
-						 (uint16)State.regs[2]);
+						 (uint16)State.regs[0]);
 	      break;
 
-	    case OP_R3:
+	    case OP_R1:
 	      (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
-						 (uint16)State.regs[3]);
+						 (uint16)State.regs[1]);
 	      break;
 
-	    case OP_R4:
+	    case OP_R2:
 	      (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
-						 (uint16)State.regs[4]);
+						 (uint16)State.regs[2]);
+	      break;
+
+	    case OP_R0R1:
+	      (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
+						 (uint16)State.regs[0]);
+	      (*d10v_callback->printf_filtered) (d10v_callback, "%*s0x%.4x", SIZE_VALUES-6, "",
+						 (uint16)State.regs[1]);
+	      i++;
 	      break;
 	    }
 	}
     }
+
+  (*d10v_callback->flush_stdout) (d10v_callback);
 }
 
 static void
@@ -473,19 +544,21 @@ trace_output_func (result)
 					     State.F0 != 0, State.F1 != 0, State.C != 0);
 	  break;
 
-	case OP_R2:
+	case OP_R0:
 	  (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-6, "",
-					     (uint16)State.regs[2],
+					     (uint16)State.regs[0],
 					     State.F0 != 0, State.F1 != 0, State.C != 0);
 	  break;
 
-	case OP_R2R3:
+	case OP_R0R1:
 	  (*d10v_callback->printf_filtered) (d10v_callback, " :: %*s0x%.4x%.4x F0=%d F1=%d C=%d\n", SIZE_VALUES-10, "",
-					     (uint16)State.regs[2], (uint16)State.regs[3],
+					     (uint16)State.regs[0], (uint16)State.regs[1],
 					     State.F0 != 0, State.F1 != 0, State.C != 0);
 	  break;
 	}
     }
+
+  (*d10v_callback->flush_stdout) (d10v_callback);
 }
 
 #else
@@ -603,15 +676,12 @@ void
 OP_1200 ()
 {
   uint32 tmp;
-  uint32 tmp1 = (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1];
-  uint32 tmp2 = (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
+  uint32 a = (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1];
+  uint32 b = (State.regs[OP[1]]) << 16 | State.regs[OP[1]+1];
 
   trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID);
-  tmp = tmp1 + tmp2;
-  if ( (tmp < tmp1) || (tmp < tmp2) )
-    State.C = 1;
-  else
-    State.C = 0;
+  tmp = a + b;
+  State.C = (tmp < a);
   State.regs[OP[0]] = tmp >> 16;
   State.regs[OP[0]+1] = tmp & 0xFFFF;
   trace_output (OP_DREG);
@@ -621,14 +691,11 @@ OP_1200 ()
 void
 OP_1000000 ()
 {
-  uint16 tmp = State.regs[OP[0]];
-  State.regs[OP[0]] = State.regs[OP[1]] + OP[2];
+  uint16 tmp = State.regs[OP[1]];
+  State.regs[OP[0]] = tmp + OP[2];
 
   trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16);
-  if ( tmp > State.regs[OP[0]])
-    State.C = 1;
-  else
-    State.C = 0;
+  State.C = (State.regs[OP[0]] < tmp);
   trace_output (OP_REG);
 }
 
@@ -725,12 +792,10 @@ OP_201 ()
   uint tmp = State.regs[OP[0]];
   if (OP[1] == 0)
     OP[1] = 16;
+
   trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID);
   State.regs[OP[0]] += OP[1];
-  if (tmp > State.regs[OP[0]])
-    State.C = 1;
-  else
-    State.C = 0;
+  State.C = (State.regs[OP[0]] < tmp);
   trace_output (OP_REG);
 }
 
@@ -765,9 +830,9 @@ OP_C01 ()
 void
 OP_4900 ()
 {
-  trace_input ("bl.s", OP_CONSTANT8, OP_R2, OP_R3);
+  trace_input ("bl.s", OP_CONSTANT8, OP_R0, OP_R1);
   State.regs[13] = PC+1;
-  PC += SEXT8 (OP[0]);
+  JMP( PC + SEXT8 (OP[0]));
   trace_output (OP_VOID);
 }
 
@@ -775,9 +840,9 @@ OP_4900 ()
 void
 OP_24800000 ()
 {
-  trace_input ("bl.l", OP_CONSTANT16, OP_R2, OP_R3);
+  trace_input ("bl.l", OP_CONSTANT16, OP_R0, OP_R1);
   State.regs[13] = PC+1;
-  PC += OP[0];
+  JMP (PC + OP[0]);
   trace_output (OP_VOID);
 }
 
@@ -795,7 +860,7 @@ void
 OP_4800 ()
 {
   trace_input ("bra.s", OP_CONSTANT8, OP_VOID, OP_VOID);
-  PC += SEXT8 (OP[0]);
+  JMP (PC + SEXT8 (OP[0]));
   trace_output (OP_VOID);
 }
 
@@ -804,7 +869,7 @@ void
 OP_24000000 ()
 {
   trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID);
-  PC += OP[0];
+  JMP (PC + OP[0]);
   trace_output (OP_VOID);
 }
 
@@ -814,7 +879,7 @@ OP_4A00 ()
 {
   trace_input ("brf0f.s", OP_CONSTANT8, OP_VOID, OP_VOID);
   if (State.F0 == 0)
-    PC += SEXT8 (OP[0]);
+    JMP (PC + SEXT8 (OP[0]));
   trace_output (OP_FLAG);
 }
 
@@ -824,7 +889,7 @@ OP_25000000 ()
 {
   trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID);
   if (State.F0 == 0)
-    PC += OP[0];
+    JMP (PC + OP[0]);
   trace_output (OP_FLAG);
 }
 
@@ -834,7 +899,7 @@ OP_4B00 ()
 {
   trace_input ("brf0t.s", OP_CONSTANT8, OP_VOID, OP_VOID);
   if (State.F0)
-    PC += SEXT8 (OP[0]);
+    JMP (PC + SEXT8 (OP[0]));
   trace_output (OP_FLAG);
 }
 
@@ -844,7 +909,7 @@ OP_25800000 ()
 {
   trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID);
   if (State.F0)
-    PC += OP[0];
+    JMP (PC + OP[0]);
   trace_output (OP_FLAG);
 }
 
@@ -912,7 +977,7 @@ OP_1403 ()
 {
   trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID);
   State.F1 = State.F0;
-  State.F0 = (State.a[OP[0]] == State.a[OP[1]]) ? 1 : 0;
+  State.F0 = ((State.a[OP[0]] & MASK40) == (State.a[OP[1]] & MASK40)) ? 1 : 0;
   trace_output (OP_FLAG);
 }
 
@@ -1130,10 +1195,9 @@ OP_15002A02 ()
   int i;
 
   trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID);
-  if (SEXT40(State.a[OP[1]]) >= 0)
-    tmp = State.a[OP[1]];
-  else
-    tmp = ~(State.a[OP[1]]);
+  tmp = SEXT40(State.a[OP[1]]);
+  if (tmp < 0)
+    tmp = ~tmp & MASK40;
   
   foo = 0x4000000000LL;
   for (i=1;i<25;i++)
@@ -1154,9 +1218,9 @@ OP_15002A02 ()
 void
 OP_4D00 ()
 {
-  trace_input ("jl", OP_REG, OP_R2, OP_R3);
+  trace_input ("jl", OP_REG, OP_R0, OP_R1);
   State.regs[13] = PC+1;
-  PC = State.regs[OP[0]]; 
+  JMP (State.regs[OP[0]]);
   trace_output (OP_VOID);
 }
 
@@ -1165,10 +1229,10 @@ void
 OP_4C00 ()
 {
   trace_input ("jmp", OP_REG,
-	       (OP[0] == 13) ? OP_R2 : OP_VOID,
-	       (OP[0] == 13) ? OP_R3 : OP_VOID);
+	       (OP[0] == 13) ? OP_R0 : OP_VOID,
+	       (OP[0] == 13) ? OP_R1 : OP_VOID);
 
-  PC = State.regs[OP[0]]; 
+  JMP (State.regs[OP[0]]);
   trace_output (OP_VOID);
 }
 
@@ -1261,8 +1325,7 @@ void
 OP_38000000 ()
 {
   trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID);
-  State.regs[OP[0]] = RB (OP[1] + State.regs[OP[2]]);
-  SEXT8 (State.regs[OP[0]]);
+  State.regs[OP[0]] = SEXT8 (RB (OP[1] + State.regs[OP[2]]));
   trace_output (OP_REG);
 }
 
@@ -1271,8 +1334,7 @@ void
 OP_7000 ()
 {
   trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID);
-  State.regs[OP[0]] = RB (State.regs[OP[1]]);
-  SEXT8 (State.regs[OP[0]]);
+  State.regs[OP[0]] = SEXT8 (RB (State.regs[OP[1]]));
   trace_output (OP_REG);
 }
 
@@ -1289,7 +1351,7 @@ OP_4001 ()
 void
 OP_20000000 ()
 {
-  trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
+  trace_input ("ldi.l", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID);
   State.regs[OP[0]] = OP[1];
   trace_output (OP_REG);
 }
@@ -1361,13 +1423,17 @@ OP_1A00 ()
 void
 OP_3A00 ()
 {
-  int64 tmp;
+  uint64 tmp;
+  uint32 src1;
+  uint32 src2;
 
   trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
-  tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
+  src1 = (uint16) State.regs[OP[1]];
+  src2 = (uint16) State.regs[OP[2]];
+  tmp = src1 * src2;
   if (State.FX)
-    tmp = SEXT40( (tmp << 1) & MASK40);
-  State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
+    tmp = (tmp << 1);
+  State.a[OP[0]] = (State.a[OP[0]] + tmp) & MASK40;
   trace_output (OP_ACCUM);
 }
 
@@ -1523,14 +1589,18 @@ OP_1800 ()
 void
 OP_3800 ()
 {
-  int64 tmp;
+  uint64 tmp;
+  uint32 src1;
+  uint32 src2;
 
   trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG);
-  tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
+  src1 = (uint16) State.regs[OP[1]];
+  src2 = (uint16) State.regs[OP[2]];
+  tmp = src1 * src2;
   if (State.FX)
-    tmp = SEXT40( (tmp << 1) & MASK40);
+    tmp = (tmp << 1);
 
-  State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) - tmp) & MASK40;
+  State.a[OP[0]] = (State.a[OP[0]] - tmp) & MASK40;
   trace_output (OP_ACCUM);
 }
 
@@ -1582,11 +1652,14 @@ OP_1C00 ()
 void
 OP_3C00 ()
 {
-  int64 tmp;
+  uint64 tmp;
+  uint32 src1;
+  uint32 src2;
 
   trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG);
-  tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
-
+  src1 = (uint16) State.regs[OP[1]];
+  src2 = (uint16) State.regs[OP[2]];
+  tmp = src1 * src2;
   if (State.FX)
     tmp <<= 1;
 
@@ -1627,9 +1700,9 @@ OP_3E00 ()
 void
 OP_3E01 ()
 {
-  trace_input ("mv2wtac", OP_ACCUM_OUTPUT, OP_DREG, OP_VOID);
+  trace_input ("mv2wtac", OP_DREG, OP_ACCUM_OUTPUT, OP_VOID);
   State.a[OP[1]] = (SEXT16 (State.regs[OP[0]]) << 16 | State.regs[OP[0]+1]) & MASK40;
-  trace_output (OP_ACCUM);
+  trace_output (OP_ACCUM_REVERSE);
 }
 
 /* mvac */
@@ -1702,23 +1775,7 @@ void
 OP_5200 ()
 {
   trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID);
-  if (OP[1] == 0)
-    {
-      /* PSW is treated specially */
-      PSW = 0;
-      if (State.SM) PSW |= 0x8000;
-      if (State.EA) PSW |= 0x2000;
-      if (State.DB) PSW |= 0x1000;
-      if (State.IE) PSW |= 0x400;
-      if (State.RP) PSW |= 0x200;
-      if (State.MD) PSW |= 0x100;
-      if (State.FX) PSW |= 0x80;
-      if (State.ST) PSW |= 0x40;
-      if (State.F0) PSW |= 8;
-      if (State.F1) PSW |= 4;
-      if (State.C) PSW |= 1;
-    }
-  State.regs[OP[0]] = State.cregs[OP[1]];
+  State.regs[OP[0]] = move_from_cr (OP[1]);
   trace_output (OP_REG);
 }
 
@@ -1758,29 +1815,7 @@ void
 OP_5600 ()
 {
   trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID);
-  State.cregs[OP[1]] =  State.regs[OP[0]];
-  if (OP[1] == 0)
-    {
-      /* PSW is treated specially */
-      State.SM = (PSW & 0x8000) ? 1 : 0;
-      State.EA = (PSW & 0x2000) ? 1 : 0;
-      State.DB = (PSW & 0x1000) ? 1 : 0;
-      State.IE = (PSW & 0x400) ? 1 : 0;
-      State.RP = (PSW & 0x200) ? 1 : 0;
-      State.MD = (PSW & 0x100) ? 1 : 0;
-      State.FX = (PSW & 0x80) ? 1 : 0;
-      State.ST = (PSW & 0x40) ? 1 : 0;
-      State.F0 = (PSW & 8) ? 1 : 0;
-      State.F1 = (PSW & 4) ? 1 : 0;
-      State.C = PSW & 1;
-      if (State.ST && !State.FX)
-	{
-	  (*d10v_callback->printf_filtered) (d10v_callback,
-					     "ERROR at PC 0x%x: ST can only be set when FX is set.\n",
-					     PC<<2);
-	  State.exception = SIGILL;
-	}
-    }
+  move_to_cr (OP[1], State.regs[OP[0]]);
   trace_output (OP_CR_REVERSE);
 }
 
@@ -1830,12 +1865,40 @@ void
 OP_5E00 ()
 {
   trace_input ("nop", OP_VOID, OP_VOID, OP_VOID);
-  trace_output (OP_VOID);
 
-  if (State.ins_type == INS_LEFT || State.ins_type == INS_LEFT_PARALLEL)
-    left_nops++;
-  else
-    right_nops++;
+  ins_type_counters[ (int)State.ins_type ]--;	/* don't count nops as normal instructions */
+  switch (State.ins_type)
+    {
+    default:
+      ins_type_counters[ (int)INS_UNKNOWN ]++;
+      break;
+
+    case INS_LEFT_PARALLEL:
+      /* Don't count a parallel op that includes a NOP as a true parallel op */
+      ins_type_counters[ (int)INS_RIGHT_PARALLEL ]--;
+      ins_type_counters[ (int)INS_RIGHT ]++;
+      ins_type_counters[ (int)INS_LEFT_NOPS ]++;
+      break;
+
+    case INS_LEFT:
+    case INS_LEFT_COND_EXE:
+      ins_type_counters[ (int)INS_LEFT_NOPS ]++;
+      break;
+
+    case INS_RIGHT_PARALLEL:
+      /* Don't count a parallel op that includes a NOP as a true parallel op */
+      ins_type_counters[ (int)INS_LEFT_PARALLEL ]--;
+      ins_type_counters[ (int)INS_LEFT ]++;
+      ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
+      break;
+
+    case INS_RIGHT:
+    case INS_RIGHT_COND_EXE:
+      ins_type_counters[ (int)INS_RIGHT_NOPS ]++;
+      break;
+    }
+
+  trace_output (OP_VOID);
 }
 
 /* not */
@@ -1882,18 +1945,20 @@ OP_5201 ()
     }
 
   State.F1 = State.F0;
+  tmp = SEXT56 ((State.a[0] << 16) | (State.a[1] & 0xffff));
   if (shift >=0)
-    tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) << shift;
+    tmp <<= shift;
   else
-    tmp = ((State.a[0] << 16) | (State.a[1] & 0xffff)) >> -shift;
-  tmp = ( SEXT60(tmp) + 0x8000 ) >> 16;
-  if (tmp > MAX32)
+    tmp >>= -shift;
+  tmp += 0x8000;
+  tmp >>= 16; /* look at bits 0:43 */
+  if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
     {
       State.regs[OP[0]] = 0x7fff;
       State.regs[OP[0]+1] = 0xffff;
       State.F0 = 1;
     } 
-  else if (tmp < MIN32)
+  else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
     {
       State.regs[OP[0]] = 0x8000;
       State.regs[OP[0]+1] = 0;
@@ -1912,23 +1977,23 @@ OP_5201 ()
 void
 OP_4201 ()
 {
-  int64 tmp;
+  signed64 tmp;
   int shift = SEXT3 (OP[2]);
 
   trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3);
   State.F1 = State.F0;
   if (shift >=0)
-    tmp = SEXT44 (State.a[1]) << shift;
+    tmp = SEXT40 (State.a[OP[1]]) << shift;
   else
-    tmp = SEXT44 (State.a[1]) >> -shift;
+    tmp = SEXT40 (State.a[OP[1]]) >> -shift;
   tmp += 0x8000;
 
-  if (tmp > MAX32)
+  if (tmp > SEXT44 (SIGNED64 (0x0007fffffff)))
     {
       State.regs[OP[0]] = 0x7fff;
       State.F0 = 1;
     }
-  else if (tmp < 0xfff80000000LL)
+  else if (tmp < SEXT44 (SIGNED64 (0xfff80000000)))
     {
       State.regs[OP[0]] = 0x8000;
       State.F0 = 1;
@@ -1998,8 +2063,8 @@ void
 OP_5F40 ()
 {
   trace_input ("rte", OP_VOID, OP_VOID, OP_VOID);
-  PC = BPC;
-  PSW = BPSW;
+  move_to_cr (PSW_CR, BPSW);
+  JMP(BPC);
   trace_output (OP_VOID);
 }
 
@@ -2129,8 +2194,6 @@ OP_3201 ()
 void
 OP_460B ()
 {
-  uint16 tmp;
-
   trace_input ("slx", OP_REG, OP_FLAG, OP_VOID);
   State.regs[OP[0]] = (State.regs[OP[0]] << 1) | State.F0;
   trace_output (OP_REG);
@@ -2151,7 +2214,7 @@ OP_3400 ()
 {
   trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID);
   if ((State.regs[OP[1]] & 31) <= 16)
-    State.a[OP[0]] >>= (State.regs[OP[1]] & 31);
+    State.a[OP[0]] = (SEXT40(State.a[OP[0]]) >> (State.regs[OP[1]] & 31)) & MASK40;
   else
     {
       (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
@@ -2179,7 +2242,7 @@ OP_3401 ()
     OP[1] = 16;
 
   trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID);
-  State.a[OP[0]] >>= OP[1];
+  State.a[OP[0]] = (SEXT40(State.a[OP[0]]) >> OP[1]) & MASK40;
   trace_output (OP_ACCUM);
 }
 
@@ -2198,7 +2261,7 @@ OP_3000 ()
 {
   trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID);
   if ((State.regs[OP[1]] & 31) <= 16)
-    State.a[OP[0]] >>= (State.regs[OP[1]] & 31);
+    State.a[OP[0]] = (uint64)((State.a[OP[0]] & MASK40) >> (State.regs[OP[1]] & 31));
   else
     {
       (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: shift value %d too large.\n", State.regs[OP[1]] & 31);
@@ -2226,7 +2289,7 @@ OP_3001 ()
     OP[1] = 16;
 
   trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID);
-  State.a[OP[0]] >>= OP[1];
+  State.a[OP[0]] = (uint64)(State.a[OP[0]] & MASK40) >> OP[1];
   trace_output (OP_ACCUM);
 }
 
@@ -2291,6 +2354,12 @@ void
 OP_6C01 ()
 {
   trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID);
+  if ( OP[1] == 15 )
+    {
+      (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
+      State.exception = SIGILL;
+      return;
+    }
   SW (State.regs[OP[1]], State.regs[OP[0]]);
   INC_ADDR (State.regs[OP[1]],-2);
   trace_output (OP_VOID);
@@ -2337,7 +2406,7 @@ OP_6E1F ()
 void
 OP_6A01 ()
 {
-  trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID);
+  trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID);
   SW (State.regs[OP[1]],   State.regs[OP[0]]);
   SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
   INC_ADDR (State.regs[OP[1]],4);
@@ -2348,7 +2417,13 @@ OP_6A01 ()
 void
 OP_6E01 ()
 {
-  trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID);
+  trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID);
+  if ( OP[1] == 15 )
+    {
+      (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
+      State.exception = SIGILL;
+      return;
+    }
   SW (State.regs[OP[1]],   State.regs[OP[0]]);
   SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
   INC_ADDR (State.regs[OP[1]],-4);
@@ -2386,12 +2461,14 @@ OP_5FE0 ()
 void
 OP_0 ()
 {
-  int32 tmp;
+  uint16 tmp;
 
   trace_input ("sub", OP_REG, OP_REG, OP_VOID);
-  tmp = (int16)State.regs[OP[0]]- (int16)State.regs[OP[1]];
-  State.C = (tmp & 0xffff0000) ? 1 : 0;
-  State.regs[OP[0]] = tmp & 0xffff;
+  /* see ../common/sim-alu.h for a more extensive discussion on how to
+     compute the carry/overflow bits. */
+  tmp = State.regs[OP[0]] - State.regs[OP[1]];
+  State.C = ((uint16) State.regs[OP[0]] >= (uint16) State.regs[OP[1]]);
+  State.regs[OP[0]] = tmp;
   trace_output (OP_REG);
 }
 
@@ -2446,14 +2523,15 @@ OP_1003 ()
 void
 OP_1000 ()
 {
-  int64 tmp;
-  int32 a,b;
+  uint32 tmp,a,b;
 
   trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID);
-  a = (int32)((State.regs[OP[0]] << 16) | State.regs[OP[0]+1]);
-  b = (int32)((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
-  tmp = a-b;
-  State.C = (tmp & 0xffffffff00000000LL) ? 1 : 0;  
+  a = (uint32)((State.regs[OP[0]] << 16) | State.regs[OP[0]+1]);
+  b = (uint32)((State.regs[OP[1]] << 16) | State.regs[OP[1]+1]);
+  /* see ../common/sim-alu.h for a more extensive discussion on how to
+     compute the carry/overflow bits */
+  tmp = a - b;
+  State.C = (a >= b);
   State.regs[OP[0]] = (tmp >> 16) & 0xffff;
   State.regs[OP[0]+1] = tmp & 0xffff;
   trace_output (OP_DREG);
@@ -2549,14 +2627,18 @@ OP_17001002 ()
 void
 OP_1 ()
 {
-  int32 tmp;
+  unsigned tmp;
   if (OP[1] == 0)
     OP[1] = 16;
 
   trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID);
-  tmp = (int16)State.regs[OP[0]] - OP[1];
-  State.C = (tmp & 0xffff0000) ? 1 : 0;
-  State.regs[OP[0]] = tmp & 0xffff;  
+  /* see ../common/sim-alu.h for a more extensive discussion on how to
+     compute the carry/overflow bits. */
+  /* since OP[1] is never <= 0, -OP[1] == ~OP[1]+1 can never overflow */
+  tmp = ((unsigned)(unsigned16) State.regs[OP[0]]
+	 + (unsigned)(unsigned16) ( - OP[1]));
+  State.C = (tmp >= (1 << 16));
+  State.regs[OP[0]] = tmp;
   trace_output (OP_REG);
 }
 
@@ -2570,11 +2652,16 @@ OP_5F00 ()
   switch (OP[0])
     {
     default:
-#if 0
-      (*d10v_callback->printf_filtered) (d10v_callback, "Unknown trap code %d\n", OP[0]);
-      State.exception = SIGILL;
-#else
-      /* Use any other traps for batch debugging. */
+#if (DEBUG & DEBUG_TRAP) == 0
+      {
+	uint16 vec = OP[0] + TRAP_VECTOR_START;
+	BPC = PC + 1;
+	move_to_cr (BPSW_CR, PSW);
+	move_to_cr (PSW_CR, PSW & PSW_SM_BIT);
+	JMP (vec);
+	break;
+      }
+#else			/* if debugging use trap to print registers */
       {
 	int i;
 	static int first_time = 1;
@@ -2588,45 +2675,45 @@ OP_5F00 ()
 	    (*d10v_callback->printf_filtered) (d10v_callback, "         a0         a1 f0 f1 c\n");
 	  }
 
-      (*d10v_callback->printf_filtered) (d10v_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
+	(*d10v_callback->printf_filtered) (d10v_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
 
-      for (i = 0; i < 16; i++)
-	(*d10v_callback->printf_filtered) (d10v_callback, " %.4x", (int) State.regs[i]);
+	for (i = 0; i < 16; i++)
+	  (*d10v_callback->printf_filtered) (d10v_callback, " %.4x", (int) State.regs[i]);
 
-      for (i = 0; i < 2; i++)
-	(*d10v_callback->printf_filtered) (d10v_callback, " %.2x%.8lx",
-					   ((int)(State.a[i] >> 32) & 0xff),
-					   ((unsigned long)State.a[i]) & 0xffffffff);
+	for (i = 0; i < 2; i++)
+	  (*d10v_callback->printf_filtered) (d10v_callback, " %.2x%.8lx",
+					     ((int)(State.a[i] >> 32) & 0xff),
+					     ((unsigned long)State.a[i]) & 0xffffffff);
 
-      (*d10v_callback->printf_filtered) (d10v_callback, "  %d  %d %d\n",
-					 State.F0 != 0, State.F1 != 0, State.C != 0);
-      break;
+	(*d10v_callback->printf_filtered) (d10v_callback, "  %d  %d %d\n",
+					   State.F0 != 0, State.F1 != 0, State.C != 0);
+	(*d10v_callback->flush_stdout) (d10v_callback);
+	break;
+      }
 #endif
-
-    case 0:
-      /* Trap 0 is used for simulating low-level I/O */
+    case 15:			/* new system call trap */
+      /* Trap 15 is used for simulating low-level I/O */
       {
-	int save_errno = errno;	
 	errno = 0;
 
 /* Registers passed to trap 0 */
 
-#define FUNC   State.regs[6]	/* function number */
-#define PARM1  State.regs[2]	/* optional parm 1 */
-#define PARM2  State.regs[3]	/* optional parm 2 */
-#define PARM3  State.regs[4]	/* optional parm 3 */
-#define PARM4  State.regs[5]	/* optional parm 3 */
+#define FUNC   State.regs[4]	/* function number */
+#define PARM1  State.regs[0]	/* optional parm 1 */
+#define PARM2  State.regs[1]	/* optional parm 2 */
+#define PARM3  State.regs[2]	/* optional parm 3 */
+#define PARM4  State.regs[3]	/* optional parm 3 */
 
 /* Registers set by trap 0 */
 
-#define RETVAL State.regs[2]		/* return value */
-#define RETVAL_HIGH State.regs[2]	/* return value */
-#define RETVAL_LOW  State.regs[3]	/* return value */
+#define RETVAL State.regs[0]		/* return value */
+#define RETVAL_HIGH State.regs[0]	/* return value */
+#define RETVAL_LOW  State.regs[1]	/* return value */
 #define RETERR State.regs[4]		/* return error code */
 
 /* Turn a pointer in a register into a pointer into real memory. */
 
-#define MEMPTR(x) ((char *)((x) + State.imem))
+#define MEMPTR(x) ((char *)(dmem_addr(x)))
 
 	switch (FUNC)
 	  {
@@ -2634,13 +2721,13 @@ OP_5F00 ()
 	  case SYS_fork:
 	    RETVAL = fork ();
 	    trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID);
-	    trace_output (OP_R2);
+	    trace_output (OP_R0);
 	    break;
 
 	  case SYS_getpid:
 	    trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
 	    RETVAL = getpid ();
-	    trace_output (OP_R2);
+	    trace_output (OP_R0);
 	    break;
 
 	  case SYS_kill:
@@ -2760,12 +2847,13 @@ OP_5F00 ()
 		  {
 		    trace_output (OP_VOID);
 		    (*d10v_callback->printf_filtered) (d10v_callback, "Unknown signal %d\n", PARM2);
+		    (*d10v_callback->flush_stdout) (d10v_callback);
 		    State.exception = SIGILL;
 		  }
 		else
 		  {
 		    RETVAL = kill (PARM1, PARM2);
-		    trace_output (OP_R2);
+		    trace_output (OP_R0);
 		  }
 	      }
 	    break;
@@ -2773,15 +2861,17 @@ OP_5F00 ()
 	  case SYS_execve:
 	    RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
 			     (char **)MEMPTR (PARM3));
-	    trace_input ("<execve>", OP_R2, OP_R3, OP_R4);
-	    trace_output (OP_R2);
+	    trace_input ("<execve>", OP_R0, OP_R1, OP_R2);
+	    trace_output (OP_R0);
 	    break;
 
+#ifdef SYS_execv
 	  case SYS_execv:
 	    RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
-	    trace_input ("<execv>", OP_R2, OP_R3, OP_VOID);
-	    trace_output (OP_R2);
+	    trace_input ("<execv>", OP_R0, OP_R1, OP_VOID);
+	    trace_output (OP_R0);
 	    break;
+#endif
 
 	  case SYS_pipe:
 	    {
@@ -2793,11 +2883,12 @@ OP_5F00 ()
 	      SW (buf, host_fd[0]);
 	      buf += sizeof(uint16);
 	      SW (buf, host_fd[1]);
-	      trace_input ("<pipe>", OP_R2, OP_VOID, OP_VOID);
-	      trace_output (OP_R2);
+	      trace_input ("<pipe>", OP_R0, OP_VOID, OP_VOID);
+	      trace_output (OP_R0);
 	    }
 	  break;
 
+#ifdef SYS_wait
 	  case SYS_wait:
 	    {
 	      int status;
@@ -2805,15 +2896,16 @@ OP_5F00 ()
 	      RETVAL = wait (&status);
 	      if (PARM1)
 		SW (PARM1, status);
-	      trace_input ("<wait>", OP_R2, OP_VOID, OP_VOID);
-	      trace_output (OP_R2);
+	      trace_input ("<wait>", OP_R0, OP_VOID, OP_VOID);
+	      trace_output (OP_R0);
 	    }
 	  break;
+#endif
 #else
 	  case SYS_getpid:
 	    trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID);
 	    RETVAL = 1;
-	    trace_output (OP_R2);
+	    trace_output (OP_R0);
 	    break;
 
 	  case SYS_kill:
@@ -2826,8 +2918,8 @@ OP_5F00 ()
 	  case SYS_read:
 	    RETVAL = d10v_callback->read (d10v_callback, PARM1, MEMPTR (PARM2),
 					  PARM3);
-	    trace_input ("<read>", OP_R2, OP_R3, OP_R4);
-	    trace_output (OP_R2);
+	    trace_input ("<read>", OP_R0, OP_R1, OP_R2);
+	    trace_output (OP_R0);
 	    break;
 
 	  case SYS_write:
@@ -2837,8 +2929,8 @@ OP_5F00 ()
 	    else
 	      RETVAL = (int)d10v_callback->write (d10v_callback, PARM1,
 						  MEMPTR (PARM2), PARM3);
-	    trace_input ("<write>", OP_R2, OP_R3, OP_R4);
-	    trace_output (OP_R2);
+	    trace_input ("<write>", OP_R0, OP_R1, OP_R2);
+	    trace_output (OP_R0);
 	    break;
 
 	  case SYS_lseek:
@@ -2849,27 +2941,27 @@ OP_5F00 ()
 	      RETVAL_HIGH = ret >> 16;
 	      RETVAL_LOW  = ret & 0xffff;
 	    }
-	    trace_input ("<lseek>", OP_R2, OP_R3, OP_R4);
-	    trace_output (OP_R2R3);
+	    trace_input ("<lseek>", OP_R0, OP_R1, OP_R2);
+	    trace_output (OP_R0R1);
 	    break;
 
 	  case SYS_close:
 	    RETVAL = d10v_callback->close (d10v_callback, PARM1);
-	    trace_input ("<close>", OP_R2, OP_VOID, OP_VOID);
-	    trace_output (OP_R2);
+	    trace_input ("<close>", OP_R0, OP_VOID, OP_VOID);
+	    trace_output (OP_R0);
 	    break;
 
 	  case SYS_open:
 	    RETVAL = d10v_callback->open (d10v_callback, MEMPTR (PARM1), PARM2);
-	    trace_input ("<open>", OP_R2, OP_R3, OP_R4);
-	    trace_output (OP_R2);
-	    trace_input ("<open>", OP_R2, OP_R3, OP_R4);
-	    trace_output (OP_R2);
+	    trace_input ("<open>", OP_R0, OP_R1, OP_R2);
+	    trace_output (OP_R0);
+	    trace_input ("<open>", OP_R0, OP_R1, OP_R2);
+	    trace_output (OP_R0);
 	    break;
 
 	  case SYS_exit:
 	    State.exception = SIG_D10V_EXIT;
-	    trace_input ("<exit>", OP_R2, OP_VOID, OP_VOID);
+	    trace_input ("<exit>", OP_R0, OP_VOID, OP_VOID);
 	    trace_output (OP_VOID);
 	    break;
 
@@ -2898,71 +2990,50 @@ OP_5F00 ()
 	      SLW (buf+28, host_stat.st_mtime);
 	      SLW (buf+36, host_stat.st_ctime);
 	    }
-	    trace_input ("<stat>", OP_R2, OP_R3, OP_VOID);
-	    trace_output (OP_R2);
+	    trace_input ("<stat>", OP_R0, OP_R1, OP_VOID);
+	    trace_output (OP_R0);
 	    break;
 
 	  case SYS_chown:
 	    RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
-	    trace_input ("<chown>", OP_R2, OP_R3, OP_R4);
-	    trace_output (OP_R2);
+	    trace_input ("<chown>", OP_R0, OP_R1, OP_R2);
+	    trace_output (OP_R0);
 	    break;
 
 	  case SYS_chmod:
 	    RETVAL = chmod (MEMPTR (PARM1), PARM2);
-	    trace_input ("<chmod>", OP_R2, OP_R3, OP_R4);
-	    trace_output (OP_R2);
+	    trace_input ("<chmod>", OP_R0, OP_R1, OP_R2);
+	    trace_output (OP_R0);
 	    break;
 
+#ifdef SYS_utime
 	  case SYS_utime:
 	    /* Cast the second argument to void *, to avoid type mismatch
 	       if a prototype is present.  */
 	    RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
-	    trace_input ("<utime>", OP_R2, OP_R3, OP_R4);
-	    trace_output (OP_R2);
+	    trace_input ("<utime>", OP_R0, OP_R1, OP_R2);
+	    trace_output (OP_R0);
 	    break;
+#endif
 
+#ifdef SYS_time
 	  case SYS_time:
 	    {
 	      unsigned long ret = time (PARM1 ? MEMPTR (PARM1) : NULL);
 	      RETVAL_HIGH = ret >> 16;
 	      RETVAL_LOW  = ret & 0xffff;
 	    }
-	    trace_input ("<time>", OP_R2, OP_R3, OP_R4);
-	    trace_output (OP_R2R3);
+	    trace_input ("<time>", OP_R0, OP_R1, OP_R2);
+	    trace_output (OP_R0R1);
 	    break;
+#endif
 	    
 	  default:
 	    abort ();
 	  }
-	RETERR = d10v_callback->get_errno(d10v_callback);
+	RETERR = (RETVAL == (uint16) -1) ? d10v_callback->get_errno(d10v_callback) : 0;
 	break;
       }
-
-    case 1:
-      /* Trap 1 prints a string */
-      {
-	char *fstr = State.regs[2] + State.imem;
-	fputs (fstr, stdout);
-	break;
-      }
-
-    case 2:
-      /* Trap 2 calls printf */
-      {
-	char *fstr = State.regs[2] + State.imem;
-	(*d10v_callback->printf_filtered) (d10v_callback, fstr,
-					   (int16)State.regs[3],
-					   (int16)State.regs[4],
-					   (int16)State.regs[5]);
-	break;
-      }
-
-    case 3:
-      /* Trap 3 writes a character */
-      putchar (State.regs[2]);
-      break;
-      }
     }
 }